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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT64_stomp.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`define QBITS 2:0
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module FT64_stomp(branchmiss,branchmiss_thrd,missid,head0,thread_en,thrd,iqentry_v,stomp);
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parameter QENTRIES = 8;
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input branchmiss;
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input branchmiss_thrd;
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input [`QBITS] missid;
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input [`QBITS] head0;
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input thread_en;
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input [QENTRIES-1:0] thrd;
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input [QENTRIES-1:0] iqentry_v;
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output reg [QENTRIES-1:0] stomp;
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// Stomp logic for branch miss.
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integer n;
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reg [QENTRIES-1:0] stomp2;
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reg [`QBITS] contid;
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always @*
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if (branchmiss) begin
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stomp2 = 8'h00;
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// If missed at the head, all queue entries but the head are stomped on.
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if (head0==missid) begin
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for (n = 0; n < QENTRIES; n = n + 1)
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if (n!=missid) begin
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if (thread_en) begin
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if (thrd[n]==branchmiss_thrd)
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stomp2[n] = iqentry_v[n];
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end
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else
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stomp2[n] = iqentry_v[n];
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end
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end
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// If head0 is after the missid queue entries between the missid and
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// head0 are stomped on.
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else if (head0 > missid) begin
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for (n = 0; n < QENTRIES; n = n + 1)
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if (n > missid && n < head0) begin
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if (thread_en) begin
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if (thrd[n]==branchmiss_thrd)
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stomp2[n] = iqentry_v[n];
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end
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else
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stomp2[n] = iqentry_v[n];
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end
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end
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// Otherwise still queue entries between missid and head0 are stomped on
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// but the range 'wraps around'.
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else begin
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for (n = 0; n < QENTRIES; n = n + 1)
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if (n < head0) begin
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if (thread_en) begin
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if (thrd[n]==branchmiss_thrd)
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stomp2[n] = iqentry_v[n];
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end
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else
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stomp2[n] = iqentry_v[n];
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end
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for (n = 0; n < QENTRIES; n = n + 1)
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if (n >= missid + 1) begin
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if (thread_en) begin
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if (thrd[n]==branchmiss_thrd)
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stomp2[n] = iqentry_v[n];
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end
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else
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stomp2[n] = iqentry_v[n];
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end
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end
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/*
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// Not sure this logic is worth it for the few cases where the target
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// of the branch is in the queue already and there are no target
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// registers in code stepped over.
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if (BRANCH_PRED) begin
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// If the next instruction in the queue is the target for the miss
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// then no instructions should have been stomped on. Undo the stomp.
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// In this case there would be no branchmiss.
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if (iqentry_stomp2[idp1(missid)] && iqentry_pc[idp1(missid)]==misspc) begin
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iqentry_stomp = 8'h00;
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end
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else if (iqentry_stomp2[idp2(missid)] && iqentry_pc[idp2(missid)]==misspc) begin
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if (iqentry_tgt[idp1(missid)]==12'h000) begin
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iqentry_stomp = 8'h00;
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setpred[(missid+1)&7] = `INV;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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end
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else if (iqentry_stomp2[(missid+3)&7] && iqentry_pc[(missid+3)&7]==misspc) begin
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if (iqentry_tgt[(missid+1)&7]==8'h00 &&
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iqentry_tgt[(missid+2)&7]==8'h00) begin
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iqentry_stomp = 8'h00;
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setpred[(missid+1)&7] = `INV;
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setpred[(missid+2)&7] = `INV;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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end
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else if (iqentry_stomp2[(missid+4)&7] && iqentry_pc[(missid+4)&7]==misspc) begin
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if (iqentry_tgt[(missid+1)&7]==8'h00 &&
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iqentry_tgt[(missid+2)&7]==8'h00 &&
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iqentry_tgt[(missid+3)&7]==8'h00
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) begin
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iqentry_stomp = 8'h00;
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setpred[(missid+1)&7] = `INV;
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setpred[(missid+2)&7] = `INV;
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setpred[(missid+3)&7] = `INV;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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end
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else if (iqentry_stomp2[(missid+5)&7] && iqentry_pc[(missid+5)&7]==misspc) begin
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if (iqentry_tgt[(missid+1)&7]==8'h00 &&
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iqentry_tgt[(missid+2)&7]==8'h00 &&
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iqentry_tgt[(missid+3)&7]==8'h00 &&
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iqentry_tgt[(missid+4)&7]==8'h00
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) begin
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iqentry_stomp = 8'h00;
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setpred[(missid+1)&7] = `INV;
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setpred[(missid+2)&7] = `INV;
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setpred[(missid+3)&7] = `INV;
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setpred[(missid+4)&7] = `INV;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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end
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else if (iqentry_stomp2[(missid+6)&7] && iqentry_pc[(missid+6)&7]==misspc) begin
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if (iqentry_tgt[(missid+1)&7]==8'h00 &&
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iqentry_tgt[(missid+2)&7]==8'h00 &&
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iqentry_tgt[(missid+3)&7]==8'h00 &&
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iqentry_tgt[(missid+4)&7]==8'h00 &&
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iqentry_tgt[(missid+5)&7]==8'h00
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) begin
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iqentry_stomp = 8'h00;
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setpred[(missid+1)&7] = `INV;
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setpred[(missid+2)&7] = `INV;
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setpred[(missid+3)&7] = `INV;
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setpred[(missid+4)&7] = `INV;
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setpred[(missid+5)&7] = `INV;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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end
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else if (iqentry_stomp2[(missid+7)&7] && iqentry_pc[(missid+7)&7]==misspc) begin
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if (iqentry_tgt[(missid+1)&7]==8'h00 &&
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iqentry_tgt[(missid+2)&7]==8'h00 &&
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iqentry_tgt[(missid+3)&7]==8'h00 &&
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iqentry_tgt[(missid+4)&7]==8'h00 &&
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iqentry_tgt[(missid+5)&7]==8'h00 &&
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iqentry_tgt[(missid+6)&7]==8'h00
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) begin
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iqentry_stomp = 8'h00;
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setpred[(missid+1)&7] = `INV;
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setpred[(missid+2)&7] = `INV;
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setpred[(missid+3)&7] = `INV;
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setpred[(missid+4)&7] = `INV;
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setpred[(missid+5)&7] = `INV;
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setpred[(missid+6)&7] = `INV;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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end
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else
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iqentry_stomp = iqentry_stomp2;
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*/
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stomp = stomp2;
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end
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else begin
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stomp = {QENTRIES{1'b0}};
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end
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endmodule
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