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// ============================================================================
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT64_config.vh
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`define SIM 1'b1
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//`define SUPPORT_SMT 1'b1
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`define SUPPORT_VECTOR 1'b1
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//`define DEBUG_LOGIC 1'b1
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`define AMSB 31
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`define ABITS `AMSB:0
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`define QBITS 3:0
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`define QENTRIES 10 // changing this still requires changing code in FT64.
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`define XBITS 7:0
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//`define SUPPORT_DBG 1'b1
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`define FULL_ISSUE_LOGIC 1'b1
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`define WAYS 2 // number of ways parallel (not working yet)
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`define NUM_IDU 2 // number of instruction decode units (1-3)
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`define NUM_ALU 2 // number of ALU's (1-2)
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`define NUM_MEM 2 // number of memory queues (1-3)
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`define NUM_FPU 2 // number of floating-point units (0-2)
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`define NUM_CMT 2 // number of commit busses (1-2)
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// Comment out the following to remove FCU enhancements (branch predictor, BTB, RSB)
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`define FCU_ENH 1
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// Comment out the following to remove bypassing logic on the functional units
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`define FU_BYPASS 1
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// These are unit availability settings at reset.
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`define ID1_AVAIL 1'b1
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`define ID2_AVAIL 1'b1
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`define ID3_AVAIL 1'b0
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`define ALU0_AVAIL 1'b1
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`define ALU1_AVAIL 1'b1
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`define FPU1_AVAIL 1'b1
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`define FPU2_AVAIL 1'b0
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`define MEM1_AVAIL 1'b1
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`define MEM2_AVAIL 1'b1
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`define MEM3_AVAIL 1'b0
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`define FCU_AVAIL 1'b1
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// Comment out to remove the write buffer from the core.
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`define HAS_WB 1'b1
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`define WB_DEPTH 8 // must be one more than desired depth
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// Uncomment to allow SIMD operations
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`define SIMD 1'b1
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// Comment the following to disable registering the output of instruction decoders.
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// Inline decoding should not be registered.
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`define REGISTER_DECODE 1'b1
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//`define INLINE_DECODE 1'b1
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