OpenCores
URL https://opencores.org/ocsvn/thor/thor/trunk

Subversion Repositories thor

[/] [thor/] [trunk/] [FT64v5/] [rtl/] [fpUnit/] [fpdivr2.v] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 51 robfinch 
// ============================================================================
2 
//        __
3 
//   \\__/ o\    (C) 2006-2018  Robert Finch, Waterloo
4 
//    \  __ /    All rights reserved.
5 
//     \/_//     robfinch<remove>@finitron.ca
6 
//       ||
7 
//
8 
//      fpdivr2.v
9 
//    Radix 2 floating point divider primitive
10 
//
11 
//
12 
// This source file is free software: you can redistribute it and/or modify
13 
// it under the terms of the GNU Lesser General Public License as published
14 
// by the Free Software Foundation, either version 3 of the License, or
15 
// (at your option) any later version.
16 
//
17 
// This source file is distributed in the hope that it will be useful,
18 
// but WITHOUT ANY WARRANTY; without even the implied warranty of
19 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20 
// GNU General Public License for more details.
21 
//
22 
// You should have received a copy of the GNU General Public License
23 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
24 
//
25 
// ============================================================================
26 
 
27 
module fpdivr2(clk4x, ld, a, b, q, r, done, lzcnt);
28 
parameter WID = 112;
29 
parameter RADIX = 2;
30 
localparam WID1 = WID;//((WID+2)/3)*3;    // make width a multiple of three
31 
localparam DMSB = WID1-1;
32 
input clk4x;
33 
input ld;
34 
input [WID1-1:0] a;
35 
input [WID1-1:0] b;
36 
output reg [WID1*2-1:0] q = 0;
37 
output reg [WID1-1:0] r = 0;
38 
output reg done = 1'b0;
39 
output reg [7:0] lzcnt;
40 
 
41 
 
42 
reg [8:0] cnt;                           // iteration count
43 
reg [WID1*2-1:0] qi = 0;
44 
reg [DMSB+1:0] ri = 0;
45 
wire b0;
46 
reg gotnz;                                      // got a non-zero bit
47 
 
48 
reg done1;
49 
wire [7:0] maxcnt;
50 
assign b0 = b <= ri;
51 
wire [DMSB+1:0] r1 = b0 ? ri - b : ri;
52 
assign maxcnt = WID1*2;
53 
 
54 
// Done pulse for external circuit. Must span over 1 1x clock so that it's
55 
// recognized.
56 
always @(posedge clk4x)
57 
if (ld)
58 
        done <= 1'b0;
59 
else if (cnt==9'h1FE)
60 
        done <= 1'b1;
61 
else if (cnt==9'h1F7)
62 
        done <= 1'b0;
63 
 
64 
// Internal done pulse
65 
always @(posedge clk4x)
66 
begin
67 
        done1 <= 1'b0;
68 
        if (ld)
69 
                done1 <= 1'b0;
70 
        else if (cnt==9'h1FF)
71 
                done1 <= 1'b1;
72 
end
73 
 
74 
always @(posedge clk4x)
75 
if (ld)
76 
        cnt <= maxcnt;
77 
else if (cnt != 9'h1F7)
78 
        cnt <= cnt - 8'd1;
79 
 
80 
always @(posedge clk4x)
81 
if (ld)
82 
        gotnz <= 1'b0;
83 
else if (!cnt[8]) begin
84 
        if (b0)
85 
                gotnz <= 1'b1;
86 
end
87 
 
88 
wire cnt81;
89 
delay1 #(1) u1 (clk4x, 1'b1, cnt[8], cnt81);
90 
 
91 
always @(posedge clk4x)
92 
if (ld)
93 
        lzcnt <= 8'h00;
94 
else if (!cnt81) begin
95 
        if (b0==1'b0 && !gotnz)
96 
                lzcnt <= lzcnt + 8'd1;
97 
end
98 
 
99 
always @(posedge clk4x)
100 
if (ld)
101 
    qi <= {3'b0,a,{WID1{1'b0}}};
102 
else if (!cnt81)
103 
    qi[WID1*2-1:0] <= {qi[WID1*2-1-1:0],b0};
104 
 
105 
always @(posedge clk4x)
106 
if (ld)
107 
        ri <= 0;
108 
else if (!cnt81)
109 
    ri <= {r1[DMSB:0],qi[WID1*2-1]};
110 
 
111 
always @(posedge clk4x)
112 
if (done1)
113 
        q <= qi;
114 
always @(posedge clk4x)
115 
if (done1)
116 
        r <= ri;
117 
 
118 
endmodule
119 
 
120 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.