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// ============================================================================
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT64.v
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// Features include:
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// - 16/32/48 bit instructions
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// - vector instruction set,
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// - SIMD instructions
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// - data width of 64 bits
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// - 32 general purpose registers
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// - 32 floating point registers
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// - 32 vector registers, length 63
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// - powerful branch prediction
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// - branch target buffer (BTB)
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// - return address predictor (RSB)
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// - bus interface unit
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// - instruction and data caches
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// - asynchronous logic loops for issue and branch miss
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// re-written for synchronous operation, not as elegant
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// but required for operation in an FPGA
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// - fine-grained simultaneous multi-threading (SMT)
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Approx. 100,000 LUTs. 160,000 LC's.
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// 38,000LUTs???
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// ============================================================================
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//
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`include "FT64_config.vh"
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`include "FT64_defines.vh"
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module FT64(hartid, rst, clk_i, clk4x, tm_clk_i, irq_i, vec_i, bte_o, cti_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_o, dat_i,
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ol_o, pcr_o, pcr2_o, exv_i, rdv_i, wrv_i, icl_o, sr_o, cr_o, rbi_i, signal_i);
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input [63:0] hartid;
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input rst;
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input clk_i;
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input clk4x;
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input tm_clk_i;
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input [3:0] irq_i;
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input [7:0] vec_i;
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output reg [1:0] bte_o;
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output reg [2:0] cti_o;
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output reg cyc_o;
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output reg stb_o;
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input ack_i;
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input err_i;
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output reg we_o;
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output reg [7:0] sel_o;
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output reg [`ABITS] adr_o;
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output reg [63:0] dat_o;
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input [63:0] dat_i;
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output reg [1:0] ol_o;
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output [31:0] pcr_o;
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output [63:0] pcr2_o;
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input exv_i;
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input rdv_i;
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input wrv_i;
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output reg icl_o;
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output reg cr_o;
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output reg sr_o;
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input rbi_i;
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input [31:0] signal_i;
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parameter TM_CLKFREQ = 20000000;
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parameter QENTRIES = `QENTRIES;
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parameter RSTPC = 32'hFFFC0100;
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parameter BRKPC = 32'hFFFC0000;
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`ifdef SUPPORT_SMT
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parameter PREGS = 256; // number of physical registers - 1
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parameter AREGS = 256; // number of architectural registers
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`else
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parameter PREGS = 128;
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parameter AREGS = 128;
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`endif
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parameter RBIT = 11;
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parameter DEBUG = 1'b0;
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parameter NMAP = QENTRIES;
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parameter BRANCH_PRED = 1'b0;
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parameter SUP_TXE = 1'b0;
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parameter SUP_VECTOR = 1;
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parameter DBW = 64;
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parameter ABW = 32;
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parameter AMSB = ABW-1;
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parameter NTHREAD = 1;
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reg [3:0] i;
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integer n;
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integer j;
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genvar g;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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// Memory access sizes
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parameter byt = 3'd0;
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parameter wyde = 3'd1;
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parameter tetra = 3'd2;
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parameter octa = 3'd3;
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// IQ states
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parameter IQS_IDLE = 2'd0;
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parameter IQS_AGEN = 2'd1;
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parameter IQS_LDDONE = 2'd2;
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parameter IQS_S3 = 2'd3;
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wire clk;
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//BUFG uclkb1
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//(
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// .I(clk_i),
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// .O(clk)
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//);
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assign clk = clk_i;
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wire dc_ack;
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wire acki = ack_i|dc_ack;
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wire [RBIT:0] Ra0, Ra1;
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wire [RBIT:0] Rb0, Rb1;
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wire [RBIT:0] Rc0, Rc1;
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wire [RBIT:0] Rt0, Rt1;
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wire [63:0] rfoa0,rfob0,rfoc0,rfoc0a;
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wire [63:0] rfoa1,rfob1,rfoc1,rfoc1a;
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`ifdef SUPPORT_SMT
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wire [7:0] Ra0s = {Ra0[7:0]};
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wire [7:0] Ra1s = {Ra1[7:0]};
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wire [7:0] Rb0s = {Rb0[7:0]};
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wire [7:0] Rb1s = {Rb1[7:0]};
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wire [7:0] Rc0s = {Rc0[7:0]};
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wire [7:0] Rc1s = {Rc1[7:0]};
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wire [7:0] Rt0s = {Rt0[7:0]};
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wire [7:0] Rt1s = {Rt1[7:0]};
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`else
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wire [6:0] Ra0s = {Ra0[7],Ra0[5:0]};
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wire [6:0] Ra1s = {Ra1[7],Ra1[5:0]};
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wire [6:0] Rb0s = {Rb0[7],Rb0[5:0]};
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wire [6:0] Rb1s = {Rb1[7],Rb1[5:0]};
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wire [6:0] Rc0s = {Rc0[7],Rc0[5:0]};
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wire [6:0] Rc1s = {Rc1[7],Rc1[5:0]};
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wire [6:0] Rt0s = {Rt0[7],Rt0[5:0]};
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wire [6:0] Rt1s = {Rt1[7],Rt1[5:0]};
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/*
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wire [5:0] Ra0s = {Ra0[5:0]};
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wire [5:0] Ra1s = {Ra1[5:0]};
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wire [5:0] Rb0s = {Rb0[5:0]};
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wire [5:0] Rb1s = {Rb1[5:0]};
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wire [5:0] Rc0s = {Rc0[5:0]};
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wire [5:0] Rc1s = {Rc1[5:0]};
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wire [5:0] Rt0s = {Rt0[5:0]};
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wire [5:0] Rt1s = {Rt1[5:0]};
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*/
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`endif
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reg [63:0] ds [0:NTHREAD];
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reg [63:0] ss [0:NTHREAD];
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reg [63:0] ptrmask [0:NTHREAD];
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reg [63:0] ptrkey = " OBJECT";
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reg [63:0] wbrcd;
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reg [PREGS-1:0] rf_v;
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reg [4:0] rf_source[0:AREGS-1];
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initial begin
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for (n = 0; n < AREGS; n = n + 1)
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rf_source[n] = 5'd0;
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end
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wire [`ABITS] pc0;
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wire [`ABITS] pc1;
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wire [`ABITS] pc2;
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reg excmiss;
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reg [`ABITS] excmisspc;
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reg excthrd;
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reg exception_set;
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reg rdvq; // accumulated read violation
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reg errq; // accumulated err_i input status
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reg exvq;
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// Vector
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reg [5:0] vqe0, vqe1; // vector element being queued
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reg [5:0] vqet0, vqet1;
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reg [7:0] vl; // vector length
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reg [63:0] vm [0:7]; // vector mask registers
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reg [1:0] m2;
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reg [31:0] wb_merges;
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// CSR's
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reg [63:0] cr0;
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wire snr = cr0[17]; // sequence number reset
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wire dce = cr0[30]; // data cache enable
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wire bpe = cr0[32]; // branch predictor enable
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wire ctgtxe = cr0[33];
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reg [63:0] pmr;
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wire id1_available = pmr[0];
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wire id2_available = pmr[1];
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wire id3_available = pmr[2];
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wire alu0_available = pmr[8];
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wire alu1_available = pmr[9];
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wire fpu1_available = pmr[16];
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wire fpu2_available = pmr[17];
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wire mem1_available = pmr[24];
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wire mem2_available = pmr[25];
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wire mem3_available = pmr[26];
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wire fcu_available = pmr[32];
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// Simply setting this flag to zero should strip out almost all the logic
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// associated SMT.
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`ifdef SUPPORT_SMT
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wire thread_en = cr0[16];
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`else
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wire thread_en = 1'b0;
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`endif
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wire vechain = cr0[18];
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reg [7:0] fcu_timeout;
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reg [63:0] tick;
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reg [63:0] wc_time;
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reg [31:0] pcr;
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reg [63:0] pcr2;
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assign pcr_o = pcr;
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assign pcr2_o = pcr2;
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reg [63:0] aec;
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reg [15:0] cause[0:15];
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`ifdef SUPPORT_SMT
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reg [`ABITS] epc [0:NTHREAD];
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reg [`ABITS] epc0 [0:NTHREAD];
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reg [`ABITS] epc1 [0:NTHREAD];
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reg [`ABITS] epc2 [0:NTHREAD];
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reg [`ABITS] epc3 [0:NTHREAD];
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reg [`ABITS] epc4 [0:NTHREAD];
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reg [`ABITS] epc5 [0:NTHREAD];
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reg [`ABITS] epc6 [0:NTHREAD];
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reg [`ABITS] epc7 [0:NTHREAD];
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reg [`ABITS] epc8 [0:NTHREAD]; // exception pc and stack
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reg [63:0] mstatus [0:NTHREAD]; // machine status
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wire [3:0] im = mstatus[0][3:0];
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wire [1:0] ol [0:NTHREAD];
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wire [1:0] dl [0:NTHREAD];
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assign ol[0] = mstatus[0][5:3]; // operating level
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assign dl[0] = mstatus[0][21:20];
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wire [7:0] cpl [0:NTHREAD];
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assign cpl[0] = mstatus[0][13:6]; // current privilege level
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wire [5:0] rgs [0:NTHREAD];
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assign rgs[0] = mstatus[0][19:14];
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assign ol[1] = mstatus[1][5:3]; // operating level
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assign cpl[1] = mstatus[1][13:6]; // current privilege level
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assign rgs[1] = mstatus[1][19:14];
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assign dl[1] = mstatus[1][21:20];
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reg [15:0] ol_stack [0:NTHREAD];
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reg [31:0] im_stack [0:NTHREAD];
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reg [63:0] pl_stack [0:NTHREAD];
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reg [63:0] rs_stack [0:NTHREAD];
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reg [63:0] fr_stack [0:NTHREAD];
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wire mprv = mstatus[0][55];
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wire [5:0] fprgs = mstatus[0][25:20];
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//assign ol_o = mprv ? ol_stack[0][2:0] : ol[0];
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wire vca = mstatus[0][32]; // vector chaining active
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`else
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reg [`ABITS] epc ;
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reg [`ABITS] epc0 ;
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reg [`ABITS] epc1 ;
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reg [`ABITS] epc2 ;
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reg [`ABITS] epc3 ;
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reg [`ABITS] epc4 ;
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reg [`ABITS] epc5 ;
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reg [`ABITS] epc6 ;
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reg [`ABITS] epc7 ;
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reg [`ABITS] epc8 ; // exception pc and stack
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reg [63:0] mstatus ; // machine status
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wire [3:0] im = mstatus[3:0];
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wire [1:0] ol ;
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wire [1:0] dl;
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assign ol = mstatus[5:3]; // operating level
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assign dl = mstatus[21:20];
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wire [7:0] cpl ;
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assign cpl = mstatus[13:6]; // current privilege level
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wire [5:0] rgs ;
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assign rgs = mstatus[19:14];
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reg [15:0] ol_stack ;
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reg [31:0] im_stack ;
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reg [63:0] pl_stack ;
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reg [63:0] rs_stack ;
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reg [63:0] fr_stack ;
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wire mprv = mstatus[55];
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wire [5:0] fprgs = mstatus[25:20];
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//assign ol_o = mprv ? ol_stack[2:0] : ol;
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wire vca = mstatus[32]; // vector chaining active
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`endif
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reg [63:0] tcb;
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reg [`ABITS] badaddr[0:15];
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reg [`ABITS] tvec[0:7];
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reg [63:0] sema;
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reg [63:0] vm_sema;
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reg [63:0] cas; // compare and swap
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reg [63:0] ve_hold;
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reg isCAS, isAMO, isInc, isSpt, isRMW;
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reg [`QBITS] casid;
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reg [`ABITS] sbl, sbu;
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reg [4:0] regLR = 5'd29;
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reg [2:0] fp_rm;
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reg fp_inexe;
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reg fp_dbzxe;
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reg fp_underxe;
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reg fp_overxe;
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reg fp_invopxe;
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313 |
|
|
reg fp_giopxe;
|
314 |
|
|
reg fp_nsfp = 1'b0;
|
315 |
|
|
reg fp_fractie;
|
316 |
|
|
reg fp_raz;
|
317 |
48 |
robfinch |
|
318 |
51 |
robfinch |
reg fp_neg;
|
319 |
|
|
reg fp_pos;
|
320 |
|
|
reg fp_zero;
|
321 |
|
|
reg fp_inf;
|
322 |
48 |
robfinch |
|
323 |
51 |
robfinch |
reg fp_inex; // inexact exception
|
324 |
|
|
reg fp_dbzx; // divide by zero exception
|
325 |
|
|
reg fp_underx; // underflow exception
|
326 |
|
|
reg fp_overx; // overflow exception
|
327 |
|
|
reg fp_giopx; // global invalid operation exception
|
328 |
|
|
reg fp_sx; // summary exception
|
329 |
|
|
reg fp_swtx; // software triggered exception
|
330 |
|
|
reg fp_gx;
|
331 |
|
|
reg fp_invopx;
|
332 |
48 |
robfinch |
|
333 |
51 |
robfinch |
reg fp_infzerox;
|
334 |
|
|
reg fp_zerozerox;
|
335 |
|
|
reg fp_subinfx;
|
336 |
|
|
reg fp_infdivx;
|
337 |
|
|
reg fp_NaNCmpx;
|
338 |
|
|
reg fp_cvtx;
|
339 |
|
|
reg fp_sqrtx;
|
340 |
|
|
reg fp_snanx;
|
341 |
48 |
robfinch |
|
342 |
51 |
robfinch |
wire [31:0] fp_status = {
|
343 |
48 |
robfinch |
|
344 |
51 |
robfinch |
fp_rm,
|
345 |
|
|
fp_inexe,
|
346 |
|
|
fp_dbzxe,
|
347 |
|
|
fp_underxe,
|
348 |
|
|
fp_overxe,
|
349 |
|
|
fp_invopxe,
|
350 |
|
|
fp_nsfp,
|
351 |
48 |
robfinch |
|
352 |
51 |
robfinch |
fp_fractie,
|
353 |
|
|
fp_raz,
|
354 |
48 |
robfinch |
1'b0,
|
355 |
51 |
robfinch |
fp_neg,
|
356 |
|
|
fp_pos,
|
357 |
|
|
fp_zero,
|
358 |
|
|
fp_inf,
|
359 |
48 |
robfinch |
|
360 |
51 |
robfinch |
fp_swtx,
|
361 |
|
|
fp_inex,
|
362 |
|
|
fp_dbzx,
|
363 |
|
|
fp_underx,
|
364 |
|
|
fp_overx,
|
365 |
|
|
fp_giopx,
|
366 |
|
|
fp_gx,
|
367 |
|
|
fp_sx,
|
368 |
48 |
robfinch |
|
369 |
51 |
robfinch |
fp_cvtx,
|
370 |
|
|
fp_sqrtx,
|
371 |
|
|
fp_NaNCmpx,
|
372 |
|
|
fp_infzerox,
|
373 |
|
|
fp_zerozerox,
|
374 |
|
|
fp_infdivx,
|
375 |
|
|
fp_subinfx,
|
376 |
|
|
fp_snanx
|
377 |
48 |
robfinch |
};
|
378 |
|
|
|
379 |
51 |
robfinch |
reg [63:0] fpu_csr;
|
380 |
|
|
wire [5:0] fp_rgs = fpu_csr[37:32];
|
381 |
48 |
robfinch |
|
382 |
|
|
//reg [25:0] m[0:8191];
|
383 |
|
|
reg [3:0] panic; // indexes the message structure
|
384 |
|
|
reg [128:0] message [0:15]; // indexed by panic
|
385 |
|
|
|
386 |
|
|
wire int_commit;
|
387 |
|
|
reg StatusHWI;
|
388 |
49 |
robfinch |
reg [47:0] insn0, insn1, insn2;
|
389 |
|
|
wire [47:0] insn0a, insn1a, insn1b, insn2a, insn2b;
|
390 |
48 |
robfinch |
reg tgtq;
|
391 |
|
|
// Only need enough bits in the seqnence number to cover the instructions in
|
392 |
|
|
// the queue plus an extra count for skipping on branch misses. In this case
|
393 |
|
|
// that would be four bits minimum (count 0 to 8).
|
394 |
|
|
reg [31:0] seq_num;
|
395 |
|
|
reg [31:0] seq_num1;
|
396 |
|
|
wire [63:0] rdat0,rdat1,rdat2;
|
397 |
|
|
reg [63:0] xdati;
|
398 |
|
|
|
399 |
|
|
reg canq1, canq2;
|
400 |
|
|
reg queued1;
|
401 |
|
|
reg queued2;
|
402 |
|
|
reg queuedNop;
|
403 |
|
|
|
404 |
|
|
reg [47:0] codebuf[0:63];
|
405 |
|
|
reg [7:0] setpred;
|
406 |
|
|
|
407 |
|
|
// instruction queue (ROB)
|
408 |
|
|
reg [31:0] iqentry_sn [0:QENTRIES-1]; // instruction sequence number
|
409 |
|
|
reg [QENTRIES-1:0] iqentry_v; // entry valid? -- this should be the first bit
|
410 |
|
|
reg [QENTRIES-1:0] iqentry_iv; // instruction is valid
|
411 |
|
|
reg [4:0] iqentry_is [0:QENTRIES-1]; // source of instruction
|
412 |
|
|
reg [QENTRIES-1:0] iqentry_out; // instruction has been issued to an ALU ...
|
413 |
|
|
reg [QENTRIES-1:0] iqentry_done; // instruction result valid
|
414 |
|
|
reg [QENTRIES-1:0] iqentry_cmt;
|
415 |
|
|
reg [QENTRIES-1:0] iqentry_thrd; // which thread the instruction is in
|
416 |
|
|
reg [QENTRIES-1:0] iqentry_pt; // predict taken
|
417 |
51 |
robfinch |
reg [QENTRIES-1:0] iqentry_bt; // update branch target buffer
|
418 |
|
|
reg [QENTRIES-1:0] iqentry_jal;
|
419 |
48 |
robfinch |
reg [QENTRIES-1:0] iqentry_agen; // address-generate ... signifies that address is ready (only for LW/SW)
|
420 |
|
|
reg [1:0] iqentry_state [0:QENTRIES-1];
|
421 |
|
|
reg [QENTRIES-1:0] iqentry_alu = 8'h00; // alu type instruction
|
422 |
|
|
reg [QENTRIES-1:0] iqentry_alu0; // only valid on alu #0
|
423 |
|
|
reg [QENTRIES-1:0] iqentry_fpu; // floating point instruction
|
424 |
|
|
reg [QENTRIES-1:0] iqentry_fc; // flow control instruction
|
425 |
|
|
reg [QENTRIES-1:0] iqentry_canex = 8'h00; // true if it's an instruction that can exception
|
426 |
50 |
robfinch |
reg [QENTRIES-1:0] iqentry_oddball = 8'h00; // writes to register file
|
427 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_load; // is a memory load instruction
|
428 |
50 |
robfinch |
reg [QENTRIES-1:0] iqentry_loadv; // is a volatile memory load instruction
|
429 |
|
|
reg [QENTRIES-1:0] iqentry_store; // is a memory store instruction
|
430 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_preload; // is a memory preload instruction
|
431 |
|
|
reg [QENTRIES-1:0] iqentry_ldcmp;
|
432 |
|
|
reg [QENTRIES-1:0] iqentry_mem; // touches memory: 1 if LW/SW
|
433 |
|
|
reg [QENTRIES-1:0] iqentry_memndx; // indexed memory operation
|
434 |
50 |
robfinch |
reg [2:0] iqentry_memsz [0:QENTRIES-1]; // size of memory op
|
435 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_rmw; // memory RMW op
|
436 |
|
|
reg [QENTRIES-1:0] iqentry_memdb;
|
437 |
|
|
reg [QENTRIES-1:0] iqentry_memsb;
|
438 |
|
|
reg [QENTRIES-1:0] iqentry_rtop;
|
439 |
48 |
robfinch |
reg [QENTRIES-1:0] iqentry_sei;
|
440 |
|
|
reg [QENTRIES-1:0] iqentry_aq; // memory aquire
|
441 |
|
|
reg [QENTRIES-1:0] iqentry_rl; // memory release
|
442 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_shft48;
|
443 |
|
|
reg [QENTRIES-1:0] iqentry_jmp; // changes control flow: 1 if BEQ/JALR
|
444 |
48 |
robfinch |
reg [QENTRIES-1:0] iqentry_br; // Bcc (for predictor)
|
445 |
51 |
robfinch |
reg [QENTRIES-1:0] iqentry_ret;
|
446 |
|
|
reg [QENTRIES-1:0] iqentry_irq;
|
447 |
|
|
reg [QENTRIES-1:0] iqentry_brk;
|
448 |
|
|
reg [QENTRIES-1:0] iqentry_rti;
|
449 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_sync; // sync instruction
|
450 |
|
|
reg [QENTRIES-1:0] iqentry_fsync;
|
451 |
48 |
robfinch |
reg [QENTRIES-1:0] iqentry_rfw = 8'h00; // writes to register file
|
452 |
|
|
reg [7:0] iqentry_we [0:QENTRIES-1]; // enable strobe
|
453 |
|
|
reg [63:0] iqentry_res [0:QENTRIES-1]; // instruction result
|
454 |
|
|
reg [47:0] iqentry_instr[0:QENTRIES-1]; // instruction opcode
|
455 |
|
|
reg [2:0] iqentry_insln[0:QENTRIES-1]; // instruction length
|
456 |
|
|
reg [7:0] iqentry_exc [0:QENTRIES-1]; // only for branches ... indicates a HALT instruction
|
457 |
|
|
reg [RBIT:0] iqentry_tgt [0:QENTRIES-1]; // Rt field or ZERO -- this is the instruction's target (if any)
|
458 |
|
|
reg [7:0] iqentry_vl [0:QENTRIES-1];
|
459 |
|
|
reg [5:0] iqentry_ven [0:QENTRIES-1]; // vector element number
|
460 |
|
|
reg [63:0] iqentry_a0 [0:QENTRIES-1]; // argument 0 (immediate)
|
461 |
|
|
reg [63:0] iqentry_a1 [0:QENTRIES-1]; // argument 1
|
462 |
|
|
reg iqentry_a1_v [0:QENTRIES-1]; // arg1 valid
|
463 |
|
|
reg [4:0] iqentry_a1_s [0:QENTRIES-1]; // arg1 source (iq entry # with top bit representing ALU/DRAM bus)
|
464 |
|
|
reg [63:0] iqentry_a2 [0:QENTRIES-1]; // argument 2
|
465 |
|
|
reg iqentry_a2_v [0:QENTRIES-1]; // arg2 valid
|
466 |
|
|
reg [4:0] iqentry_a2_s [0:QENTRIES-1]; // arg2 source (iq entry # with top bit representing ALU/DRAM bus)
|
467 |
|
|
reg [63:0] iqentry_a3 [0:QENTRIES-1]; // argument 3
|
468 |
|
|
reg iqentry_a3_v [0:QENTRIES-1]; // arg3 valid
|
469 |
|
|
reg [4:0] iqentry_a3_s [0:QENTRIES-1]; // arg3 source (iq entry # with top bit representing ALU/DRAM bus)
|
470 |
49 |
robfinch |
reg [`ABITS] iqentry_pc [0:QENTRIES-1]; // program counter for this instruction
|
471 |
48 |
robfinch |
reg [RBIT:0] iqentry_Ra [0:QENTRIES-1];
|
472 |
|
|
reg [RBIT:0] iqentry_Rb [0:QENTRIES-1];
|
473 |
|
|
reg [RBIT:0] iqentry_Rc [0:QENTRIES-1];
|
474 |
|
|
// debugging
|
475 |
|
|
//reg [4:0] iqentry_ra [0:7]; // Ra
|
476 |
|
|
initial begin
|
477 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
478 |
|
|
iqentry_a1_s[n] = 5'd0;
|
479 |
|
|
iqentry_a2_s[n] = 5'd0;
|
480 |
|
|
iqentry_a3_s[n] = 5'd0;
|
481 |
|
|
end
|
482 |
|
|
|
483 |
|
|
wire [QENTRIES-1:0] iqentry_source = 8'h00;
|
484 |
|
|
reg [QENTRIES-1:0] iqentry_imm;
|
485 |
|
|
wire [QENTRIES-1:0] iqentry_memready;
|
486 |
|
|
wire [QENTRIES-1:0] iqentry_memopsvalid;
|
487 |
|
|
|
488 |
|
|
reg [QENTRIES-1:0] memissue = 8'h00;
|
489 |
|
|
reg [1:0] missued;
|
490 |
|
|
integer last_issue;
|
491 |
|
|
reg [QENTRIES-1:0] iqentry_memissue;
|
492 |
|
|
wire [QENTRIES-1:0] iqentry_stomp;
|
493 |
|
|
reg [3:0] stompedOnRets;
|
494 |
|
|
reg [QENTRIES-1:0] iqentry_alu0_issue;
|
495 |
|
|
reg [QENTRIES-1:0] iqentry_alu1_issue;
|
496 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_alu2_issue;
|
497 |
48 |
robfinch |
reg [QENTRIES-1:0] iqentry_id1issue;
|
498 |
|
|
reg [QENTRIES-1:0] iqentry_id2issue;
|
499 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_id3issue;
|
500 |
48 |
robfinch |
reg [1:0] iqentry_mem_islot [0:QENTRIES-1];
|
501 |
|
|
reg [QENTRIES-1:0] iqentry_fcu_issue;
|
502 |
49 |
robfinch |
reg [QENTRIES-1:0] iqentry_fpu1_issue;
|
503 |
|
|
reg [QENTRIES-1:0] iqentry_fpu2_issue;
|
504 |
48 |
robfinch |
|
505 |
|
|
wire [PREGS-1:1] livetarget;
|
506 |
|
|
wire [PREGS-1:1] iqentry_0_livetarget;
|
507 |
|
|
wire [PREGS-1:1] iqentry_1_livetarget;
|
508 |
|
|
wire [PREGS-1:1] iqentry_2_livetarget;
|
509 |
|
|
wire [PREGS-1:1] iqentry_3_livetarget;
|
510 |
|
|
wire [PREGS-1:1] iqentry_4_livetarget;
|
511 |
|
|
wire [PREGS-1:1] iqentry_5_livetarget;
|
512 |
|
|
wire [PREGS-1:1] iqentry_6_livetarget;
|
513 |
|
|
wire [PREGS-1:1] iqentry_7_livetarget;
|
514 |
|
|
wire [PREGS-1:1] iqentry_0_latestID;
|
515 |
|
|
wire [PREGS-1:1] iqentry_1_latestID;
|
516 |
|
|
wire [PREGS-1:1] iqentry_2_latestID;
|
517 |
|
|
wire [PREGS-1:1] iqentry_3_latestID;
|
518 |
|
|
wire [PREGS-1:1] iqentry_4_latestID;
|
519 |
|
|
wire [PREGS-1:1] iqentry_5_latestID;
|
520 |
|
|
wire [PREGS-1:1] iqentry_6_latestID;
|
521 |
|
|
wire [PREGS-1:1] iqentry_7_latestID;
|
522 |
|
|
wire [PREGS-1:1] iqentry_0_cumulative;
|
523 |
|
|
wire [PREGS-1:1] iqentry_1_cumulative;
|
524 |
|
|
wire [PREGS-1:1] iqentry_2_cumulative;
|
525 |
|
|
wire [PREGS-1:1] iqentry_3_cumulative;
|
526 |
|
|
wire [PREGS-1:1] iqentry_4_cumulative;
|
527 |
|
|
wire [PREGS-1:1] iqentry_5_cumulative;
|
528 |
|
|
wire [PREGS-1:1] iqentry_6_cumulative;
|
529 |
|
|
wire [PREGS-1:1] iqentry_7_cumulative;
|
530 |
|
|
wire [PREGS-1:1] iq0_out;
|
531 |
|
|
wire [PREGS-1:1] iq1_out;
|
532 |
|
|
wire [PREGS-1:1] iq2_out;
|
533 |
|
|
wire [PREGS-1:1] iq3_out;
|
534 |
|
|
wire [PREGS-1:1] iq4_out;
|
535 |
|
|
wire [PREGS-1:1] iq5_out;
|
536 |
|
|
wire [PREGS-1:1] iq6_out;
|
537 |
|
|
wire [PREGS-1:1] iq7_out;
|
538 |
|
|
|
539 |
|
|
reg [`QBITS] tail0;
|
540 |
|
|
reg [`QBITS] tail1;
|
541 |
|
|
reg [`QBITS] head0;
|
542 |
|
|
reg [`QBITS] head1;
|
543 |
|
|
reg [`QBITS] head2; // used only to determine memory-access ordering
|
544 |
|
|
reg [`QBITS] head3; // used only to determine memory-access ordering
|
545 |
|
|
reg [`QBITS] head4; // used only to determine memory-access ordering
|
546 |
|
|
reg [`QBITS] head5; // used only to determine memory-access ordering
|
547 |
|
|
reg [`QBITS] head6; // used only to determine memory-access ordering
|
548 |
|
|
reg [`QBITS] head7; // used only to determine memory-access ordering
|
549 |
|
|
|
550 |
|
|
wire take_branch0;
|
551 |
|
|
wire take_branch1;
|
552 |
|
|
|
553 |
|
|
reg [3:0] nop_fetchbuf;
|
554 |
|
|
wire fetchbuf; // determines which pair to read from & write to
|
555 |
49 |
robfinch |
wire [3:0] fb_panic;
|
556 |
48 |
robfinch |
|
557 |
|
|
wire [47:0] fetchbuf0_instr;
|
558 |
|
|
wire [2:0] fetchbuf0_insln;
|
559 |
49 |
robfinch |
wire [`ABITS] fetchbuf0_pc;
|
560 |
48 |
robfinch |
wire fetchbuf0_v;
|
561 |
|
|
wire fetchbuf0_thrd;
|
562 |
|
|
wire fetchbuf0_mem;
|
563 |
|
|
wire fetchbuf0_memld;
|
564 |
|
|
wire fetchbuf0_rfw;
|
565 |
|
|
wire [47:0] fetchbuf1_instr;
|
566 |
|
|
wire [2:0] fetchbuf1_insln;
|
567 |
49 |
robfinch |
wire [`ABITS] fetchbuf1_pc;
|
568 |
48 |
robfinch |
wire fetchbuf1_v;
|
569 |
|
|
wire fetchbuf1_thrd;
|
570 |
|
|
wire fetchbuf1_mem;
|
571 |
|
|
wire fetchbuf1_memld;
|
572 |
|
|
wire fetchbuf1_rfw;
|
573 |
|
|
|
574 |
|
|
wire [47:0] fetchbufA_instr;
|
575 |
49 |
robfinch |
wire [`ABITS] fetchbufA_pc;
|
576 |
48 |
robfinch |
wire fetchbufA_v;
|
577 |
|
|
wire [47:0] fetchbufB_instr;
|
578 |
49 |
robfinch |
wire [`ABITS] fetchbufB_pc;
|
579 |
48 |
robfinch |
wire fetchbufB_v;
|
580 |
|
|
wire [47:0] fetchbufC_instr;
|
581 |
49 |
robfinch |
wire [`ABITS] fetchbufC_pc;
|
582 |
48 |
robfinch |
wire fetchbufC_v;
|
583 |
|
|
wire [47:0] fetchbufD_instr;
|
584 |
49 |
robfinch |
wire [`ABITS] fetchbufD_pc;
|
585 |
48 |
robfinch |
wire fetchbufD_v;
|
586 |
|
|
|
587 |
|
|
//reg did_branchback0;
|
588 |
|
|
//reg did_branchback1;
|
589 |
|
|
|
590 |
|
|
reg id1_v;
|
591 |
|
|
reg [4:0] id1_id;
|
592 |
|
|
reg [47:0] id1_instr;
|
593 |
|
|
reg [5:0] id1_ven;
|
594 |
|
|
reg [7:0] id1_vl;
|
595 |
|
|
reg id1_thrd;
|
596 |
|
|
reg id1_pt;
|
597 |
|
|
reg [4:0] id1_Rt;
|
598 |
51 |
robfinch |
wire [143:0] id1_bus;
|
599 |
48 |
robfinch |
|
600 |
|
|
reg id2_v;
|
601 |
|
|
reg [4:0] id2_id;
|
602 |
|
|
reg [47:0] id2_instr;
|
603 |
|
|
reg [5:0] id2_ven;
|
604 |
|
|
reg [7:0] id2_vl;
|
605 |
|
|
reg id2_thrd;
|
606 |
|
|
reg id2_pt;
|
607 |
|
|
reg [4:0] id2_Rt;
|
608 |
51 |
robfinch |
wire [143:0] id2_bus;
|
609 |
48 |
robfinch |
|
610 |
49 |
robfinch |
reg id3_v;
|
611 |
|
|
reg [4:0] id3_id;
|
612 |
|
|
reg [47:0] id3_instr;
|
613 |
|
|
reg [5:0] id3_ven;
|
614 |
|
|
reg [7:0] id3_vl;
|
615 |
|
|
reg id3_thrd;
|
616 |
|
|
reg id3_pt;
|
617 |
|
|
reg [4:0] id3_Rt;
|
618 |
51 |
robfinch |
wire [143:0] id3_bus;
|
619 |
49 |
robfinch |
|
620 |
48 |
robfinch |
reg alu0_ld;
|
621 |
|
|
reg alu0_dataready;
|
622 |
|
|
wire alu0_done;
|
623 |
|
|
wire alu0_idle;
|
624 |
|
|
reg [3:0] alu0_sourceid;
|
625 |
|
|
reg [47:0] alu0_instr;
|
626 |
|
|
reg alu0_bt;
|
627 |
|
|
reg alu0_mem;
|
628 |
|
|
reg alu0_shft48;
|
629 |
|
|
reg [63:0] alu0_argA;
|
630 |
|
|
reg [63:0] alu0_argB;
|
631 |
|
|
reg [63:0] alu0_argC;
|
632 |
|
|
reg [63:0] alu0_argI; // only used by BEQ
|
633 |
|
|
reg [RBIT:0] alu0_tgt;
|
634 |
|
|
reg [5:0] alu0_ven;
|
635 |
|
|
reg alu0_thrd;
|
636 |
49 |
robfinch |
reg [`ABITS] alu0_pc;
|
637 |
48 |
robfinch |
wire [63:0] alu0_bus;
|
638 |
|
|
wire [63:0] alu0b_bus;
|
639 |
|
|
wire [3:0] alu0_id;
|
640 |
49 |
robfinch |
wire [`XBITS] alu0_exc;
|
641 |
48 |
robfinch |
wire alu0_v;
|
642 |
|
|
wire alu0_branchmiss;
|
643 |
49 |
robfinch |
wire [`ABITS] alu0_misspc;
|
644 |
48 |
robfinch |
|
645 |
|
|
reg alu1_ld;
|
646 |
|
|
reg alu1_dataready;
|
647 |
|
|
wire alu1_done;
|
648 |
|
|
wire alu1_idle;
|
649 |
|
|
reg [3:0] alu1_sourceid;
|
650 |
|
|
reg [47:0] alu1_instr;
|
651 |
|
|
reg alu1_bt;
|
652 |
|
|
reg alu1_mem;
|
653 |
|
|
reg alu1_shft48;
|
654 |
|
|
reg [63:0] alu1_argA;
|
655 |
|
|
reg [63:0] alu1_argB;
|
656 |
|
|
reg [63:0] alu1_argC;
|
657 |
|
|
reg [63:0] alu1_argI; // only used by BEQ
|
658 |
|
|
reg [RBIT:0] alu1_tgt;
|
659 |
|
|
reg [5:0] alu1_ven;
|
660 |
49 |
robfinch |
reg [`ABITS] alu1_pc;
|
661 |
48 |
robfinch |
reg alu1_thrd;
|
662 |
|
|
wire [63:0] alu1_bus;
|
663 |
|
|
wire [63:0] alu1b_bus;
|
664 |
|
|
wire [3:0] alu1_id;
|
665 |
49 |
robfinch |
wire [`XBITS] alu1_exc;
|
666 |
48 |
robfinch |
wire alu1_v;
|
667 |
|
|
wire alu1_branchmiss;
|
668 |
49 |
robfinch |
wire [`ABITS] alu1_misspc;
|
669 |
48 |
robfinch |
|
670 |
49 |
robfinch |
reg fpu1_ld;
|
671 |
|
|
reg fpu1_dataready = 1'b1;
|
672 |
|
|
wire fpu1_done = 1'b1;
|
673 |
|
|
wire fpu1_idle;
|
674 |
|
|
reg [3:0] fpu1_sourceid;
|
675 |
|
|
reg [47:0] fpu1_instr;
|
676 |
|
|
reg [63:0] fpu1_argA;
|
677 |
|
|
reg [63:0] fpu1_argB;
|
678 |
|
|
reg [63:0] fpu1_argC;
|
679 |
|
|
reg [63:0] fpu1_argI; // only used by BEQ
|
680 |
|
|
reg [RBIT:0] fpu1_tgt;
|
681 |
|
|
reg [`ABITS] fpu1_pc;
|
682 |
|
|
wire [63:0] fpu1_bus;
|
683 |
|
|
wire [3:0] fpu1_id;
|
684 |
|
|
wire [`XBITS] fpu1_exc = 9'h000;
|
685 |
|
|
wire fpu1_v;
|
686 |
|
|
wire [31:0] fpu1_status;
|
687 |
48 |
robfinch |
|
688 |
49 |
robfinch |
reg fpu2_ld;
|
689 |
|
|
reg fpu2_dataready = 1'b1;
|
690 |
|
|
wire fpu2_done = 1'b1;
|
691 |
|
|
wire fpu2_idle;
|
692 |
|
|
reg [3:0] fpu2_sourceid;
|
693 |
|
|
reg [47:0] fpu2_instr;
|
694 |
|
|
reg [63:0] fpu2_argA;
|
695 |
|
|
reg [63:0] fpu2_argB;
|
696 |
|
|
reg [63:0] fpu2_argC;
|
697 |
|
|
reg [63:0] fpu2_argI; // only used by BEQ
|
698 |
|
|
reg [RBIT:0] fpu2_tgt;
|
699 |
|
|
reg [`ABITS] fpu2_pc;
|
700 |
|
|
wire [63:0] fpu2_bus;
|
701 |
|
|
wire [3:0] fpu2_id;
|
702 |
|
|
wire [`XBITS] fpu2_exc = 9'h000;
|
703 |
|
|
wire fpu2_v;
|
704 |
|
|
wire [31:0] fpu2_status;
|
705 |
|
|
|
706 |
48 |
robfinch |
reg [63:0] waitctr;
|
707 |
|
|
reg fcu_ld;
|
708 |
|
|
reg fcu_dataready;
|
709 |
|
|
reg fcu_done;
|
710 |
|
|
reg fcu_idle = 1'b1;
|
711 |
|
|
reg [3:0] fcu_sourceid;
|
712 |
|
|
reg [47:0] fcu_instr;
|
713 |
|
|
reg [2:0] fcu_insln;
|
714 |
51 |
robfinch |
reg fcu_branch;
|
715 |
48 |
robfinch |
reg fcu_call;
|
716 |
51 |
robfinch |
reg fcu_ret;
|
717 |
|
|
reg fcu_jal;
|
718 |
|
|
reg fcu_brk;
|
719 |
|
|
reg fcu_rti;
|
720 |
48 |
robfinch |
reg fcu_bt;
|
721 |
|
|
reg [63:0] fcu_argA;
|
722 |
|
|
reg [63:0] fcu_argB;
|
723 |
|
|
reg [63:0] fcu_argC;
|
724 |
|
|
reg [63:0] fcu_argI; // only used by BEQ
|
725 |
|
|
reg [63:0] fcu_argT;
|
726 |
|
|
reg [63:0] fcu_argT2;
|
727 |
49 |
robfinch |
reg [`ABITS] fcu_pc;
|
728 |
|
|
reg [`ABITS] fcu_nextpc;
|
729 |
|
|
reg [`ABITS] fcu_brdisp;
|
730 |
48 |
robfinch |
wire [63:0] fcu_bus;
|
731 |
|
|
wire [3:0] fcu_id;
|
732 |
49 |
robfinch |
reg [`XBITS] fcu_exc;
|
733 |
48 |
robfinch |
wire fcu_v;
|
734 |
|
|
reg fcu_thrd;
|
735 |
|
|
reg fcu_branchmiss;
|
736 |
|
|
reg fcu_clearbm;
|
737 |
49 |
robfinch |
reg [`ABITS] fcu_misspc;
|
738 |
48 |
robfinch |
|
739 |
|
|
reg [63:0] rmw_argA;
|
740 |
|
|
reg [63:0] rmw_argB;
|
741 |
|
|
reg [63:0] rmw_argC;
|
742 |
|
|
wire [63:0] rmw_res;
|
743 |
|
|
reg [31:0] rmw_instr;
|
744 |
|
|
|
745 |
49 |
robfinch |
// write buffer
|
746 |
|
|
reg [63:0] wb_data [0:`WB_DEPTH-1];
|
747 |
|
|
reg [`ABITS] wb_addr [0:`WB_DEPTH-1];
|
748 |
|
|
reg [1:0] wb_ol [0:`WB_DEPTH-1];
|
749 |
|
|
reg [`WB_DEPTH-1:0] wb_v;
|
750 |
|
|
reg [`WB_DEPTH-1:0] wb_rmw;
|
751 |
|
|
reg [QENTRIES-1:0] wb_id [0:`WB_DEPTH-1];
|
752 |
|
|
reg [QENTRIES-1:0] wbo_id;
|
753 |
|
|
reg [7:0] wb_sel [0:`WB_DEPTH-1];
|
754 |
|
|
reg wb_en;
|
755 |
|
|
|
756 |
48 |
robfinch |
reg branchmiss = 1'b0;
|
757 |
|
|
reg branchmiss_thrd = 1'b0;
|
758 |
49 |
robfinch |
reg [`ABITS] misspc;
|
759 |
48 |
robfinch |
reg [`QBITS] missid;
|
760 |
|
|
|
761 |
|
|
wire take_branch;
|
762 |
|
|
wire take_branchA;
|
763 |
|
|
wire take_branchB;
|
764 |
|
|
wire take_branchC;
|
765 |
|
|
wire take_branchD;
|
766 |
|
|
|
767 |
|
|
wire dram_avail;
|
768 |
|
|
reg [2:0] dram0; // state of the DRAM request (latency = 4; can have three in pipeline)
|
769 |
|
|
reg [2:0] dram1; // state of the DRAM request (latency = 4; can have three in pipeline)
|
770 |
|
|
reg [2:0] dram2; // state of the DRAM request (latency = 4; can have three in pipeline)
|
771 |
|
|
reg [63:0] dram0_data;
|
772 |
49 |
robfinch |
reg [`ABITS] dram0_addr;
|
773 |
48 |
robfinch |
reg [31:0] dram0_seg;
|
774 |
|
|
reg [47:0] dram0_instr;
|
775 |
|
|
reg dram0_rmw;
|
776 |
|
|
reg dram0_preload;
|
777 |
|
|
reg [RBIT:0] dram0_tgt;
|
778 |
|
|
reg [3:0] dram0_id;
|
779 |
49 |
robfinch |
reg [`XBITS] dram0_exc;
|
780 |
48 |
robfinch |
reg dram0_unc;
|
781 |
|
|
reg [2:0] dram0_memsize;
|
782 |
|
|
reg dram0_load; // is a load operation
|
783 |
50 |
robfinch |
reg dram0_store;
|
784 |
48 |
robfinch |
reg [1:0] dram0_ol;
|
785 |
|
|
reg [63:0] dram1_data;
|
786 |
49 |
robfinch |
reg [`ABITS] dram1_addr;
|
787 |
48 |
robfinch |
reg [31:0] dram1_seg;
|
788 |
|
|
reg [47:0] dram1_instr;
|
789 |
|
|
reg dram1_rmw;
|
790 |
|
|
reg dram1_preload;
|
791 |
|
|
reg [RBIT:0] dram1_tgt;
|
792 |
|
|
reg [3:0] dram1_id;
|
793 |
49 |
robfinch |
reg [`XBITS] dram1_exc;
|
794 |
48 |
robfinch |
reg dram1_unc;
|
795 |
|
|
reg [2:0] dram1_memsize;
|
796 |
|
|
reg dram1_load;
|
797 |
50 |
robfinch |
reg dram1_store;
|
798 |
48 |
robfinch |
reg [1:0] dram1_ol;
|
799 |
|
|
reg [63:0] dram2_data;
|
800 |
49 |
robfinch |
reg [`ABITS] dram2_addr;
|
801 |
48 |
robfinch |
reg [31:0] dram2_seg;
|
802 |
|
|
reg [47:0] dram2_instr;
|
803 |
|
|
reg dram2_rmw;
|
804 |
|
|
reg dram2_preload;
|
805 |
|
|
reg [RBIT:0] dram2_tgt;
|
806 |
|
|
reg [3:0] dram2_id;
|
807 |
49 |
robfinch |
reg [`XBITS] dram2_exc;
|
808 |
48 |
robfinch |
reg dram2_unc;
|
809 |
|
|
reg [2:0] dram2_memsize;
|
810 |
|
|
reg dram2_load;
|
811 |
50 |
robfinch |
reg dram2_store;
|
812 |
48 |
robfinch |
reg [1:0] dram2_ol;
|
813 |
|
|
|
814 |
|
|
reg dramA_v;
|
815 |
|
|
reg [3:0] dramA_id;
|
816 |
|
|
reg [63:0] dramA_bus;
|
817 |
49 |
robfinch |
reg [`XBITS] dramA_exc;
|
818 |
48 |
robfinch |
reg dramB_v;
|
819 |
|
|
reg [3:0] dramB_id;
|
820 |
|
|
reg [63:0] dramB_bus;
|
821 |
49 |
robfinch |
reg [`XBITS] dramB_exc;
|
822 |
48 |
robfinch |
reg dramC_v;
|
823 |
|
|
reg [3:0] dramC_id;
|
824 |
|
|
reg [63:0] dramC_bus;
|
825 |
49 |
robfinch |
reg [`XBITS] dramC_exc;
|
826 |
48 |
robfinch |
|
827 |
|
|
wire outstanding_stores;
|
828 |
|
|
reg [63:0] I; // instruction count
|
829 |
|
|
|
830 |
|
|
reg commit0_v;
|
831 |
|
|
reg [4:0] commit0_id;
|
832 |
|
|
reg [RBIT:0] commit0_tgt;
|
833 |
|
|
reg [7:0] commit0_we = 8'h00;
|
834 |
|
|
reg [63:0] commit0_bus;
|
835 |
|
|
reg commit1_v;
|
836 |
|
|
reg [4:0] commit1_id;
|
837 |
|
|
reg [RBIT:0] commit1_tgt;
|
838 |
|
|
reg [7:0] commit1_we = 8'h00;
|
839 |
|
|
reg [63:0] commit1_bus;
|
840 |
|
|
|
841 |
|
|
reg [4:0] bstate;
|
842 |
|
|
parameter BIDLE = 5'd0;
|
843 |
|
|
parameter B1 = 5'd1;
|
844 |
|
|
parameter B2 = 5'd2;
|
845 |
|
|
parameter B3 = 5'd3;
|
846 |
|
|
parameter B4 = 5'd4;
|
847 |
|
|
parameter B5 = 5'd5;
|
848 |
|
|
parameter B6 = 5'd6;
|
849 |
|
|
parameter B7 = 5'd7;
|
850 |
|
|
parameter B8 = 5'd8;
|
851 |
|
|
parameter B9 = 5'd9;
|
852 |
|
|
parameter B10 = 5'd10;
|
853 |
|
|
parameter B11 = 5'd11;
|
854 |
|
|
parameter B12 = 5'd12;
|
855 |
|
|
parameter B13 = 5'd13;
|
856 |
|
|
parameter B14 = 5'd14;
|
857 |
|
|
parameter B15 = 5'd15;
|
858 |
|
|
parameter B16 = 5'd16;
|
859 |
|
|
parameter B17 = 5'd17;
|
860 |
|
|
parameter B18 = 5'd18;
|
861 |
|
|
parameter B19 = 5'd19;
|
862 |
|
|
parameter B2a = 5'd20;
|
863 |
|
|
parameter B2b = 5'd21;
|
864 |
|
|
parameter B2c = 5'd22;
|
865 |
|
|
parameter B2d = 5'd23;
|
866 |
|
|
parameter B20 = 5'd24;
|
867 |
|
|
parameter B21 = 5'd25;
|
868 |
|
|
reg [1:0] bwhich;
|
869 |
|
|
reg [3:0] icstate,picstate;
|
870 |
|
|
parameter IDLE = 4'd0;
|
871 |
|
|
parameter IC1 = 4'd1;
|
872 |
|
|
parameter IC2 = 4'd2;
|
873 |
|
|
parameter IC3 = 4'd3;
|
874 |
|
|
parameter IC4 = 4'd4;
|
875 |
|
|
parameter IC5 = 4'd5;
|
876 |
|
|
parameter IC6 = 4'd6;
|
877 |
|
|
parameter IC7 = 4'd7;
|
878 |
|
|
parameter IC8 = 4'd8;
|
879 |
|
|
parameter IC9 = 4'd9;
|
880 |
|
|
parameter IC10 = 4'd10;
|
881 |
|
|
parameter IC3a = 4'd11;
|
882 |
|
|
reg invic, invdc;
|
883 |
49 |
robfinch |
reg [1:0] icwhich;
|
884 |
|
|
reg icnxt,L2_nxt;
|
885 |
|
|
wire ihit0,ihit1,ihit2,ihitL2;
|
886 |
|
|
wire ihit = ihit0&ihit1&ihit2;
|
887 |
48 |
robfinch |
reg phit;
|
888 |
|
|
wire threadx;
|
889 |
|
|
always @*
|
890 |
|
|
phit <= ihit&&icstate==IDLE;
|
891 |
|
|
reg [2:0] iccnt;
|
892 |
49 |
robfinch |
reg L1_wr0,L1_wr1,L1_wr2;
|
893 |
48 |
robfinch |
reg L1_invline;
|
894 |
49 |
robfinch |
reg [8:0] L1_en;
|
895 |
48 |
robfinch |
reg [37:0] L1_adr, L2_adr;
|
896 |
49 |
robfinch |
reg [287:0] L2_rdat;
|
897 |
|
|
wire [287:0] L2_dato;
|
898 |
48 |
robfinch |
reg L2_xsel;
|
899 |
|
|
|
900 |
|
|
FT64_regfile2w6r_oc #(.RBIT(RBIT)) urf1
|
901 |
|
|
(
|
902 |
|
|
.clk(clk),
|
903 |
|
|
.clk4x(clk4x),
|
904 |
|
|
.wr0(commit0_v),
|
905 |
|
|
.wr1(commit1_v),
|
906 |
|
|
.we0(commit0_we),
|
907 |
|
|
.we1(commit1_we),
|
908 |
|
|
.wa0(commit0_tgt),
|
909 |
|
|
.wa1(commit1_tgt),
|
910 |
|
|
.i0(commit0_bus),
|
911 |
|
|
.i1(commit1_bus),
|
912 |
|
|
.rclk(~clk),
|
913 |
|
|
.ra0(Ra0),
|
914 |
|
|
.ra1(Rb0),
|
915 |
|
|
.ra2(Rc0),
|
916 |
|
|
.ra3(Ra1),
|
917 |
|
|
.ra4(Rb1),
|
918 |
|
|
.ra5(Rc1),
|
919 |
|
|
.o0(rfoa0),
|
920 |
|
|
.o1(rfob0),
|
921 |
|
|
.o2(rfoc0a),
|
922 |
|
|
.o3(rfoa1),
|
923 |
|
|
.o4(rfob1),
|
924 |
|
|
.o5(rfoc1a)
|
925 |
|
|
);
|
926 |
|
|
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
|
927 |
|
|
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
|
928 |
|
|
|
929 |
|
|
function [2:0] fnInsLength;
|
930 |
|
|
input [47:0] ins;
|
931 |
|
|
case(ins[7:6])
|
932 |
|
|
2'b00: fnInsLength = 3'd4;
|
933 |
|
|
2'b01: fnInsLength = 3'd6;
|
934 |
|
|
2'b10: fnInsLength = 3'd2;
|
935 |
|
|
2'b11: fnInsLength = 3'd2;
|
936 |
|
|
endcase
|
937 |
|
|
endfunction
|
938 |
|
|
|
939 |
49 |
robfinch |
wire [`ABITS] pc0plus6 = pc0 + 32'd6;
|
940 |
|
|
wire [`ABITS] pc0plus12 = pc0 + 32'd12;
|
941 |
48 |
robfinch |
|
942 |
|
|
`ifdef SUPPORT_SMT
|
943 |
49 |
robfinch |
generate begin : gInsnVar
|
944 |
|
|
if (`WAYS > 1) begin
|
945 |
|
|
assign insn1a = insn1b;
|
946 |
|
|
end
|
947 |
|
|
if (`WAYS > 2) begin
|
948 |
|
|
assign insn2a = insn2b;
|
949 |
|
|
end
|
950 |
|
|
end
|
951 |
|
|
endgenerate
|
952 |
48 |
robfinch |
`else
|
953 |
49 |
robfinch |
generate begin : gInsnVar
|
954 |
|
|
if (`WAYS > 1) begin
|
955 |
|
|
assign insn1a = {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
|
956 |
|
|
end
|
957 |
|
|
if (`WAYS > 2) begin
|
958 |
|
|
assign insn2a = {insn2b,insn1b,insn0a} >> {fnInsLength(insn0a) + fnInsLength(insn1a),3'b0};
|
959 |
|
|
end
|
960 |
|
|
end
|
961 |
|
|
endgenerate
|
962 |
48 |
robfinch |
`endif
|
963 |
|
|
|
964 |
|
|
FT64_L1_icache uic0
|
965 |
|
|
(
|
966 |
|
|
.rst(rst),
|
967 |
|
|
.clk(clk),
|
968 |
|
|
.nxt(icnxt),
|
969 |
|
|
.wr(L1_wr0),
|
970 |
|
|
.en(L1_en),
|
971 |
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0} : L1_adr),
|
972 |
|
|
.wadr(L1_adr),
|
973 |
|
|
.i(L2_rdat),
|
974 |
|
|
.o(insn0a),
|
975 |
|
|
.hit(ihit0),
|
976 |
|
|
.invall(invic),
|
977 |
|
|
.invline(L1_invline)
|
978 |
|
|
);
|
979 |
49 |
robfinch |
generate begin : gICacheInst
|
980 |
|
|
if (`WAYS > 1) begin
|
981 |
48 |
robfinch |
FT64_L1_icache uic1
|
982 |
|
|
(
|
983 |
|
|
.rst(rst),
|
984 |
|
|
.clk(clk),
|
985 |
|
|
.nxt(icnxt),
|
986 |
|
|
.wr(L1_wr1),
|
987 |
|
|
.en(L1_en),
|
988 |
|
|
`ifdef SUPPORT_SMT
|
989 |
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc1} : L1_adr),
|
990 |
|
|
`else
|
991 |
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0plus6} : L1_adr),
|
992 |
|
|
`endif
|
993 |
|
|
.wadr(L1_adr),
|
994 |
|
|
.i(L2_rdat),
|
995 |
|
|
.o(insn1b),
|
996 |
|
|
.hit(ihit1),
|
997 |
|
|
.invall(invic),
|
998 |
|
|
.invline(L1_invline)
|
999 |
|
|
);
|
1000 |
49 |
robfinch |
end
|
1001 |
|
|
else begin
|
1002 |
|
|
assign ihit1 = 1'b1;
|
1003 |
|
|
end
|
1004 |
|
|
if (`WAYS > 2) begin
|
1005 |
|
|
FT64_L1_icache uic2
|
1006 |
|
|
(
|
1007 |
|
|
.rst(rst),
|
1008 |
|
|
.clk(clk),
|
1009 |
|
|
.nxt(icnxt),
|
1010 |
|
|
.wr(L1_wr2),
|
1011 |
|
|
.en(L1_en),
|
1012 |
|
|
`ifdef SUPPORT_SMT
|
1013 |
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc2} : L1_adr),
|
1014 |
|
|
`else
|
1015 |
|
|
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0plus12} : L1_adr),
|
1016 |
|
|
`endif
|
1017 |
|
|
.wadr(L1_adr),
|
1018 |
|
|
.i(L2_rdat),
|
1019 |
|
|
.o(insn2b),
|
1020 |
|
|
.hit(ihit2),
|
1021 |
|
|
.invall(invic),
|
1022 |
|
|
.invline(L1_invline)
|
1023 |
|
|
);
|
1024 |
|
|
end
|
1025 |
|
|
else
|
1026 |
|
|
assign ihit2 = 1'b1;
|
1027 |
|
|
end
|
1028 |
|
|
endgenerate
|
1029 |
|
|
|
1030 |
48 |
robfinch |
FT64_L2_icache uic2
|
1031 |
|
|
(
|
1032 |
|
|
.rst(rst),
|
1033 |
|
|
.clk(clk),
|
1034 |
|
|
.nxt(L2_nxt),
|
1035 |
|
|
.wr(bstate==B7 && ack_i),
|
1036 |
|
|
.xsel(L2_xsel),
|
1037 |
|
|
.adr(L2_adr),
|
1038 |
|
|
.cnt(iccnt),
|
1039 |
|
|
.exv_i(exvq),
|
1040 |
|
|
.i(dat_i),
|
1041 |
|
|
.err_i(errq),
|
1042 |
|
|
.o(L2_dato),
|
1043 |
49 |
robfinch |
.hit(ihitL2),
|
1044 |
48 |
robfinch |
.invall(invic),
|
1045 |
|
|
.invline()
|
1046 |
|
|
);
|
1047 |
|
|
|
1048 |
|
|
wire predict_taken;
|
1049 |
|
|
wire predict_taken0;
|
1050 |
|
|
wire predict_taken1;
|
1051 |
|
|
wire predict_takenA;
|
1052 |
|
|
wire predict_takenB;
|
1053 |
|
|
wire predict_takenC;
|
1054 |
|
|
wire predict_takenD;
|
1055 |
|
|
wire predict_takenA1;
|
1056 |
|
|
wire predict_takenB1;
|
1057 |
|
|
wire predict_takenC1;
|
1058 |
|
|
wire predict_takenD1;
|
1059 |
|
|
|
1060 |
49 |
robfinch |
wire [`ABITS] btgtA, btgtB, btgtC, btgtD;
|
1061 |
48 |
robfinch |
wire btbwr0 = iqentry_v[head0] && iqentry_done[head0] &&
|
1062 |
|
|
(
|
1063 |
51 |
robfinch |
iqentry_jal[head0] ||
|
1064 |
|
|
iqentry_brk[head0] ||
|
1065 |
|
|
iqentry_rti[head0]);
|
1066 |
48 |
robfinch |
wire btbwr1 = iqentry_v[head1] && iqentry_done[head1] &&
|
1067 |
|
|
(
|
1068 |
51 |
robfinch |
iqentry_jal[head1] ||
|
1069 |
|
|
iqentry_brk[head1] ||
|
1070 |
|
|
iqentry_rti[head1]);
|
1071 |
48 |
robfinch |
|
1072 |
50 |
robfinch |
wire fcu_clk;
|
1073 |
49 |
robfinch |
`ifdef FCU_ENH
|
1074 |
50 |
robfinch |
//BUFGCE ufcuclk
|
1075 |
|
|
//(
|
1076 |
|
|
// .I(clk_i),
|
1077 |
|
|
// .CE(fcu_available),
|
1078 |
|
|
// .O(fcu_clk)
|
1079 |
|
|
//);
|
1080 |
49 |
robfinch |
`endif
|
1081 |
50 |
robfinch |
assign fcu_clk = clk_i;
|
1082 |
49 |
robfinch |
|
1083 |
|
|
`ifdef FCU_ENH
|
1084 |
48 |
robfinch |
FT64_BTB ubtb1
|
1085 |
|
|
(
|
1086 |
49 |
robfinch |
.rst(rst),
|
1087 |
|
|
.wclk(fcu_clk),
|
1088 |
|
|
.wr(btbwr0 | btbwr1),
|
1089 |
|
|
.wadr(btbwr0 ? iqentry_pc[head0] : iqentry_pc[head1]),
|
1090 |
|
|
.wdat(btbwr0 ? iqentry_a0[head0] : iqentry_a0[head1]),
|
1091 |
|
|
.valid(btbwr0 ? iqentry_bt[head0] & iqentry_v[head0] : iqentry_bt[head1] & iqentry_v[head1]),
|
1092 |
|
|
.rclk(~clk),
|
1093 |
|
|
.pcA(fetchbufA_pc),
|
1094 |
|
|
.btgtA(btgtA),
|
1095 |
|
|
.pcB(fetchbufB_pc),
|
1096 |
|
|
.btgtB(btgtB),
|
1097 |
|
|
.pcC(fetchbufC_pc),
|
1098 |
|
|
.btgtC(btgtC),
|
1099 |
|
|
.pcD(fetchbufD_pc),
|
1100 |
|
|
.btgtD(btgtD),
|
1101 |
|
|
.npcA(BRKPC),
|
1102 |
|
|
.npcB(BRKPC),
|
1103 |
|
|
.npcC(BRKPC),
|
1104 |
|
|
.npcD(BRKPC)
|
1105 |
48 |
robfinch |
);
|
1106 |
49 |
robfinch |
`else
|
1107 |
|
|
// Branch tergets are picked up by fetchbuf logic and need to be present.
|
1108 |
|
|
// Without a target predictor they are just set to the reset address.
|
1109 |
|
|
// This virtually guarentees a miss.
|
1110 |
|
|
assign btgtA = RSTPC;
|
1111 |
|
|
assign btgtB = RSTPC;
|
1112 |
|
|
assign btgtC = RSTPC;
|
1113 |
|
|
assign btgtD = RSTPC;
|
1114 |
|
|
`endif
|
1115 |
48 |
robfinch |
|
1116 |
49 |
robfinch |
`ifdef FCU_ENH
|
1117 |
48 |
robfinch |
FT64_BranchPredictor ubp1
|
1118 |
|
|
(
|
1119 |
49 |
robfinch |
.rst(rst),
|
1120 |
|
|
.clk(fcu_clk),
|
1121 |
|
|
.en(bpe),
|
1122 |
|
|
.xisBranch0(iqentry_br[head0] & commit0_v),
|
1123 |
|
|
.xisBranch1(iqentry_br[head1] & commit1_v),
|
1124 |
|
|
.pcA(fetchbufA_pc),
|
1125 |
|
|
.pcB(fetchbufB_pc),
|
1126 |
|
|
.pcC(fetchbufC_pc),
|
1127 |
|
|
.pcD(fetchbufD_pc),
|
1128 |
|
|
.xpc0(iqentry_pc[head0]),
|
1129 |
|
|
.xpc1(iqentry_pc[head1]),
|
1130 |
|
|
.takb0(commit0_v & iqentry_res[head0][0]),
|
1131 |
|
|
.takb1(commit1_v & iqentry_res[head1][0]),
|
1132 |
|
|
.predict_takenA(predict_takenA),
|
1133 |
|
|
.predict_takenB(predict_takenB),
|
1134 |
|
|
.predict_takenC(predict_takenC),
|
1135 |
|
|
.predict_takenD(predict_takenD)
|
1136 |
48 |
robfinch |
);
|
1137 |
49 |
robfinch |
`else
|
1138 |
|
|
// Predict based on sign of displacement
|
1139 |
|
|
assign predict_takenA = fetchbufA_instr[31];
|
1140 |
|
|
assign predict_takenB = fetchbufB_instr[31];
|
1141 |
|
|
assign predict_takenC = fetchbufC_instr[31];
|
1142 |
|
|
assign predict_takenD = fetchbufD_instr[31];
|
1143 |
|
|
`endif
|
1144 |
48 |
robfinch |
|
1145 |
|
|
//-----------------------------------------------------------------------------
|
1146 |
|
|
// Debug
|
1147 |
|
|
//-----------------------------------------------------------------------------
|
1148 |
|
|
`ifdef SUPPORT_DBG
|
1149 |
|
|
|
1150 |
|
|
wire [DBW-1:0] dbg_stat1x;
|
1151 |
|
|
reg [DBW-1:0] dbg_stat;
|
1152 |
|
|
reg [DBW-1:0] dbg_ctrl;
|
1153 |
|
|
reg [ABW-1:0] dbg_adr0;
|
1154 |
|
|
reg [ABW-1:0] dbg_adr1;
|
1155 |
|
|
reg [ABW-1:0] dbg_adr2;
|
1156 |
|
|
reg [ABW-1:0] dbg_adr3;
|
1157 |
|
|
reg dbg_imatchA0,dbg_imatchA1,dbg_imatchA2,dbg_imatchA3,dbg_imatchA;
|
1158 |
|
|
reg dbg_imatchB0,dbg_imatchB1,dbg_imatchB2,dbg_imatchB3,dbg_imatchB;
|
1159 |
|
|
|
1160 |
|
|
wire dbg_lmatch00 =
|
1161 |
|
|
dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram0_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
|
1162 |
|
|
((dbg_ctrl[19:18]==2'b00 && dram0_addr[2:0]==dbg_adr0[2:0]) ||
|
1163 |
|
|
(dbg_ctrl[19:18]==2'b01 && dram0_addr[2:1]==dbg_adr0[2:1]) ||
|
1164 |
|
|
(dbg_ctrl[19:18]==2'b10 && dram0_addr[2]==dbg_adr0[2]) ||
|
1165 |
|
|
dbg_ctrl[19:18]==2'b11)
|
1166 |
|
|
;
|
1167 |
|
|
wire dbg_lmatch01 =
|
1168 |
|
|
dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram1_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
|
1169 |
|
|
((dbg_ctrl[19:18]==2'b00 && dram1_addr[2:0]==dbg_adr0[2:0]) ||
|
1170 |
|
|
(dbg_ctrl[19:18]==2'b01 && dram1_addr[2:1]==dbg_adr0[2:1]) ||
|
1171 |
|
|
(dbg_ctrl[19:18]==2'b10 && dram1_addr[2]==dbg_adr0[2]) ||
|
1172 |
|
|
dbg_ctrl[19:18]==2'b11)
|
1173 |
|
|
;
|
1174 |
|
|
wire dbg_lmatch02 =
|
1175 |
|
|
dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram2_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
|
1176 |
|
|
((dbg_ctrl[19:18]==2'b00 && dram2_addr[2:0]==dbg_adr0[2:0]) ||
|
1177 |
|
|
(dbg_ctrl[19:18]==2'b01 && dram2_addr[2:1]==dbg_adr0[2:1]) ||
|
1178 |
|
|
(dbg_ctrl[19:18]==2'b10 && dram2_addr[2]==dbg_adr0[2]) ||
|
1179 |
|
|
dbg_ctrl[19:18]==2'b11)
|
1180 |
|
|
;
|
1181 |
|
|
wire dbg_lmatch10 =
|
1182 |
|
|
dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram0_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
|
1183 |
|
|
((dbg_ctrl[23:22]==2'b00 && dram0_addr[2:0]==dbg_adr1[2:0]) ||
|
1184 |
|
|
(dbg_ctrl[23:22]==2'b01 && dram0_addr[2:1]==dbg_adr1[2:1]) ||
|
1185 |
|
|
(dbg_ctrl[23:22]==2'b10 && dram0_addr[2]==dbg_adr1[2]) ||
|
1186 |
|
|
dbg_ctrl[23:22]==2'b11)
|
1187 |
|
|
;
|
1188 |
|
|
wire dbg_lmatch11 =
|
1189 |
|
|
dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram1_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
|
1190 |
|
|
((dbg_ctrl[23:22]==2'b00 && dram1_addr[2:0]==dbg_adr1[2:0]) ||
|
1191 |
|
|
(dbg_ctrl[23:22]==2'b01 && dram1_addr[2:1]==dbg_adr1[2:1]) ||
|
1192 |
|
|
(dbg_ctrl[23:22]==2'b10 && dram1_addr[2]==dbg_adr1[2]) ||
|
1193 |
|
|
dbg_ctrl[23:22]==2'b11)
|
1194 |
|
|
;
|
1195 |
|
|
wire dbg_lmatch12 =
|
1196 |
|
|
dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram2_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
|
1197 |
|
|
((dbg_ctrl[23:22]==2'b00 && dram2_addr[2:0]==dbg_adr1[2:0]) ||
|
1198 |
|
|
(dbg_ctrl[23:22]==2'b01 && dram2_addr[2:1]==dbg_adr1[2:1]) ||
|
1199 |
|
|
(dbg_ctrl[23:22]==2'b10 && dram2_addr[2]==dbg_adr1[2]) ||
|
1200 |
|
|
dbg_ctrl[23:22]==2'b11)
|
1201 |
|
|
;
|
1202 |
|
|
wire dbg_lmatch20 =
|
1203 |
|
|
dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram0_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
|
1204 |
|
|
((dbg_ctrl[27:26]==2'b00 && dram0_addr[2:0]==dbg_adr2[2:0]) ||
|
1205 |
|
|
(dbg_ctrl[27:26]==2'b01 && dram0_addr[2:1]==dbg_adr2[2:1]) ||
|
1206 |
|
|
(dbg_ctrl[27:26]==2'b10 && dram0_addr[2]==dbg_adr2[2]) ||
|
1207 |
|
|
dbg_ctrl[27:26]==2'b11)
|
1208 |
|
|
;
|
1209 |
|
|
wire dbg_lmatch21 =
|
1210 |
|
|
dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram1_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
|
1211 |
|
|
((dbg_ctrl[27:26]==2'b00 && dram1_addr[2:0]==dbg_adr2[2:0]) ||
|
1212 |
|
|
(dbg_ctrl[27:26]==2'b01 && dram1_addr[2:1]==dbg_adr2[2:1]) ||
|
1213 |
|
|
(dbg_ctrl[27:26]==2'b10 && dram1_addr[2]==dbg_adr2[2]) ||
|
1214 |
|
|
dbg_ctrl[27:26]==2'b11)
|
1215 |
|
|
;
|
1216 |
|
|
wire dbg_lmatch22 =
|
1217 |
|
|
dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram2_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
|
1218 |
|
|
((dbg_ctrl[27:26]==2'b00 && dram2_addr[2:0]==dbg_adr2[2:0]) ||
|
1219 |
|
|
(dbg_ctrl[27:26]==2'b01 && dram2_addr[2:1]==dbg_adr2[2:1]) ||
|
1220 |
|
|
(dbg_ctrl[27:26]==2'b10 && dram2_addr[2]==dbg_adr2[2]) ||
|
1221 |
|
|
dbg_ctrl[27:26]==2'b11)
|
1222 |
|
|
;
|
1223 |
|
|
wire dbg_lmatch30 =
|
1224 |
|
|
dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram0_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
|
1225 |
|
|
((dbg_ctrl[31:30]==2'b00 && dram0_addr[2:0]==dbg_adr3[2:0]) ||
|
1226 |
|
|
(dbg_ctrl[31:30]==2'b01 && dram0_addr[2:1]==dbg_adr3[2:1]) ||
|
1227 |
|
|
(dbg_ctrl[31:30]==2'b10 && dram0_addr[2]==dbg_adr3[2]) ||
|
1228 |
|
|
dbg_ctrl[31:30]==2'b11)
|
1229 |
|
|
;
|
1230 |
|
|
wire dbg_lmatch31 =
|
1231 |
|
|
dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram1_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
|
1232 |
|
|
((dbg_ctrl[31:30]==2'b00 && dram1_addr[2:0]==dbg_adr3[2:0]) ||
|
1233 |
|
|
(dbg_ctrl[31:30]==2'b01 && dram1_addr[2:1]==dbg_adr3[2:1]) ||
|
1234 |
|
|
(dbg_ctrl[31:30]==2'b10 && dram1_addr[2]==dbg_adr3[2]) ||
|
1235 |
|
|
dbg_ctrl[31:30]==2'b11)
|
1236 |
|
|
;
|
1237 |
|
|
wire dbg_lmatch32 =
|
1238 |
|
|
dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram2_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
|
1239 |
|
|
((dbg_ctrl[31:30]==2'b00 && dram2_addr[2:0]==dbg_adr3[2:0]) ||
|
1240 |
|
|
(dbg_ctrl[31:30]==2'b01 && dram2_addr[2:1]==dbg_adr3[2:1]) ||
|
1241 |
|
|
(dbg_ctrl[31:30]==2'b10 && dram2_addr[2]==dbg_adr3[2]) ||
|
1242 |
|
|
dbg_ctrl[31:30]==2'b11)
|
1243 |
|
|
;
|
1244 |
|
|
wire dbg_lmatch0 = dbg_lmatch00|dbg_lmatch10|dbg_lmatch20|dbg_lmatch30;
|
1245 |
|
|
wire dbg_lmatch1 = dbg_lmatch01|dbg_lmatch11|dbg_lmatch21|dbg_lmatch31;
|
1246 |
|
|
wire dbg_lmatch2 = dbg_lmatch02|dbg_lmatch12|dbg_lmatch22|dbg_lmatch32;
|
1247 |
|
|
wire dbg_lmatch = dbg_lmatch00|dbg_lmatch10|dbg_lmatch20|dbg_lmatch30|
|
1248 |
|
|
dbg_lmatch01|dbg_lmatch11|dbg_lmatch21|dbg_lmatch31|
|
1249 |
|
|
dbg_lmatch02|dbg_lmatch12|dbg_lmatch22|dbg_lmatch32
|
1250 |
|
|
;
|
1251 |
|
|
|
1252 |
|
|
wire dbg_smatch00 =
|
1253 |
|
|
dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram0_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
|
1254 |
|
|
((dbg_ctrl[19:18]==2'b00 && dram0_addr[2:0]==dbg_adr0[2:0]) ||
|
1255 |
|
|
(dbg_ctrl[19:18]==2'b01 && dram0_addr[2:1]==dbg_adr0[2:1]) ||
|
1256 |
|
|
(dbg_ctrl[19:18]==2'b10 && dram0_addr[2]==dbg_adr0[2]) ||
|
1257 |
|
|
dbg_ctrl[19:18]==2'b11)
|
1258 |
|
|
;
|
1259 |
|
|
wire dbg_smatch01 =
|
1260 |
|
|
dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram1_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
|
1261 |
|
|
((dbg_ctrl[19:18]==2'b00 && dram1_addr[2:0]==dbg_adr0[2:0]) ||
|
1262 |
|
|
(dbg_ctrl[19:18]==2'b01 && dram1_addr[2:1]==dbg_adr0[2:1]) ||
|
1263 |
|
|
(dbg_ctrl[19:18]==2'b10 && dram1_addr[2]==dbg_adr0[2]) ||
|
1264 |
|
|
dbg_ctrl[19:18]==2'b11)
|
1265 |
|
|
;
|
1266 |
|
|
wire dbg_smatch02 =
|
1267 |
|
|
dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram2_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
|
1268 |
|
|
((dbg_ctrl[19:18]==2'b00 && dram2_addr[2:0]==dbg_adr0[2:0]) ||
|
1269 |
|
|
(dbg_ctrl[19:18]==2'b01 && dram2_addr[2:1]==dbg_adr0[2:1]) ||
|
1270 |
|
|
(dbg_ctrl[19:18]==2'b10 && dram2_addr[2]==dbg_adr0[2]) ||
|
1271 |
|
|
dbg_ctrl[19:18]==2'b11)
|
1272 |
|
|
;
|
1273 |
|
|
wire dbg_smatch10 =
|
1274 |
|
|
dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram0_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
|
1275 |
|
|
((dbg_ctrl[23:22]==2'b00 && dram0_addr[2:0]==dbg_adr1[2:0]) ||
|
1276 |
|
|
(dbg_ctrl[23:22]==2'b01 && dram0_addr[2:1]==dbg_adr1[2:1]) ||
|
1277 |
|
|
(dbg_ctrl[23:22]==2'b10 && dram0_addr[2]==dbg_adr1[2]) ||
|
1278 |
|
|
dbg_ctrl[23:22]==2'b11)
|
1279 |
|
|
;
|
1280 |
|
|
wire dbg_smatch11 =
|
1281 |
|
|
dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram1_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
|
1282 |
|
|
((dbg_ctrl[23:22]==2'b00 && dram1_addr[2:0]==dbg_adr1[2:0]) ||
|
1283 |
|
|
(dbg_ctrl[23:22]==2'b01 && dram1_addr[2:1]==dbg_adr1[2:1]) ||
|
1284 |
|
|
(dbg_ctrl[23:22]==2'b10 && dram1_addr[2]==dbg_adr1[2]) ||
|
1285 |
|
|
dbg_ctrl[23:22]==2'b11)
|
1286 |
|
|
;
|
1287 |
|
|
wire dbg_smatch12 =
|
1288 |
|
|
dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram2_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
|
1289 |
|
|
((dbg_ctrl[23:22]==2'b00 && dram2_addr[2:0]==dbg_adr1[2:0]) ||
|
1290 |
|
|
(dbg_ctrl[23:22]==2'b01 && dram2_addr[2:1]==dbg_adr1[2:1]) ||
|
1291 |
|
|
(dbg_ctrl[23:22]==2'b10 && dram2_addr[2]==dbg_adr1[2]) ||
|
1292 |
|
|
dbg_ctrl[23:22]==2'b11)
|
1293 |
|
|
;
|
1294 |
|
|
wire dbg_smatch20 =
|
1295 |
|
|
dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram0_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
|
1296 |
|
|
((dbg_ctrl[27:26]==2'b00 && dram0_addr[2:0]==dbg_adr2[2:0]) ||
|
1297 |
|
|
(dbg_ctrl[27:26]==2'b01 && dram0_addr[2:1]==dbg_adr2[2:1]) ||
|
1298 |
|
|
(dbg_ctrl[27:26]==2'b10 && dram0_addr[2]==dbg_adr2[2]) ||
|
1299 |
|
|
dbg_ctrl[27:26]==2'b11)
|
1300 |
|
|
;
|
1301 |
|
|
wire dbg_smatch21 =
|
1302 |
|
|
dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram1_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
|
1303 |
|
|
((dbg_ctrl[27:26]==2'b00 && dram1_addr[2:0]==dbg_adr2[2:0]) ||
|
1304 |
|
|
(dbg_ctrl[27:26]==2'b01 && dram1_addr[2:1]==dbg_adr2[2:1]) ||
|
1305 |
|
|
(dbg_ctrl[27:26]==2'b10 && dram1_addr[2]==dbg_adr2[2]) ||
|
1306 |
|
|
dbg_ctrl[27:26]==2'b11)
|
1307 |
|
|
;
|
1308 |
|
|
wire dbg_smatch22 =
|
1309 |
|
|
dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram2_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
|
1310 |
|
|
((dbg_ctrl[27:26]==2'b00 && dram2_addr[2:0]==dbg_adr2[2:0]) ||
|
1311 |
|
|
(dbg_ctrl[27:26]==2'b01 && dram2_addr[2:1]==dbg_adr2[2:1]) ||
|
1312 |
|
|
(dbg_ctrl[27:26]==2'b10 && dram2_addr[2]==dbg_adr2[2]) ||
|
1313 |
|
|
dbg_ctrl[27:26]==2'b11)
|
1314 |
|
|
;
|
1315 |
|
|
wire dbg_smatch30 =
|
1316 |
|
|
dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram0_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
|
1317 |
|
|
((dbg_ctrl[31:30]==2'b00 && dram0_addr[2:0]==dbg_adr3[2:0]) ||
|
1318 |
|
|
(dbg_ctrl[31:30]==2'b01 && dram0_addr[2:1]==dbg_adr3[2:1]) ||
|
1319 |
|
|
(dbg_ctrl[31:30]==2'b10 && dram0_addr[2]==dbg_adr3[2]) ||
|
1320 |
|
|
dbg_ctrl[31:30]==2'b11)
|
1321 |
|
|
;
|
1322 |
|
|
wire dbg_smatch31 =
|
1323 |
|
|
dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram1_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
|
1324 |
|
|
((dbg_ctrl[31:30]==2'b00 && dram1_addr[2:0]==dbg_adr3[2:0]) ||
|
1325 |
|
|
(dbg_ctrl[31:30]==2'b01 && dram1_addr[2:1]==dbg_adr3[2:1]) ||
|
1326 |
|
|
(dbg_ctrl[31:30]==2'b10 && dram1_addr[2]==dbg_adr3[2]) ||
|
1327 |
|
|
dbg_ctrl[31:30]==2'b11)
|
1328 |
|
|
;
|
1329 |
|
|
wire dbg_smatch32 =
|
1330 |
|
|
dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram2_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
|
1331 |
|
|
((dbg_ctrl[31:30]==2'b00 && dram2_addr[2:0]==dbg_adr3[2:0]) ||
|
1332 |
|
|
(dbg_ctrl[31:30]==2'b01 && dram2_addr[2:1]==dbg_adr3[2:1]) ||
|
1333 |
|
|
(dbg_ctrl[31:30]==2'b10 && dram2_addr[2]==dbg_adr3[2]) ||
|
1334 |
|
|
dbg_ctrl[31:30]==2'b11)
|
1335 |
|
|
;
|
1336 |
|
|
wire dbg_smatch0 = dbg_smatch00|dbg_smatch10|dbg_smatch20|dbg_smatch30;
|
1337 |
|
|
wire dbg_smatch1 = dbg_smatch01|dbg_smatch11|dbg_smatch21|dbg_smatch31;
|
1338 |
|
|
wire dbg_smatch2 = dbg_smatch02|dbg_smatch12|dbg_smatch22|dbg_smatch32;
|
1339 |
|
|
|
1340 |
|
|
wire dbg_smatch = dbg_smatch00|dbg_smatch10|dbg_smatch20|dbg_smatch30|
|
1341 |
|
|
dbg_smatch01|dbg_smatch11|dbg_smatch21|dbg_smatch31|
|
1342 |
|
|
dbg_smatch02|dbg_smatch12|dbg_smatch22|dbg_smatch32
|
1343 |
|
|
;
|
1344 |
|
|
|
1345 |
|
|
wire dbg_stat0 = dbg_imatchA0 | dbg_imatchB0 | dbg_lmatch00 | dbg_lmatch01 | dbg_lmatch02 | dbg_smatch00 | dbg_smatch01 | dbg_smatch02;
|
1346 |
|
|
wire dbg_stat1 = dbg_imatchA1 | dbg_imatchB1 | dbg_lmatch10 | dbg_lmatch11 | dbg_lmatch12 | dbg_smatch10 | dbg_smatch11 | dbg_smatch12;
|
1347 |
|
|
wire dbg_stat2 = dbg_imatchA2 | dbg_imatchB2 | dbg_lmatch20 | dbg_lmatch21 | dbg_lmatch22 | dbg_smatch20 | dbg_smatch21 | dbg_smatch22;
|
1348 |
|
|
wire dbg_stat3 = dbg_imatchA3 | dbg_imatchB3 | dbg_lmatch30 | dbg_lmatch31 | dbg_lmatch32 | dbg_smatch30 | dbg_smatch31 | dbg_smatch32;
|
1349 |
|
|
assign dbg_stat1x = {dbg_stat3,dbg_stat2,dbg_stat1,dbg_stat0};
|
1350 |
|
|
wire debug_on = |dbg_ctrl[3:0]|dbg_ctrl[7]|dbg_ctrl[63];
|
1351 |
|
|
|
1352 |
|
|
always @*
|
1353 |
|
|
begin
|
1354 |
|
|
if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf0_pc==dbg_adr0)
|
1355 |
|
|
dbg_imatchA0 = `TRUE;
|
1356 |
|
|
if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf0_pc==dbg_adr1)
|
1357 |
|
|
dbg_imatchA1 = `TRUE;
|
1358 |
|
|
if (dbg_ctrl[2] && dbg_ctrl[25:24]==2'b00 && fetchbuf0_pc==dbg_adr2)
|
1359 |
|
|
dbg_imatchA2 = `TRUE;
|
1360 |
|
|
if (dbg_ctrl[3] && dbg_ctrl[29:28]==2'b00 && fetchbuf0_pc==dbg_adr3)
|
1361 |
|
|
dbg_imatchA3 = `TRUE;
|
1362 |
|
|
if (dbg_imatchA0|dbg_imatchA1|dbg_imatchA2|dbg_imatchA3)
|
1363 |
|
|
dbg_imatchA = `TRUE;
|
1364 |
|
|
end
|
1365 |
|
|
|
1366 |
|
|
always @*
|
1367 |
|
|
begin
|
1368 |
|
|
if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf1_pc==dbg_adr0)
|
1369 |
|
|
dbg_imatchB0 = `TRUE;
|
1370 |
|
|
if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf1_pc==dbg_adr1)
|
1371 |
|
|
dbg_imatchB1 = `TRUE;
|
1372 |
|
|
if (dbg_ctrl[2] && dbg_ctrl[25:24]==2'b00 && fetchbuf1_pc==dbg_adr2)
|
1373 |
|
|
dbg_imatchB2 = `TRUE;
|
1374 |
|
|
if (dbg_ctrl[3] && dbg_ctrl[29:28]==2'b00 && fetchbuf1_pc==dbg_adr3)
|
1375 |
|
|
dbg_imatchB3 = `TRUE;
|
1376 |
|
|
if (dbg_imatchB0|dbg_imatchB1|dbg_imatchB2|dbg_imatchB3)
|
1377 |
|
|
dbg_imatchB = `TRUE;
|
1378 |
|
|
end
|
1379 |
|
|
`endif
|
1380 |
|
|
|
1381 |
|
|
//-----------------------------------------------------------------------------
|
1382 |
|
|
//-----------------------------------------------------------------------------
|
1383 |
|
|
|
1384 |
|
|
// hirq squashes the pc increment if there's an irq.
|
1385 |
|
|
wire hirq = (irq_i > im) && ~int_commit;
|
1386 |
|
|
always @*
|
1387 |
|
|
if (hirq)
|
1388 |
49 |
robfinch |
insn0 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
|
1389 |
48 |
robfinch |
else if (phit) begin
|
1390 |
49 |
robfinch |
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00)
|
1391 |
|
|
insn0 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
1392 |
48 |
robfinch |
else
|
1393 |
|
|
insn0 <= insn0a;
|
1394 |
|
|
end
|
1395 |
|
|
else
|
1396 |
|
|
insn0 <= `NOP_INSN;
|
1397 |
49 |
robfinch |
generate begin : gInsnMux
|
1398 |
|
|
if (`WAYS > 1) begin
|
1399 |
48 |
robfinch |
always @*
|
1400 |
|
|
if (phit) begin
|
1401 |
49 |
robfinch |
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00)
|
1402 |
|
|
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
1403 |
48 |
robfinch |
else
|
1404 |
|
|
insn1 <= insn1a;
|
1405 |
|
|
end
|
1406 |
|
|
else
|
1407 |
|
|
insn1 <= `NOP_INSN;
|
1408 |
49 |
robfinch |
end
|
1409 |
|
|
if (`WAYS > 2) begin
|
1410 |
|
|
always @*
|
1411 |
|
|
if (phit) begin
|
1412 |
|
|
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00)
|
1413 |
|
|
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
|
1414 |
|
|
else
|
1415 |
|
|
insn2 <= insn2a;
|
1416 |
|
|
end
|
1417 |
|
|
else
|
1418 |
|
|
insn2 <= `NOP_INSN;
|
1419 |
|
|
end
|
1420 |
|
|
end
|
1421 |
|
|
endgenerate
|
1422 |
48 |
robfinch |
|
1423 |
|
|
wire [63:0] dc0_out, dc1_out, dc2_out;
|
1424 |
|
|
assign rdat0 = dram0_unc ? xdati : dc0_out;
|
1425 |
|
|
assign rdat1 = dram1_unc ? xdati : dc1_out;
|
1426 |
|
|
assign rdat2 = dram2_unc ? xdati : dc2_out;
|
1427 |
|
|
|
1428 |
|
|
reg preload;
|
1429 |
|
|
reg [1:0] dccnt;
|
1430 |
|
|
wire dhit0, dhit1, dhit2;
|
1431 |
|
|
wire dhit00, dhit10, dhit20;
|
1432 |
|
|
wire dhit01, dhit11, dhit21;
|
1433 |
49 |
robfinch |
reg [`ABITS] dc_wadr;
|
1434 |
48 |
robfinch |
reg [63:0] dc_wdat;
|
1435 |
|
|
reg isStore;
|
1436 |
|
|
|
1437 |
|
|
FT64_dcache udc0
|
1438 |
|
|
(
|
1439 |
|
|
.rst(rst),
|
1440 |
|
|
.wclk(clk),
|
1441 |
|
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit0)),
|
1442 |
|
|
.sel(sel_o),
|
1443 |
|
|
.wadr({pcr[5:0],adr_o}),
|
1444 |
|
|
.i(bstate==B2d ? dat_i : dat_o),
|
1445 |
|
|
.rclk(clk),
|
1446 |
|
|
.rdsize(dram0_memsize),
|
1447 |
|
|
.radr({pcr[5:0],dram0_addr}),
|
1448 |
|
|
.o(dc0_out),
|
1449 |
|
|
.hit(),
|
1450 |
|
|
.hit0(dhit0),
|
1451 |
|
|
.hit1()
|
1452 |
|
|
);
|
1453 |
49 |
robfinch |
generate begin : gDCacheInst
|
1454 |
|
|
if (`NUM_MEM > 1) begin
|
1455 |
48 |
robfinch |
FT64_dcache udc1
|
1456 |
|
|
(
|
1457 |
|
|
.rst(rst),
|
1458 |
|
|
.wclk(clk),
|
1459 |
|
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit1)),
|
1460 |
|
|
.sel(sel_o),
|
1461 |
|
|
.wadr({pcr[5:0],adr_o}),
|
1462 |
|
|
.i(bstate==B2d ? dat_i : dat_o),
|
1463 |
|
|
.rclk(clk),
|
1464 |
|
|
.rdsize(dram1_memsize),
|
1465 |
|
|
.radr({pcr[5:0],dram1_addr}),
|
1466 |
|
|
.o(dc1_out),
|
1467 |
|
|
.hit(),
|
1468 |
|
|
.hit0(dhit1),
|
1469 |
|
|
.hit1()
|
1470 |
|
|
);
|
1471 |
49 |
robfinch |
end
|
1472 |
|
|
if (`NUM_MEM > 2) begin
|
1473 |
48 |
robfinch |
FT64_dcache udc2
|
1474 |
|
|
(
|
1475 |
|
|
.rst(rst),
|
1476 |
|
|
.wclk(clk),
|
1477 |
|
|
.wr((bstate==B2d && ack_i)||((bstate==B1||(bstate==B19 && isStore)) && dhit2)),
|
1478 |
|
|
.sel(sel_o),
|
1479 |
|
|
.wadr({pcr[5:0],adr_o}),
|
1480 |
|
|
.i(bstate==B2d ? dat_i : dat_o),
|
1481 |
|
|
.rclk(clk),
|
1482 |
|
|
.rdsize(dram2_memsize),
|
1483 |
|
|
.radr({pcr[5:0],dram2_addr}),
|
1484 |
|
|
.o(dc2_out),
|
1485 |
|
|
.hit(),
|
1486 |
|
|
.hit0(dhit2),
|
1487 |
|
|
.hit1()
|
1488 |
|
|
);
|
1489 |
49 |
robfinch |
end
|
1490 |
|
|
end
|
1491 |
|
|
endgenerate
|
1492 |
48 |
robfinch |
|
1493 |
|
|
function [`QBITS] idp1;
|
1494 |
|
|
input [`QBITS] id;
|
1495 |
|
|
case(id)
|
1496 |
|
|
3'd0: idp1 = 3'd1;
|
1497 |
|
|
3'd1: idp1 = 3'd2;
|
1498 |
|
|
3'd2: idp1 = 3'd3;
|
1499 |
|
|
3'd3: idp1 = 3'd4;
|
1500 |
|
|
3'd4: idp1 = 3'd5;
|
1501 |
|
|
3'd5: idp1 = 3'd6;
|
1502 |
|
|
3'd6: idp1 = 3'd7;
|
1503 |
|
|
3'd7: idp1 = 3'd0;
|
1504 |
|
|
endcase
|
1505 |
|
|
endfunction
|
1506 |
|
|
|
1507 |
|
|
function [`QBITS] idp2;
|
1508 |
|
|
input [`QBITS] id;
|
1509 |
|
|
case(id)
|
1510 |
|
|
3'd0: idp2 = 3'd2;
|
1511 |
|
|
3'd1: idp2 = 3'd3;
|
1512 |
|
|
3'd2: idp2 = 3'd4;
|
1513 |
|
|
3'd3: idp2 = 3'd5;
|
1514 |
|
|
3'd4: idp2 = 3'd6;
|
1515 |
|
|
3'd5: idp2 = 3'd7;
|
1516 |
|
|
3'd6: idp2 = 3'd0;
|
1517 |
|
|
3'd7: idp2 = 3'd1;
|
1518 |
|
|
endcase
|
1519 |
|
|
endfunction
|
1520 |
|
|
|
1521 |
|
|
function [`QBITS] idp3;
|
1522 |
|
|
input [`QBITS] id;
|
1523 |
|
|
case(id)
|
1524 |
|
|
3'd0: idp3 = 3'd3;
|
1525 |
|
|
3'd1: idp3 = 3'd4;
|
1526 |
|
|
3'd2: idp3 = 3'd5;
|
1527 |
|
|
3'd3: idp3 = 3'd6;
|
1528 |
|
|
3'd4: idp3 = 3'd7;
|
1529 |
|
|
3'd5: idp3 = 3'd0;
|
1530 |
|
|
3'd6: idp3 = 3'd1;
|
1531 |
|
|
3'd7: idp3 = 3'd2;
|
1532 |
|
|
endcase
|
1533 |
|
|
endfunction
|
1534 |
|
|
|
1535 |
|
|
function [`QBITS] idp4;
|
1536 |
|
|
input [`QBITS] id;
|
1537 |
|
|
case(id)
|
1538 |
|
|
3'd0: idp4 = 3'd4;
|
1539 |
|
|
3'd1: idp4 = 3'd5;
|
1540 |
|
|
3'd2: idp4 = 3'd6;
|
1541 |
|
|
3'd3: idp4 = 3'd7;
|
1542 |
|
|
3'd4: idp4 = 3'd0;
|
1543 |
|
|
3'd5: idp4 = 3'd1;
|
1544 |
|
|
3'd6: idp4 = 3'd2;
|
1545 |
|
|
3'd7: idp4 = 3'd3;
|
1546 |
|
|
endcase
|
1547 |
|
|
endfunction
|
1548 |
|
|
|
1549 |
|
|
function [`QBITS] idp5;
|
1550 |
|
|
input [`QBITS] id;
|
1551 |
|
|
case(id)
|
1552 |
|
|
3'd0: idp5 = 3'd5;
|
1553 |
|
|
3'd1: idp5 = 3'd6;
|
1554 |
|
|
3'd2: idp5 = 3'd7;
|
1555 |
|
|
3'd3: idp5 = 3'd0;
|
1556 |
|
|
3'd4: idp5 = 3'd1;
|
1557 |
|
|
3'd5: idp5 = 3'd2;
|
1558 |
|
|
3'd6: idp5 = 3'd3;
|
1559 |
|
|
3'd7: idp5 = 3'd4;
|
1560 |
|
|
endcase
|
1561 |
|
|
endfunction
|
1562 |
|
|
|
1563 |
|
|
function [`QBITS] idp6;
|
1564 |
|
|
input [`QBITS] id;
|
1565 |
|
|
case(id)
|
1566 |
|
|
3'd0: idp6 = 3'd6;
|
1567 |
|
|
3'd1: idp6 = 3'd7;
|
1568 |
|
|
3'd2: idp6 = 3'd0;
|
1569 |
|
|
3'd3: idp6 = 3'd1;
|
1570 |
|
|
3'd4: idp6 = 3'd2;
|
1571 |
|
|
3'd5: idp6 = 3'd3;
|
1572 |
|
|
3'd6: idp6 = 3'd4;
|
1573 |
|
|
3'd7: idp6 = 3'd5;
|
1574 |
|
|
endcase
|
1575 |
|
|
endfunction
|
1576 |
|
|
|
1577 |
|
|
function [`QBITS] idp7;
|
1578 |
|
|
input [`QBITS] id;
|
1579 |
|
|
case(id)
|
1580 |
|
|
3'd0: idp7 = 3'd7;
|
1581 |
|
|
3'd1: idp7 = 3'd0;
|
1582 |
|
|
3'd2: idp7 = 3'd1;
|
1583 |
|
|
3'd3: idp7 = 3'd2;
|
1584 |
|
|
3'd4: idp7 = 3'd3;
|
1585 |
|
|
3'd5: idp7 = 3'd4;
|
1586 |
|
|
3'd6: idp7 = 3'd5;
|
1587 |
|
|
3'd7: idp7 = 3'd6;
|
1588 |
|
|
endcase
|
1589 |
|
|
endfunction
|
1590 |
|
|
|
1591 |
|
|
function [`QBITS] idm1;
|
1592 |
|
|
input [`QBITS] id;
|
1593 |
|
|
case(id)
|
1594 |
|
|
3'd0: idm1 = 3'd7;
|
1595 |
|
|
3'd1: idm1 = 3'd0;
|
1596 |
|
|
3'd2: idm1 = 3'd1;
|
1597 |
|
|
3'd3: idm1 = 3'd2;
|
1598 |
|
|
3'd4: idm1 = 3'd3;
|
1599 |
|
|
3'd5: idm1 = 3'd4;
|
1600 |
|
|
3'd6: idm1 = 3'd5;
|
1601 |
|
|
3'd7: idm1 = 3'd6;
|
1602 |
|
|
endcase
|
1603 |
|
|
endfunction
|
1604 |
|
|
|
1605 |
|
|
`ifdef SUPPORT_SMT
|
1606 |
|
|
function [RBIT:0] fnRa;
|
1607 |
|
|
input [47:0] isn;
|
1608 |
|
|
input [5:0] vqei;
|
1609 |
|
|
input [5:0] vli;
|
1610 |
|
|
input thrd;
|
1611 |
|
|
case(isn[`INSTRUCTION_OP])
|
1612 |
|
|
`IVECTOR:
|
1613 |
|
|
case(isn[`INSTRUCTION_S2])
|
1614 |
|
|
`VCIDX,`VSCAN: fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
|
1615 |
|
|
`VMxx:
|
1616 |
|
|
case(isn[25:23])
|
1617 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP,`VMFIRST,`VMLAST:
|
1618 |
|
|
fnRa = {6'h3F,1'b1,2'b0,isn[8:6]};
|
1619 |
|
|
`VMFILL:fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
|
1620 |
|
|
default:fnRa = {6'h3F,1'b1,2'b0,isn[8:6]};
|
1621 |
|
|
endcase
|
1622 |
|
|
`VSHLV: fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
|
1623 |
|
|
`VSHRV: fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
|
1624 |
|
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
1625 |
|
|
default: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
1626 |
|
|
endcase
|
1627 |
50 |
robfinch |
`R2: casez(isn[`INSTRUCTION_S2])
|
1628 |
48 |
robfinch |
`MOV:
|
1629 |
|
|
case(isn[25:23])
|
1630 |
|
|
3'd0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1631 |
50 |
robfinch |
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
1632 |
48 |
robfinch |
3'd2: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1633 |
|
|
3'd3: fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
|
1634 |
|
|
3'd4: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1635 |
51 |
robfinch |
3'd5: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1636 |
|
|
3'd6: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1637 |
48 |
robfinch |
default:fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1638 |
|
|
endcase
|
1639 |
|
|
`VMOV:
|
1640 |
|
|
case (isn[`INSTRUCTION_S1])
|
1641 |
|
|
5'h0: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1642 |
|
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
1643 |
|
|
endcase
|
1644 |
|
|
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1645 |
|
|
endcase
|
1646 |
51 |
robfinch |
`FLOAT: fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1647 |
48 |
robfinch |
default: fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1648 |
|
|
endcase
|
1649 |
|
|
endfunction
|
1650 |
|
|
|
1651 |
|
|
function [RBIT:0] fnRb;
|
1652 |
|
|
input [47:0] isn;
|
1653 |
|
|
input fb;
|
1654 |
|
|
input [5:0] vqei;
|
1655 |
|
|
input [5:0] rfoa0i;
|
1656 |
|
|
input [5:0] rfoa1i;
|
1657 |
|
|
input thrd;
|
1658 |
|
|
case(isn[`INSTRUCTION_OP])
|
1659 |
|
|
`R2: case(isn[`INSTRUCTION_S2])
|
1660 |
|
|
`VEX: fnRb = fb ? {rfoa1i,1'b1,isn[`INSTRUCTION_RB]} : {rfoa0i,1'b1,isn[`INSTRUCTION_RB]};
|
1661 |
|
|
`LVX,`SVX: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1662 |
|
|
default: fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1663 |
|
|
endcase
|
1664 |
|
|
`IVECTOR:
|
1665 |
|
|
case(isn[`INSTRUCTION_S2])
|
1666 |
|
|
`VMxx:
|
1667 |
|
|
case(isn[25:23])
|
1668 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
|
1669 |
|
|
fnRb = {6'h3F,1'b1,2'b0,isn[13:11]};
|
1670 |
|
|
default: fnRb = 12'h000;
|
1671 |
|
|
endcase
|
1672 |
|
|
`VXCHG: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1673 |
|
|
`VSxx,`VSxxU: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1674 |
|
|
`VSxxS,`VSxxSU: fnRb = {vqei,1'b0,isn[`INSTRUCTION_RB]};
|
1675 |
|
|
`VADDS,`VSUBS,`VMULS,`VANDS,`VORS,`VXORS,`VXORS:
|
1676 |
|
|
fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1677 |
|
|
`VSHL,`VSHR,`VASR:
|
1678 |
|
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1679 |
|
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1680 |
|
|
endcase
|
1681 |
51 |
robfinch |
`FLOAT: fnRb = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1682 |
48 |
robfinch |
default: fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1683 |
|
|
endcase
|
1684 |
|
|
endfunction
|
1685 |
|
|
|
1686 |
|
|
function [RBIT:0] fnRc;
|
1687 |
|
|
input [47:0] isn;
|
1688 |
|
|
input [5:0] vqei;
|
1689 |
|
|
input thrd;
|
1690 |
|
|
case(isn[`INSTRUCTION_OP])
|
1691 |
|
|
`R2: case(isn[`INSTRUCTION_S2])
|
1692 |
|
|
`SVX: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1693 |
|
|
`SBX,`SCX,`SHX,`SWX,`SWCX,`CACHEX:
|
1694 |
|
|
fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1695 |
|
|
`CMOVEZ,`CMOVNZ,`MAJ:
|
1696 |
|
|
fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1697 |
|
|
default: fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1698 |
|
|
endcase
|
1699 |
|
|
`IVECTOR:
|
1700 |
|
|
case(isn[`INSTRUCTION_S2])
|
1701 |
|
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1702 |
|
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1703 |
|
|
endcase
|
1704 |
51 |
robfinch |
`FLOAT: fnRc = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1705 |
48 |
robfinch |
default: fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1706 |
|
|
endcase
|
1707 |
|
|
endfunction
|
1708 |
|
|
|
1709 |
|
|
function [RBIT:0] fnRt;
|
1710 |
|
|
input [47:0] isn;
|
1711 |
|
|
input [5:0] vqei;
|
1712 |
|
|
input [5:0] vli;
|
1713 |
|
|
input thrd;
|
1714 |
|
|
casez(isn[`INSTRUCTION_OP])
|
1715 |
|
|
`IVECTOR:
|
1716 |
|
|
case(isn[`INSTRUCTION_S2])
|
1717 |
|
|
`VMxx:
|
1718 |
|
|
case(isn[25:23])
|
1719 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMFILL:
|
1720 |
|
|
fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1721 |
|
|
`VMPOP: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1722 |
|
|
default:
|
1723 |
|
|
fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1724 |
|
|
endcase
|
1725 |
|
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1726 |
|
|
`VSHLV: fnRt = (vqei+1 >= vli) ? 11'h000 : {vli-vqei-1,1'b1,isn[`INSTRUCTION_RC]};
|
1727 |
|
|
`VSHRV: fnRt = (vqei >= vli) ? 11'h000 : {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1728 |
|
|
`VEINS: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]}; // ToDo: add element # from Ra
|
1729 |
|
|
`V2BITS: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1730 |
|
|
default: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1731 |
|
|
endcase
|
1732 |
|
|
|
1733 |
50 |
robfinch |
`R2: casez(isn[`INSTRUCTION_S2])
|
1734 |
48 |
robfinch |
`MOV:
|
1735 |
|
|
case(isn[25:23])
|
1736 |
50 |
robfinch |
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
1737 |
48 |
robfinch |
3'd1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1738 |
|
|
3'd2: fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RB]};
|
1739 |
|
|
3'd3: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1740 |
51 |
robfinch |
3'd4: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1741 |
48 |
robfinch |
3'd5: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1742 |
51 |
robfinch |
3'd6: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1743 |
48 |
robfinch |
default:fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1744 |
|
|
endcase
|
1745 |
|
|
`VMOV:
|
1746 |
|
|
case (isn[`INSTRUCTION_S1])
|
1747 |
|
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
1748 |
|
|
5'h1: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1749 |
|
|
default: fnRt = 12'h000;
|
1750 |
|
|
endcase
|
1751 |
|
|
`R1:
|
1752 |
|
|
case(isn[22:18])
|
1753 |
|
|
`CNTLO,`CNTLZ,`CNTPOP,`ABS,`NOT:
|
1754 |
|
|
fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1755 |
|
|
`MEMDB,`MEMSB,`SYNC:
|
1756 |
|
|
fnRt = 12'd0;
|
1757 |
|
|
default: fnRt = 12'd0;
|
1758 |
|
|
endcase
|
1759 |
|
|
`CMOVEZ: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_S1]};
|
1760 |
|
|
`CMOVNZ: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_S1]};
|
1761 |
|
|
`MUX: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_S1]};
|
1762 |
|
|
`MIN: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_S1]};
|
1763 |
|
|
`MAX: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_S1]};
|
1764 |
|
|
`LVX: fnRt = {vqei,1'b1,isn[20:16]};
|
1765 |
|
|
`SHIFTR: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1766 |
|
|
`SHIFT31,`SHIFT63:
|
1767 |
|
|
fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1768 |
|
|
`SEI: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1769 |
|
|
`WAIT,`RTI,`CHK:
|
1770 |
|
|
fnRt = 12'd0;
|
1771 |
|
|
default: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1772 |
|
|
endcase
|
1773 |
|
|
`MEMNDX:
|
1774 |
|
|
case(isn[`INSTRUCTION_S2])
|
1775 |
|
|
`SBX,`SCX,`SHX,`SWX,`SWCX,`CACHEX:
|
1776 |
|
|
fnRt = 12'd0;
|
1777 |
|
|
default: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1778 |
|
|
endcase
|
1779 |
|
|
`FLOAT:
|
1780 |
|
|
case(isn[31:26])
|
1781 |
|
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
1782 |
|
|
fnRt = 12'd0;
|
1783 |
|
|
`FSYNC: fnRt = 12'd0;
|
1784 |
51 |
robfinch |
default: fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1785 |
48 |
robfinch |
endcase
|
1786 |
|
|
`BRK: fnRt = 12'd0;
|
1787 |
|
|
`REX: fnRt = 12'd0;
|
1788 |
|
|
`CHK: fnRt = 12'd0;
|
1789 |
|
|
`EXEC: fnRt = 12'd0;
|
1790 |
|
|
`Bcc: fnRt = 12'd0;
|
1791 |
|
|
`BBc: case(isn[20:19])
|
1792 |
|
|
`IBNE: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1793 |
|
|
`DBNZ: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1794 |
|
|
default: fnRt = 12'd0;
|
1795 |
|
|
endcase
|
1796 |
|
|
`BEQI: fnRt = 12'd0;
|
1797 |
|
|
`SB,`Sx,`SWC,`CACHE:
|
1798 |
|
|
fnRt = 12'd0;
|
1799 |
|
|
`JMP: fnRt = 12'd0;
|
1800 |
|
|
`CALL: fnRt = {rgs[thrd],1'b0,regLR}; // regLR
|
1801 |
|
|
`RET: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
|
1802 |
|
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1803 |
|
|
`AMO: fnRt = isn[31] ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
|
1804 |
|
|
default: fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
|
1805 |
|
|
endcase
|
1806 |
|
|
endfunction
|
1807 |
|
|
`else
|
1808 |
|
|
function [RBIT:0] fnRa;
|
1809 |
|
|
input [47:0] isn;
|
1810 |
|
|
input [5:0] vqei;
|
1811 |
|
|
input [5:0] vli;
|
1812 |
|
|
input thrd;
|
1813 |
|
|
case(isn[`INSTRUCTION_OP])
|
1814 |
|
|
`IVECTOR:
|
1815 |
|
|
case(isn[`INSTRUCTION_S2])
|
1816 |
51 |
robfinch |
`VCIDX,`VSCAN: fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
|
1817 |
|
|
`VMxx:
|
1818 |
|
|
case(isn[25:23])
|
1819 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP,`VMFIRST,`VMLAST:
|
1820 |
|
|
fnRa = {6'h3F,1'b1,2'b0,isn[8:6]};
|
1821 |
|
|
`VMFILL:fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
|
1822 |
|
|
default:fnRa = {6'h3F,1'b1,2'b0,isn[8:6]};
|
1823 |
|
|
endcase
|
1824 |
|
|
`VSHLV: fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
|
1825 |
|
|
`VSHRV: fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
|
1826 |
|
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
1827 |
|
|
default: fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
|
1828 |
|
|
endcase
|
1829 |
50 |
robfinch |
`R2:
|
1830 |
|
|
casez(isn[`INSTRUCTION_S2])
|
1831 |
|
|
`MOV:
|
1832 |
|
|
case(isn[25:23])
|
1833 |
|
|
3'd0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1834 |
|
|
3'd1: fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
|
1835 |
|
|
3'd2: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1836 |
|
|
3'd3: fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
|
1837 |
|
|
3'd4: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1838 |
51 |
robfinch |
3'd5: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1839 |
|
|
3'd6: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1840 |
50 |
robfinch |
default:fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1841 |
|
|
endcase
|
1842 |
|
|
`VMOV:
|
1843 |
|
|
case (isn[`INSTRUCTION_S1])
|
1844 |
|
|
5'h0: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1845 |
|
|
5'h1: fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
|
1846 |
|
|
endcase
|
1847 |
|
|
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1848 |
|
|
endcase
|
1849 |
51 |
robfinch |
`FLOAT: fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1850 |
48 |
robfinch |
default: fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
1851 |
|
|
endcase
|
1852 |
|
|
endfunction
|
1853 |
|
|
|
1854 |
|
|
function [RBIT:0] fnRb;
|
1855 |
|
|
input [47:0] isn;
|
1856 |
|
|
input fb;
|
1857 |
|
|
input [5:0] vqei;
|
1858 |
|
|
input [5:0] rfoa0i;
|
1859 |
|
|
input [5:0] rfoa1i;
|
1860 |
|
|
input thrd;
|
1861 |
|
|
case(isn[`INSTRUCTION_OP])
|
1862 |
|
|
`RR: case(isn[`INSTRUCTION_S2])
|
1863 |
|
|
`VEX: fnRb = fb ? {rfoa1i,1'b1,isn[`INSTRUCTION_RB]} : {rfoa0i,1'b1,isn[`INSTRUCTION_RB]};
|
1864 |
|
|
`LVX,`SVX: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1865 |
|
|
default: fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1866 |
|
|
endcase
|
1867 |
|
|
`IVECTOR:
|
1868 |
|
|
case(isn[`INSTRUCTION_S2])
|
1869 |
|
|
`VMxx:
|
1870 |
|
|
case(isn[25:23])
|
1871 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
|
1872 |
|
|
fnRb = {6'h3F,1'b1,2'b0,isn[13:11]};
|
1873 |
|
|
default: fnRb = 12'h000;
|
1874 |
|
|
endcase
|
1875 |
|
|
`VXCHG: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1876 |
|
|
`VSxx,`VSxxU: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1877 |
|
|
`VSxxS,`VSxxSU: fnRb = {vqei,1'b0,isn[`INSTRUCTION_RB]};
|
1878 |
|
|
`VADDS,`VSUBS,`VMULS,`VANDS,`VORS,`VXORS,`VXORS:
|
1879 |
|
|
fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1880 |
|
|
`VSHL,`VSHR,`VASR:
|
1881 |
|
|
fnRb = {isn[25],isn[22]}==2'b00 ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1882 |
|
|
default: fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
1883 |
|
|
endcase
|
1884 |
51 |
robfinch |
`FLOAT: fnRb = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1885 |
48 |
robfinch |
default: fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1886 |
|
|
endcase
|
1887 |
|
|
endfunction
|
1888 |
|
|
|
1889 |
|
|
function [RBIT:0] fnRc;
|
1890 |
|
|
input [47:0] isn;
|
1891 |
|
|
input [5:0] vqei;
|
1892 |
|
|
input thrd;
|
1893 |
|
|
case(isn[`INSTRUCTION_OP])
|
1894 |
|
|
`R2: case(isn[`INSTRUCTION_S2])
|
1895 |
|
|
`SVX: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1896 |
|
|
`SBX,`SCX,`SHX,`SWX,`SWCX,`CACHEX:
|
1897 |
|
|
fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
1898 |
|
|
`CMOVEZ,`CMOVNZ,`MAJ:
|
1899 |
|
|
fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
1900 |
|
|
default: fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
1901 |
|
|
endcase
|
1902 |
|
|
`IVECTOR:
|
1903 |
|
|
case(isn[`INSTRUCTION_S2])
|
1904 |
|
|
`VSxx,`VSxxS,`VSxxU,`VSxxSU: fnRc = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1905 |
|
|
default: fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1906 |
|
|
endcase
|
1907 |
51 |
robfinch |
`FLOAT: fnRc = {fp_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
1908 |
48 |
robfinch |
default: fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
1909 |
|
|
endcase
|
1910 |
|
|
endfunction
|
1911 |
|
|
|
1912 |
|
|
function [RBIT:0] fnRt;
|
1913 |
|
|
input [47:0] isn;
|
1914 |
|
|
input [5:0] vqei;
|
1915 |
|
|
input [5:0] vli;
|
1916 |
|
|
input thrd;
|
1917 |
|
|
casez(isn[`INSTRUCTION_OP])
|
1918 |
|
|
`IVECTOR:
|
1919 |
|
|
case(isn[`INSTRUCTION_S2])
|
1920 |
|
|
`VMxx:
|
1921 |
|
|
case(isn[25:23])
|
1922 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMFILL:
|
1923 |
|
|
fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1924 |
|
|
`VMPOP: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1925 |
|
|
default:
|
1926 |
|
|
fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1927 |
|
|
endcase
|
1928 |
|
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1929 |
|
|
`VSHLV: fnRt = (vqei+1 >= vli) ? 11'h000 : {vli-vqei-1,1'b1,isn[`INSTRUCTION_RC]};
|
1930 |
|
|
`VSHRV: fnRt = (vqei >= vli) ? 11'h000 : {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1931 |
|
|
`VEINS: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]}; // ToDo: add element # from Ra
|
1932 |
|
|
`V2BITS: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1933 |
|
|
default: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1934 |
|
|
endcase
|
1935 |
|
|
|
1936 |
|
|
`FVECTOR:
|
1937 |
|
|
case(isn[`INSTRUCTION_S2])
|
1938 |
|
|
`VMxx:
|
1939 |
|
|
case(isn[25:23])
|
1940 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMFILL:
|
1941 |
|
|
fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1942 |
|
|
`VMPOP: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1943 |
|
|
default:
|
1944 |
|
|
fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1945 |
|
|
endcase
|
1946 |
|
|
`VSxx,`VSxxU,`VSxxS,`VSxxSU: fnRt = {6'h3F,1'b1,2'b0,isn[18:16]};
|
1947 |
|
|
`VSHLV: fnRt = (vqei+1 >= vli) ? 11'h000 : {vli-vqei-1,1'b1,isn[`INSTRUCTION_RC]};
|
1948 |
|
|
`VSHRV: fnRt = (vqei >= vli) ? 11'h000 : {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1949 |
|
|
`VEINS: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]}; // ToDo: add element # from Ra
|
1950 |
|
|
`V2BITS: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1951 |
|
|
default: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RC]};
|
1952 |
|
|
endcase
|
1953 |
|
|
|
1954 |
50 |
robfinch |
`R2:
|
1955 |
|
|
casez(isn[`INSTRUCTION_S2])
|
1956 |
|
|
`MOV:
|
1957 |
|
|
case(isn[25:23])
|
1958 |
|
|
3'd0: fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RB]};
|
1959 |
|
|
3'd1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1960 |
|
|
3'd2: fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RB]};
|
1961 |
|
|
3'd3: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1962 |
51 |
robfinch |
3'd4: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1963 |
50 |
robfinch |
3'd5: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1964 |
51 |
robfinch |
3'd6: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1965 |
50 |
robfinch |
default:fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1966 |
|
|
endcase
|
1967 |
|
|
`VMOV:
|
1968 |
|
|
case (isn[`INSTRUCTION_S1])
|
1969 |
|
|
5'h0: fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RB]};
|
1970 |
|
|
5'h1: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1971 |
|
|
default: fnRt = 12'h000;
|
1972 |
|
|
endcase
|
1973 |
|
|
`R1:
|
1974 |
|
|
case(isn[22:18])
|
1975 |
|
|
`CNTLO,`CNTLZ,`CNTPOP,`ABS,`NOT:
|
1976 |
|
|
fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1977 |
|
|
`MEMDB,`MEMSB,`SYNC:
|
1978 |
|
|
fnRt = 12'd0;
|
1979 |
|
|
default: fnRt = 12'd0;
|
1980 |
|
|
endcase
|
1981 |
|
|
`CMOVEZ: fnRt = {rgs,1'b0,isn[`INSTRUCTION_S1]};
|
1982 |
|
|
`CMOVNZ: fnRt = {rgs,1'b0,isn[`INSTRUCTION_S1]};
|
1983 |
|
|
`MUX: fnRt = {rgs,1'b0,isn[`INSTRUCTION_S1]};
|
1984 |
|
|
`MIN: fnRt = {rgs,1'b0,isn[`INSTRUCTION_S1]};
|
1985 |
|
|
`MAX: fnRt = {rgs,1'b0,isn[`INSTRUCTION_S1]};
|
1986 |
|
|
`LVX: fnRt = {vqei,1'b1,isn[20:16]};
|
1987 |
|
|
`SHIFTR: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
1988 |
|
|
`SHIFT31,`SHIFT63:
|
1989 |
|
|
fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1990 |
|
|
`SEI: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
1991 |
|
|
`WAIT,`RTI,`CHK:
|
1992 |
|
|
fnRt = 12'd0;
|
1993 |
|
|
default: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
1994 |
|
|
endcase
|
1995 |
48 |
robfinch |
`MEMNDX:
|
1996 |
|
|
case(isn[`INSTRUCTION_S2])
|
1997 |
|
|
`SBX,`SCX,`SHX,`SWX,`SWCX,`CACHEX:
|
1998 |
|
|
fnRt = 12'd0;
|
1999 |
|
|
default: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
2000 |
|
|
endcase
|
2001 |
|
|
`FLOAT:
|
2002 |
|
|
case(isn[31:26])
|
2003 |
|
|
`FTX,`FCX,`FEX,`FDX,`FRM:
|
2004 |
|
|
fnRt = 12'd0;
|
2005 |
|
|
`FSYNC: fnRt = 12'd0;
|
2006 |
51 |
robfinch |
default: fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RC]};
|
2007 |
48 |
robfinch |
endcase
|
2008 |
|
|
`BRK: fnRt = 12'd0;
|
2009 |
|
|
`REX: fnRt = 12'd0;
|
2010 |
|
|
`CHK: fnRt = 12'd0;
|
2011 |
|
|
`EXEC: fnRt = 12'd0;
|
2012 |
|
|
`Bcc: fnRt = 12'd0;
|
2013 |
|
|
`BBc:
|
2014 |
|
|
case(isn[20:19])
|
2015 |
|
|
`IBNE: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
2016 |
|
|
`DBNZ: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
2017 |
|
|
default: fnRt = 12'd0;
|
2018 |
|
|
endcase
|
2019 |
|
|
`BEQI: fnRt = 12'd0;
|
2020 |
|
|
`SB,`Sx,`SWC,`CACHE:
|
2021 |
|
|
fnRt = 12'd0;
|
2022 |
|
|
`JMP: fnRt = 12'd0;
|
2023 |
|
|
`CALL: fnRt = {rgs,1'b0,regLR}; // regLR
|
2024 |
|
|
`RET: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RA]};
|
2025 |
|
|
`LV: fnRt = {vqei,1'b1,isn[`INSTRUCTION_RB]};
|
2026 |
|
|
`AMO: fnRt = isn[31] ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {rgs,1'b0,isn[`INSTRUCTION_RC]};
|
2027 |
|
|
default: fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
|
2028 |
|
|
endcase
|
2029 |
|
|
endfunction
|
2030 |
|
|
`endif
|
2031 |
|
|
|
2032 |
|
|
// Determines which lanes of the target register get updated.
|
2033 |
|
|
function [7:0] fnWe;
|
2034 |
|
|
input [47:0] isn;
|
2035 |
|
|
casez(isn[`INSTRUCTION_OP])
|
2036 |
|
|
`R2:
|
2037 |
|
|
case(isn[`INSTRUCTION_S2])
|
2038 |
|
|
`R1:
|
2039 |
|
|
case(isn[22:18])
|
2040 |
|
|
`ABS,`CNTLZ,`CNTLO,`CNTPOP:
|
2041 |
|
|
case(isn[25:23])
|
2042 |
|
|
3'b000: fnWe = 8'h01;
|
2043 |
|
|
3'b001: fnWe = 8'h03;
|
2044 |
|
|
3'b010: fnWe = 8'h0F;
|
2045 |
|
|
3'b011: fnWe = 8'hFF;
|
2046 |
|
|
default: fnWe = 8'hFF;
|
2047 |
|
|
endcase
|
2048 |
|
|
default: fnWe = 8'hFF;
|
2049 |
|
|
endcase
|
2050 |
|
|
`SHIFT31: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
2051 |
|
|
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
2052 |
|
|
`SLT,`SLTU,`SLE,`SLEU,
|
2053 |
|
|
`ADD,`SUB,
|
2054 |
|
|
`AND,`OR,`XOR,
|
2055 |
|
|
`NAND,`NOR,`XNOR,
|
2056 |
50 |
robfinch |
`DIV,`DIVU,`DIVSU,
|
2057 |
|
|
`MOD,`MODU,`MODSU,
|
2058 |
|
|
`MUL,`MULU,`MULSU,
|
2059 |
|
|
`MULH,`MULUH,`MULSUH:
|
2060 |
48 |
robfinch |
case(isn[25:23])
|
2061 |
|
|
3'b000: fnWe = 8'h01;
|
2062 |
|
|
3'b001: fnWe = 8'h03;
|
2063 |
|
|
3'b010: fnWe = 8'h0F;
|
2064 |
|
|
3'b011: fnWe = 8'hFF;
|
2065 |
|
|
default: fnWe = 8'hFF;
|
2066 |
|
|
endcase
|
2067 |
|
|
default: fnWe = 8'hFF;
|
2068 |
|
|
endcase
|
2069 |
|
|
default: fnWe = 8'hFF;
|
2070 |
|
|
endcase
|
2071 |
|
|
endfunction
|
2072 |
|
|
|
2073 |
|
|
// Detect if a source is automatically valid
|
2074 |
|
|
function Source1Valid;
|
2075 |
|
|
input [47:0] isn;
|
2076 |
|
|
casez(isn[`INSTRUCTION_OP])
|
2077 |
|
|
`BRK: Source1Valid = TRUE;
|
2078 |
|
|
`Bcc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2079 |
|
|
`BBc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2080 |
|
|
`BEQI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2081 |
|
|
`CHK: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2082 |
|
|
`RR: case(isn[`INSTRUCTION_S2])
|
2083 |
|
|
`SHIFT31: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2084 |
|
|
`SHIFT63: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2085 |
|
|
`SHIFTR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2086 |
|
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2087 |
|
|
endcase
|
2088 |
|
|
`MEMNDX:Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2089 |
|
|
`ADDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2090 |
|
|
`SLTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2091 |
|
|
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2092 |
|
|
`SGTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2093 |
|
|
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2094 |
|
|
`ANDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2095 |
|
|
`ORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2096 |
|
|
`XORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2097 |
|
|
`XNORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2098 |
|
|
`MULUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2099 |
|
|
`AMO: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2100 |
|
|
`LB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2101 |
|
|
`LBU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2102 |
|
|
`Lx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2103 |
|
|
`LxU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2104 |
|
|
`LWR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2105 |
|
|
`LV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2106 |
|
|
`LVx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2107 |
|
|
`SB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2108 |
|
|
`Sx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2109 |
|
|
`SWC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2110 |
|
|
`SV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2111 |
|
|
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2112 |
|
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2113 |
|
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2114 |
|
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2115 |
|
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
2116 |
51 |
robfinch |
`BITFIELD: case(isn[47:44])
|
2117 |
|
|
`BFINSI: Source1Valid = TRUE;
|
2118 |
|
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0 || isn[30]==1'b0;
|
2119 |
|
|
endcase
|
2120 |
48 |
robfinch |
`IVECTOR:
|
2121 |
51 |
robfinch |
Source1Valid = FALSE;
|
2122 |
48 |
robfinch |
default: Source1Valid = TRUE;
|
2123 |
|
|
endcase
|
2124 |
|
|
endfunction
|
2125 |
|
|
|
2126 |
|
|
function Source2Valid;
|
2127 |
|
|
input [47:0] isn;
|
2128 |
|
|
casez(isn[`INSTRUCTION_OP])
|
2129 |
|
|
`BRK: Source2Valid = TRUE;
|
2130 |
|
|
`Bcc: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2131 |
|
|
`BBc: Source2Valid = TRUE;
|
2132 |
|
|
`BEQI: Source2Valid = TRUE;
|
2133 |
|
|
`CHK: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2134 |
|
|
`RR: case(isn[`INSTRUCTION_S2])
|
2135 |
|
|
`R1: Source2Valid = TRUE;
|
2136 |
|
|
`SHIFTR: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
2137 |
|
|
`SHIFT31: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
2138 |
|
|
`SHIFT63: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
2139 |
|
|
`LVX,`SVX: Source2Valid = FALSE;
|
2140 |
|
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2141 |
|
|
endcase
|
2142 |
|
|
`MEMNDX:
|
2143 |
|
|
case(isn[`INSTRUCTION_S2])
|
2144 |
|
|
`LVX,`SVX: Source2Valid = FALSE;
|
2145 |
|
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2146 |
|
|
endcase
|
2147 |
|
|
`ADDI: Source2Valid = TRUE;
|
2148 |
|
|
`SLTI: Source2Valid = TRUE;
|
2149 |
|
|
`SLTUI: Source2Valid = TRUE;
|
2150 |
|
|
`SGTI: Source2Valid = TRUE;
|
2151 |
|
|
`SGTUI: Source2Valid = TRUE;
|
2152 |
|
|
`ANDI: Source2Valid = TRUE;
|
2153 |
|
|
`ORI: Source2Valid = TRUE;
|
2154 |
|
|
`XORI: Source2Valid = TRUE;
|
2155 |
|
|
`XNORI: Source2Valid = TRUE;
|
2156 |
|
|
`MULUI: Source2Valid = TRUE;
|
2157 |
|
|
`LB: Source2Valid = TRUE;
|
2158 |
|
|
`LBU: Source2Valid = TRUE;
|
2159 |
|
|
`Lx: Source2Valid = TRUE;
|
2160 |
|
|
`LxU: Source2Valid = TRUE;
|
2161 |
|
|
`LWR: Source2Valid = TRUE;
|
2162 |
|
|
`LVx: Source2Valid = TRUE;
|
2163 |
|
|
`INC: Source2Valid = TRUE;
|
2164 |
|
|
`SB: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2165 |
|
|
`Sx: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2166 |
|
|
`SWC: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2167 |
|
|
`CAS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2168 |
|
|
`JAL: Source2Valid = TRUE;
|
2169 |
|
|
`RET: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2170 |
|
|
`IVECTOR:
|
2171 |
|
|
case(isn[`INSTRUCTION_S2])
|
2172 |
|
|
`VABS: Source2Valid = TRUE;
|
2173 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
|
2174 |
|
|
Source2Valid = FALSE;
|
2175 |
|
|
`VADDS,`VSUBS,`VANDS,`VORS,`VXORS:
|
2176 |
|
|
Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2177 |
|
|
`VBITS2V: Source2Valid = TRUE;
|
2178 |
|
|
`V2BITS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
2179 |
|
|
`VSHL,`VSHR,`VASR: Source2Valid = isn[22:21]==2'd2;
|
2180 |
|
|
default: Source2Valid = FALSE;
|
2181 |
|
|
endcase
|
2182 |
|
|
`LV: Source2Valid = TRUE;
|
2183 |
|
|
`SV: Source2Valid = FALSE;
|
2184 |
|
|
`AMO: Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
|
2185 |
51 |
robfinch |
`BITFIELD: Source2Valid = isn[`INSTRUCTION_RB]==5'd0 || isn[31]==1'b0;
|
2186 |
48 |
robfinch |
default: Source2Valid = TRUE;
|
2187 |
|
|
endcase
|
2188 |
|
|
endfunction
|
2189 |
|
|
|
2190 |
|
|
function Source3Valid;
|
2191 |
|
|
input [47:0] isn;
|
2192 |
|
|
case(isn[`INSTRUCTION_OP])
|
2193 |
|
|
`IVECTOR:
|
2194 |
|
|
case(isn[`INSTRUCTION_S2])
|
2195 |
|
|
`VEX: Source3Valid = TRUE;
|
2196 |
|
|
default: Source3Valid = TRUE;
|
2197 |
|
|
endcase
|
2198 |
|
|
`CHK: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2199 |
|
|
`R2:
|
2200 |
|
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
2201 |
|
|
case(isn[47:42])
|
2202 |
|
|
`CMOVEZ,`CMOVNZ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2203 |
|
|
default: Source3Valid = TRUE;
|
2204 |
|
|
endcase
|
2205 |
|
|
else
|
2206 |
|
|
case(isn[`INSTRUCTION_S2])
|
2207 |
|
|
`SBX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2208 |
|
|
`SCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2209 |
|
|
`SHX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2210 |
|
|
`SWX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2211 |
|
|
`SWCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2212 |
|
|
`CASX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2213 |
|
|
`MAJ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2214 |
|
|
default: Source3Valid = TRUE;
|
2215 |
|
|
endcase
|
2216 |
|
|
`MEMNDX:
|
2217 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2218 |
|
|
case(isn[`INSTRUCTION_S2])
|
2219 |
|
|
`SBX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2220 |
|
|
`SCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2221 |
|
|
`SHX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2222 |
|
|
`SWX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2223 |
|
|
`SWCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2224 |
|
|
`CASX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
2225 |
|
|
default: Source3Valid = TRUE;
|
2226 |
|
|
endcase
|
2227 |
51 |
robfinch |
`BITFIELD: Source3Valid = isn[`INSTRUCTION_RC]==5'd0 || isn[32]==1'b0;
|
2228 |
48 |
robfinch |
default: Source3Valid = TRUE;
|
2229 |
|
|
endcase
|
2230 |
|
|
endfunction
|
2231 |
|
|
|
2232 |
|
|
// Used to indicate to the queue logic that the instruction needs to be
|
2233 |
|
|
// recycled to the queue VL number of times.
|
2234 |
|
|
function IsVector;
|
2235 |
|
|
input [47:0] isn;
|
2236 |
|
|
case(isn[`INSTRUCTION_OP])
|
2237 |
51 |
robfinch |
`MEMNDX:
|
2238 |
|
|
case(isn[`INSTRUCTION_S2])
|
2239 |
|
|
`LVX,`SVX: IsVector = TRUE;
|
2240 |
|
|
default: IsVector = FALSE;
|
2241 |
|
|
endcase
|
2242 |
48 |
robfinch |
`IVECTOR:
|
2243 |
51 |
robfinch |
case(isn[`INSTRUCTION_S2])
|
2244 |
|
|
`VMxx:
|
2245 |
|
|
case(isn[25:23])
|
2246 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
|
2247 |
|
|
IsVector = FALSE;
|
2248 |
|
|
default: IsVector = TRUE;
|
2249 |
|
|
endcase
|
2250 |
|
|
`VEINS: IsVector = FALSE;
|
2251 |
|
|
`VEX: IsVector = FALSE;
|
2252 |
|
|
default: IsVector = TRUE;
|
2253 |
|
|
endcase
|
2254 |
48 |
robfinch |
`LV,`SV: IsVector = TRUE;
|
2255 |
|
|
default: IsVector = FALSE;
|
2256 |
|
|
endcase
|
2257 |
|
|
endfunction
|
2258 |
|
|
|
2259 |
|
|
function IsVeins;
|
2260 |
|
|
input [47:0] isn;
|
2261 |
|
|
case(isn[`INSTRUCTION_OP])
|
2262 |
|
|
`IVECTOR: IsVeins = isn[`INSTRUCTION_S2]==`VEINS;
|
2263 |
|
|
default: IsVeins = FALSE;
|
2264 |
|
|
endcase
|
2265 |
|
|
endfunction
|
2266 |
|
|
|
2267 |
|
|
function IsVex;
|
2268 |
|
|
input [47:0] isn;
|
2269 |
|
|
case(isn[`INSTRUCTION_OP])
|
2270 |
|
|
`IVECTOR: IsVex = isn[`INSTRUCTION_S2]==`VEX;
|
2271 |
|
|
default: IsVex = FALSE;
|
2272 |
|
|
endcase
|
2273 |
|
|
endfunction
|
2274 |
|
|
|
2275 |
|
|
function IsVCmprss;
|
2276 |
|
|
input [47:0] isn;
|
2277 |
|
|
case(isn[`INSTRUCTION_OP])
|
2278 |
|
|
`IVECTOR: IsVCmprss = isn[`INSTRUCTION_S2]==`VCMPRSS || isn[`INSTRUCTION_S2]==`VCIDX;
|
2279 |
|
|
default: IsVCmprss = FALSE;
|
2280 |
|
|
endcase
|
2281 |
|
|
endfunction
|
2282 |
|
|
|
2283 |
|
|
function IsVShifti;
|
2284 |
|
|
input [47:0] isn;
|
2285 |
|
|
case(isn[`INSTRUCTION_OP])
|
2286 |
|
|
`IVECTOR:
|
2287 |
|
|
case(isn[`INSTRUCTION_S2])
|
2288 |
|
|
`VSHL,`VSHR,`VASR:
|
2289 |
|
|
IsVShifti = {isn[25],isn[22]}==2'd2;
|
2290 |
|
|
default: IsVShifti = FALSE;
|
2291 |
|
|
endcase
|
2292 |
|
|
default: IsVShifti = FALSE;
|
2293 |
|
|
endcase
|
2294 |
|
|
endfunction
|
2295 |
|
|
|
2296 |
|
|
function IsVLS;
|
2297 |
|
|
input [47:0] isn;
|
2298 |
|
|
case(isn[`INSTRUCTION_OP])
|
2299 |
|
|
`MEMNDX:
|
2300 |
|
|
case(isn[`INSTRUCTION_S2])
|
2301 |
|
|
`LVX,`SVX,`LVWS,`SVWS: IsVLS = TRUE;
|
2302 |
|
|
default: IsVLS = FALSE;
|
2303 |
|
|
endcase
|
2304 |
|
|
`LV,`SV: IsVLS = TRUE;
|
2305 |
|
|
default: IsVLS = FALSE;
|
2306 |
|
|
endcase
|
2307 |
|
|
endfunction
|
2308 |
|
|
|
2309 |
|
|
function [1:0] fnM2;
|
2310 |
|
|
input [31:0] isn;
|
2311 |
|
|
case(isn[`INSTRUCTION_OP])
|
2312 |
|
|
`RR: fnM2 = isn[24:23];
|
2313 |
|
|
default: fnM2 = 2'b00;
|
2314 |
|
|
endcase
|
2315 |
|
|
endfunction
|
2316 |
|
|
|
2317 |
|
|
function [0:0] IsMem;
|
2318 |
|
|
input [47:0] isn;
|
2319 |
|
|
case(isn[`INSTRUCTION_OP])
|
2320 |
|
|
`MEMNDX: IsMem = TRUE;
|
2321 |
|
|
`AMO: IsMem = TRUE;
|
2322 |
|
|
`LB: IsMem = TRUE;
|
2323 |
|
|
`LBU: IsMem = TRUE;
|
2324 |
|
|
`Lx: IsMem = TRUE;
|
2325 |
|
|
`LxU: IsMem = TRUE;
|
2326 |
|
|
`LWR: IsMem = TRUE;
|
2327 |
|
|
`LV,`SV: IsMem = TRUE;
|
2328 |
|
|
`INC: IsMem = TRUE;
|
2329 |
|
|
`SB: IsMem = TRUE;
|
2330 |
|
|
`Sx: IsMem = TRUE;
|
2331 |
|
|
`SWC: IsMem = TRUE;
|
2332 |
|
|
`CAS: IsMem = TRUE;
|
2333 |
|
|
`LVx: IsMem = TRUE;
|
2334 |
|
|
default: IsMem = FALSE;
|
2335 |
|
|
endcase
|
2336 |
|
|
endfunction
|
2337 |
|
|
|
2338 |
|
|
function IsMemNdx;
|
2339 |
|
|
input [47:0] isn;
|
2340 |
|
|
case(isn[`INSTRUCTION_OP])
|
2341 |
|
|
`MEMNDX: IsMemNdx = TRUE;
|
2342 |
|
|
default: IsMemNdx = FALSE;
|
2343 |
|
|
endcase
|
2344 |
|
|
endfunction
|
2345 |
|
|
|
2346 |
|
|
function IsLoad;
|
2347 |
|
|
input [47:0] isn;
|
2348 |
|
|
case(isn[`INSTRUCTION_OP])
|
2349 |
|
|
`MEMNDX:
|
2350 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2351 |
50 |
robfinch |
case(isn[`INSTRUCTION_S2])
|
2352 |
|
|
`LBX: IsLoad = TRUE;
|
2353 |
|
|
`LBUX: IsLoad = TRUE;
|
2354 |
|
|
`LCX: IsLoad = TRUE;
|
2355 |
|
|
`LCUX: IsLoad = TRUE;
|
2356 |
|
|
`LHX: IsLoad = TRUE;
|
2357 |
|
|
`LHUX: IsLoad = TRUE;
|
2358 |
|
|
`LWX: IsLoad = TRUE;
|
2359 |
|
|
`LVBX: IsLoad = TRUE;
|
2360 |
|
|
`LVBUX: IsLoad = TRUE;
|
2361 |
|
|
`LVCX: IsLoad = TRUE;
|
2362 |
|
|
`LVCUX: IsLoad = TRUE;
|
2363 |
|
|
`LVHX: IsLoad = TRUE;
|
2364 |
|
|
`LVHUX: IsLoad = TRUE;
|
2365 |
|
|
`LVWX: IsLoad = TRUE;
|
2366 |
|
|
`LWRX: IsLoad = TRUE;
|
2367 |
|
|
`LVX: IsLoad = TRUE;
|
2368 |
|
|
default: IsLoad = FALSE;
|
2369 |
|
|
endcase
|
2370 |
48 |
robfinch |
else
|
2371 |
|
|
IsLoad = FALSE;
|
2372 |
|
|
`LB: IsLoad = TRUE;
|
2373 |
|
|
`LBU: IsLoad = TRUE;
|
2374 |
|
|
`Lx: IsLoad = TRUE;
|
2375 |
|
|
`LxU: IsLoad = TRUE;
|
2376 |
|
|
`LWR: IsLoad = TRUE;
|
2377 |
|
|
`LV: IsLoad = TRUE;
|
2378 |
|
|
`LVx: IsLoad = TRUE;
|
2379 |
|
|
default: IsLoad = FALSE;
|
2380 |
|
|
endcase
|
2381 |
|
|
endfunction
|
2382 |
|
|
|
2383 |
|
|
function IsInc;
|
2384 |
|
|
input [47:0] isn;
|
2385 |
|
|
case(isn[`INSTRUCTION_OP])
|
2386 |
|
|
`MEMNDX:
|
2387 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2388 |
|
|
case(isn[`INSTRUCTION_S2])
|
2389 |
|
|
`INC: IsInc = TRUE;
|
2390 |
|
|
default: IsInc = FALSE;
|
2391 |
|
|
endcase
|
2392 |
|
|
else
|
2393 |
|
|
IsInc = FALSE;
|
2394 |
|
|
`INC: IsInc = TRUE;
|
2395 |
|
|
default: IsInc = FALSE;
|
2396 |
|
|
endcase
|
2397 |
|
|
endfunction
|
2398 |
|
|
|
2399 |
|
|
function IsSWC;
|
2400 |
|
|
input [47:0] isn;
|
2401 |
|
|
case(isn[`INSTRUCTION_OP])
|
2402 |
|
|
`MEMNDX:
|
2403 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2404 |
|
|
case(isn[`INSTRUCTION_S2])
|
2405 |
|
|
`SWCX: IsSWC = TRUE;
|
2406 |
|
|
default: IsSWC = FALSE;
|
2407 |
|
|
endcase
|
2408 |
|
|
else
|
2409 |
|
|
IsSWC = FALSE;
|
2410 |
|
|
`SWC: IsSWC = TRUE;
|
2411 |
|
|
default: IsSWC = FALSE;
|
2412 |
|
|
endcase
|
2413 |
|
|
endfunction
|
2414 |
|
|
|
2415 |
|
|
// Aquire / release bits are only available on indexed SWC / LWR
|
2416 |
|
|
function IsSWCX;
|
2417 |
|
|
input [47:0] isn;
|
2418 |
|
|
case(isn[`INSTRUCTION_OP])
|
2419 |
|
|
`MEMNDX:
|
2420 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2421 |
|
|
case(isn[`INSTRUCTION_S2])
|
2422 |
|
|
`SWCX: IsSWCX = TRUE;
|
2423 |
|
|
default: IsSWCX = FALSE;
|
2424 |
|
|
endcase
|
2425 |
|
|
else
|
2426 |
|
|
IsSWCX = FALSE;
|
2427 |
|
|
default: IsSWCX = FALSE;
|
2428 |
|
|
endcase
|
2429 |
|
|
endfunction
|
2430 |
|
|
|
2431 |
|
|
function IsLWR;
|
2432 |
|
|
input [47:0] isn;
|
2433 |
|
|
case(isn[`INSTRUCTION_OP])
|
2434 |
|
|
`MEMNDX:
|
2435 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2436 |
|
|
case(isn[`INSTRUCTION_S2])
|
2437 |
|
|
`LWRX: IsLWR = TRUE;
|
2438 |
|
|
default: IsLWR = FALSE;
|
2439 |
|
|
endcase
|
2440 |
|
|
else
|
2441 |
|
|
IsLWR = FALSE;
|
2442 |
|
|
`LWR: IsLWR = TRUE;
|
2443 |
|
|
default: IsLWR = FALSE;
|
2444 |
|
|
endcase
|
2445 |
|
|
endfunction
|
2446 |
|
|
|
2447 |
|
|
function IsLWRX;
|
2448 |
|
|
input [47:0] isn;
|
2449 |
|
|
case(isn[`INSTRUCTION_OP])
|
2450 |
|
|
`MEMNDX:
|
2451 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2452 |
|
|
case(isn[`INSTRUCTION_S2])
|
2453 |
|
|
`LWRX: IsLWRX = TRUE;
|
2454 |
|
|
default: IsLWRX = FALSE;
|
2455 |
|
|
endcase
|
2456 |
|
|
else
|
2457 |
|
|
IsLWRX = FALSE;
|
2458 |
|
|
default: IsLWRX = FALSE;
|
2459 |
|
|
endcase
|
2460 |
|
|
endfunction
|
2461 |
|
|
|
2462 |
|
|
function IsCAS;
|
2463 |
|
|
input [47:0] isn;
|
2464 |
|
|
case(isn[`INSTRUCTION_OP])
|
2465 |
|
|
`MEMNDX:
|
2466 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2467 |
|
|
case(isn[`INSTRUCTION_S2])
|
2468 |
|
|
`CASX: IsCAS = TRUE;
|
2469 |
|
|
default: IsCAS = FALSE;
|
2470 |
|
|
endcase
|
2471 |
|
|
else
|
2472 |
|
|
IsCAS = FALSE;
|
2473 |
|
|
`CAS: IsCAS = TRUE;
|
2474 |
|
|
default: IsCAS = FALSE;
|
2475 |
|
|
endcase
|
2476 |
|
|
endfunction
|
2477 |
|
|
|
2478 |
|
|
function IsAMO;
|
2479 |
|
|
input [47:0] isn;
|
2480 |
|
|
case(isn[`INSTRUCTION_OP])
|
2481 |
|
|
`AMO: IsAMO = TRUE;
|
2482 |
|
|
default: IsAMO = FALSE;
|
2483 |
|
|
endcase
|
2484 |
|
|
endfunction
|
2485 |
|
|
|
2486 |
|
|
// Really IsPredictableBranch
|
2487 |
|
|
// Does not include BccR's
|
2488 |
|
|
function IsBranch;
|
2489 |
|
|
input [47:0] isn;
|
2490 |
|
|
casez(isn[`INSTRUCTION_OP])
|
2491 |
|
|
`Bcc: IsBranch = TRUE;
|
2492 |
|
|
`BBc: IsBranch = TRUE;
|
2493 |
|
|
`BEQI: IsBranch = TRUE;
|
2494 |
|
|
`CHK: IsBranch = TRUE;
|
2495 |
|
|
default: IsBranch = FALSE;
|
2496 |
|
|
endcase
|
2497 |
|
|
endfunction
|
2498 |
|
|
|
2499 |
|
|
function IsWait;
|
2500 |
|
|
input [47:0] isn;
|
2501 |
|
|
IsWait = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`WAIT;
|
2502 |
|
|
endfunction
|
2503 |
|
|
|
2504 |
|
|
function IsCall;
|
2505 |
|
|
input [47:0] isn;
|
2506 |
|
|
IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
|
2507 |
|
|
endfunction
|
2508 |
|
|
|
2509 |
|
|
function IsJmp;
|
2510 |
|
|
input [47:0] isn;
|
2511 |
|
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
|
2512 |
|
|
endfunction
|
2513 |
|
|
|
2514 |
|
|
function IsFlowCtrl;
|
2515 |
|
|
input [47:0] isn;
|
2516 |
|
|
casez(isn[`INSTRUCTION_OP])
|
2517 |
|
|
`BRK: IsFlowCtrl = TRUE;
|
2518 |
49 |
robfinch |
`R2: case(isn[`INSTRUCTION_S2])
|
2519 |
48 |
robfinch |
`RTI: IsFlowCtrl = TRUE;
|
2520 |
|
|
default: IsFlowCtrl = FALSE;
|
2521 |
|
|
endcase
|
2522 |
|
|
`Bcc: IsFlowCtrl = TRUE;
|
2523 |
|
|
`BBc: IsFlowCtrl = TRUE;
|
2524 |
|
|
`BEQI: IsFlowCtrl = TRUE;
|
2525 |
|
|
`CHK: IsFlowCtrl = TRUE;
|
2526 |
|
|
`JAL: IsFlowCtrl = TRUE;
|
2527 |
|
|
`JMP: IsFlowCtrl = TRUE;
|
2528 |
|
|
`CALL: IsFlowCtrl = TRUE;
|
2529 |
|
|
`RET: IsFlowCtrl = TRUE;
|
2530 |
|
|
default: IsFlowCtrl = FALSE;
|
2531 |
|
|
endcase
|
2532 |
|
|
endfunction
|
2533 |
|
|
|
2534 |
|
|
function IsCache;
|
2535 |
|
|
input [47:0] isn;
|
2536 |
|
|
case(isn[`INSTRUCTION_OP])
|
2537 |
|
|
`MEMNDX:
|
2538 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2539 |
|
|
case(isn[`INSTRUCTION_S2])
|
2540 |
|
|
`CACHEX: IsCache = TRUE;
|
2541 |
|
|
default: IsCache = FALSE;
|
2542 |
|
|
endcase
|
2543 |
|
|
else
|
2544 |
|
|
IsCache = FALSE;
|
2545 |
|
|
`CACHE: IsCache = TRUE;
|
2546 |
|
|
default: IsCache = FALSE;
|
2547 |
|
|
endcase
|
2548 |
|
|
endfunction
|
2549 |
|
|
|
2550 |
|
|
function [4:0] CacheCmd;
|
2551 |
|
|
input [47:0] isn;
|
2552 |
|
|
case(isn[`INSTRUCTION_OP])
|
2553 |
|
|
`MEMNDX:
|
2554 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2555 |
|
|
case(isn[`INSTRUCTION_S2])
|
2556 |
|
|
`CACHEX: CacheCmd = isn[22:18];
|
2557 |
|
|
default: CacheCmd = 5'd0;
|
2558 |
|
|
endcase
|
2559 |
|
|
else
|
2560 |
|
|
CacheCmd = 5'd0;
|
2561 |
|
|
`CACHE: CacheCmd = isn[15:11];
|
2562 |
|
|
default: CacheCmd = 5'd0;
|
2563 |
|
|
endcase
|
2564 |
|
|
endfunction
|
2565 |
|
|
|
2566 |
|
|
function IsMemsb;
|
2567 |
|
|
input [47:0] isn;
|
2568 |
|
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
2569 |
|
|
endfunction
|
2570 |
|
|
|
2571 |
|
|
function IsSEI;
|
2572 |
|
|
input [47:0] isn;
|
2573 |
|
|
IsSEI = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`SEI);
|
2574 |
|
|
endfunction
|
2575 |
|
|
|
2576 |
|
|
function IsLV;
|
2577 |
|
|
input [47:0] isn;
|
2578 |
|
|
case(isn[`INSTRUCTION_OP])
|
2579 |
|
|
`MEMNDX:
|
2580 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2581 |
|
|
case(isn[`INSTRUCTION_S2])
|
2582 |
|
|
`LVX: IsLV = TRUE;
|
2583 |
|
|
default: IsLV = FALSE;
|
2584 |
|
|
endcase
|
2585 |
|
|
else
|
2586 |
|
|
IsLV = FALSE;
|
2587 |
|
|
`LV: IsLV = TRUE;
|
2588 |
|
|
default: IsLV = FALSE;
|
2589 |
|
|
endcase
|
2590 |
|
|
endfunction
|
2591 |
|
|
|
2592 |
|
|
function IsRFW;
|
2593 |
|
|
input [47:0] isn;
|
2594 |
|
|
input [5:0] vqei;
|
2595 |
|
|
input [5:0] vli;
|
2596 |
|
|
input thrd;
|
2597 |
|
|
if (fnRt(isn,vqei,vli,thrd)==12'd0)
|
2598 |
|
|
IsRFW = FALSE;
|
2599 |
|
|
else
|
2600 |
|
|
casez(isn[`INSTRUCTION_OP])
|
2601 |
|
|
`IVECTOR: IsRFW = TRUE;
|
2602 |
|
|
`FVECTOR: IsRFW = TRUE;
|
2603 |
|
|
`R2:
|
2604 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2605 |
|
|
case(isn[`INSTRUCTION_S2])
|
2606 |
|
|
`R1: IsRFW = TRUE;
|
2607 |
|
|
`ADD: IsRFW = TRUE;
|
2608 |
|
|
`SUB: IsRFW = TRUE;
|
2609 |
|
|
`SLT: IsRFW = TRUE;
|
2610 |
|
|
`SLTU: IsRFW = TRUE;
|
2611 |
|
|
`SLE: IsRFW = TRUE;
|
2612 |
|
|
`SLEU: IsRFW = TRUE;
|
2613 |
|
|
`AND: IsRFW = TRUE;
|
2614 |
|
|
`OR: IsRFW = TRUE;
|
2615 |
|
|
`XOR: IsRFW = TRUE;
|
2616 |
|
|
`MULU: IsRFW = TRUE;
|
2617 |
|
|
`MULSU: IsRFW = TRUE;
|
2618 |
|
|
`MUL: IsRFW = TRUE;
|
2619 |
50 |
robfinch |
`MULUH: IsRFW = TRUE;
|
2620 |
|
|
`MULSUH: IsRFW = TRUE;
|
2621 |
|
|
`MULH: IsRFW = TRUE;
|
2622 |
|
|
`DIVU: IsRFW = TRUE;
|
2623 |
|
|
`DIVSU: IsRFW = TRUE;
|
2624 |
|
|
`DIV:IsRFW = TRUE;
|
2625 |
|
|
`MODU: IsRFW = TRUE;
|
2626 |
|
|
`MODSU: IsRFW = TRUE;
|
2627 |
|
|
`MOD:IsRFW = TRUE;
|
2628 |
48 |
robfinch |
`MOV: IsRFW = TRUE;
|
2629 |
|
|
`VMOV: IsRFW = TRUE;
|
2630 |
|
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
2631 |
|
|
IsRFW = TRUE;
|
2632 |
|
|
`MIN,`MAX: IsRFW = TRUE;
|
2633 |
|
|
`SEI: IsRFW = TRUE;
|
2634 |
|
|
default: IsRFW = FALSE;
|
2635 |
|
|
endcase
|
2636 |
|
|
else
|
2637 |
|
|
IsRFW = FALSE;
|
2638 |
|
|
`MEMNDX:
|
2639 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2640 |
50 |
robfinch |
case(isn[`INSTRUCTION_S2])
|
2641 |
|
|
`LBX: IsRFW = TRUE;
|
2642 |
|
|
`LBUX: IsRFW = TRUE;
|
2643 |
|
|
`LCX: IsRFW = TRUE;
|
2644 |
|
|
`LCUX: IsRFW = TRUE;
|
2645 |
|
|
`LHX: IsRFW = TRUE;
|
2646 |
|
|
`LHUX: IsRFW = TRUE;
|
2647 |
|
|
`LWX: IsRFW = TRUE;
|
2648 |
|
|
`LVBX: IsRFW = TRUE;
|
2649 |
|
|
`LVBUX: IsRFW = TRUE;
|
2650 |
|
|
`LVCX: IsRFW = TRUE;
|
2651 |
|
|
`LVCUX: IsRFW = TRUE;
|
2652 |
|
|
`LVHX: IsRFW = TRUE;
|
2653 |
|
|
`LVHUX: IsRFW = TRUE;
|
2654 |
|
|
`LVWX: IsRFW = TRUE;
|
2655 |
|
|
`LWRX: IsRFW = TRUE;
|
2656 |
|
|
`LVX: IsRFW = TRUE;
|
2657 |
|
|
`CASX: IsRFW = TRUE;
|
2658 |
|
|
default: IsRFW = FALSE;
|
2659 |
|
|
endcase
|
2660 |
48 |
robfinch |
else
|
2661 |
|
|
IsRFW = FALSE;
|
2662 |
|
|
`BBc:
|
2663 |
|
|
case(isn[20:19])
|
2664 |
|
|
`IBNE: IsRFW = TRUE;
|
2665 |
|
|
`DBNZ: IsRFW = TRUE;
|
2666 |
|
|
default: IsRFW = FALSE;
|
2667 |
|
|
endcase
|
2668 |
|
|
`BITFIELD: IsRFW = TRUE;
|
2669 |
|
|
`ADDI: IsRFW = TRUE;
|
2670 |
|
|
`SLTI: IsRFW = TRUE;
|
2671 |
|
|
`SLTUI: IsRFW = TRUE;
|
2672 |
|
|
`SGTI: IsRFW = TRUE;
|
2673 |
|
|
`SGTUI: IsRFW = TRUE;
|
2674 |
|
|
`ANDI: IsRFW = TRUE;
|
2675 |
|
|
`ORI: IsRFW = TRUE;
|
2676 |
|
|
`XORI: IsRFW = TRUE;
|
2677 |
|
|
`MULUI: IsRFW = TRUE;
|
2678 |
|
|
`MULI: IsRFW = TRUE;
|
2679 |
|
|
`DIVUI: IsRFW = TRUE;
|
2680 |
|
|
`DIVI: IsRFW = TRUE;
|
2681 |
|
|
`MODI: IsRFW = TRUE;
|
2682 |
|
|
`JAL: IsRFW = TRUE;
|
2683 |
|
|
`CALL: IsRFW = TRUE;
|
2684 |
|
|
`RET: IsRFW = TRUE;
|
2685 |
|
|
`LB: IsRFW = TRUE;
|
2686 |
|
|
`LBU: IsRFW = TRUE;
|
2687 |
|
|
`Lx: IsRFW = TRUE;
|
2688 |
|
|
`LWR: IsRFW = TRUE;
|
2689 |
|
|
`LV: IsRFW = TRUE;
|
2690 |
|
|
`LVx: IsRFW = TRUE;
|
2691 |
|
|
`CAS: IsRFW = TRUE;
|
2692 |
|
|
`AMO: IsRFW = TRUE;
|
2693 |
|
|
`CSRRW: IsRFW = TRUE;
|
2694 |
|
|
default: IsRFW = FALSE;
|
2695 |
|
|
endcase
|
2696 |
|
|
endfunction
|
2697 |
|
|
|
2698 |
|
|
function IsShifti;
|
2699 |
|
|
input [47:0] isn;
|
2700 |
|
|
case(isn[`INSTRUCTION_OP])
|
2701 |
|
|
`R2:
|
2702 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
2703 |
|
|
case(isn[`INSTRUCTION_S2])
|
2704 |
|
|
`SHIFT31,`SHIFT63:
|
2705 |
|
|
IsShifti = TRUE;
|
2706 |
|
|
default: IsShifti = FALSE;
|
2707 |
|
|
endcase
|
2708 |
|
|
else
|
2709 |
|
|
IsShifti = FALSE;
|
2710 |
|
|
default: IsShifti = FALSE;
|
2711 |
|
|
endcase
|
2712 |
|
|
endfunction
|
2713 |
|
|
|
2714 |
|
|
function IsRtop;
|
2715 |
|
|
input [47:0] isn;
|
2716 |
|
|
case(isn[`INSTRUCTION_OP])
|
2717 |
|
|
`R2:
|
2718 |
|
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
2719 |
|
|
case(isn[47:42])
|
2720 |
|
|
`RTOP: IsRtop = TRUE;
|
2721 |
|
|
default: IsRtop = FALSE;
|
2722 |
|
|
endcase
|
2723 |
|
|
else
|
2724 |
|
|
IsRtop = FALSE;
|
2725 |
|
|
default: IsRtop = FALSE;
|
2726 |
|
|
endcase
|
2727 |
|
|
endfunction
|
2728 |
|
|
|
2729 |
|
|
function IsMul;
|
2730 |
|
|
input [47:0] isn;
|
2731 |
|
|
case(isn[`INSTRUCTION_OP])
|
2732 |
50 |
robfinch |
`R2:
|
2733 |
48 |
robfinch |
if (isn[`INSTRUCTION_L2]==2'b00)
|
2734 |
50 |
robfinch |
case(isn[`INSTRUCTION_S2])
|
2735 |
|
|
`MULU,`MULSU,`MUL: IsMul = TRUE;
|
2736 |
|
|
`MULUH,`MULSUH,`MULH: IsMul = TRUE;
|
2737 |
|
|
default: IsMul = FALSE;
|
2738 |
|
|
endcase
|
2739 |
48 |
robfinch |
else
|
2740 |
|
|
IsMul = FALSE;
|
2741 |
|
|
`MULUI,`MULI: IsMul = TRUE;
|
2742 |
|
|
default: IsMul = FALSE;
|
2743 |
|
|
endcase
|
2744 |
|
|
endfunction
|
2745 |
|
|
|
2746 |
|
|
function IsDivmod;
|
2747 |
|
|
input [47:0] isn;
|
2748 |
|
|
case(isn[`INSTRUCTION_OP])
|
2749 |
50 |
robfinch |
`R2:
|
2750 |
48 |
robfinch |
if (isn[`INSTRUCTION_L2]==2'b00)
|
2751 |
50 |
robfinch |
case(isn[`INSTRUCTION_S2])
|
2752 |
|
|
`DIVU,`DIVSU,`DIV: IsDivmod = TRUE;
|
2753 |
|
|
`MODU,`MODSU,`MOD: IsDivmod = TRUE;
|
2754 |
|
|
default: IsDivmod = FALSE;
|
2755 |
|
|
endcase
|
2756 |
48 |
robfinch |
else
|
2757 |
|
|
IsDivmod = FALSE;
|
2758 |
|
|
`DIVUI,`DIVI,`MODI: IsDivmod = TRUE;
|
2759 |
|
|
default: IsDivmod = FALSE;
|
2760 |
|
|
endcase
|
2761 |
|
|
endfunction
|
2762 |
|
|
|
2763 |
|
|
function IsExec;
|
2764 |
|
|
input [47:0] isn;
|
2765 |
|
|
case(isn[`INSTRUCTION_OP])
|
2766 |
|
|
`EXEC: IsExec = TRUE;
|
2767 |
|
|
default: IsExec = FALSE;
|
2768 |
|
|
endcase
|
2769 |
|
|
endfunction
|
2770 |
|
|
|
2771 |
|
|
function [7:0] fnSelect;
|
2772 |
|
|
input [47:0] ins;
|
2773 |
49 |
robfinch |
input [`ABITS] adr;
|
2774 |
48 |
robfinch |
begin
|
2775 |
|
|
case(ins[`INSTRUCTION_OP])
|
2776 |
|
|
`MEMNDX:
|
2777 |
|
|
if (ins[`INSTRUCTION_L2]==2'b00)
|
2778 |
|
|
case(ins[`INSTRUCTION_S2])
|
2779 |
|
|
`LBX,`LBUX,`SBX:
|
2780 |
|
|
case(adr[2:0])
|
2781 |
|
|
3'd0: fnSelect = 8'h01;
|
2782 |
|
|
3'd1: fnSelect = 8'h02;
|
2783 |
|
|
3'd2: fnSelect = 8'h04;
|
2784 |
|
|
3'd3: fnSelect = 8'h08;
|
2785 |
|
|
3'd4: fnSelect = 8'h10;
|
2786 |
|
|
3'd5: fnSelect = 8'h20;
|
2787 |
|
|
3'd6: fnSelect = 8'h40;
|
2788 |
|
|
3'd7: fnSelect = 8'h80;
|
2789 |
|
|
endcase
|
2790 |
|
|
`LCX,`LCUX,`SCX:
|
2791 |
|
|
case(adr[2:1])
|
2792 |
|
|
2'd0: fnSelect = 8'h03;
|
2793 |
|
|
2'd1: fnSelect = 8'h0C;
|
2794 |
|
|
2'd2: fnSelect = 8'h30;
|
2795 |
|
|
2'd3: fnSelect = 8'hC0;
|
2796 |
|
|
endcase
|
2797 |
|
|
`LHX,`LHUX,`SHX:
|
2798 |
|
|
case(adr[2])
|
2799 |
|
|
1'b0: fnSelect = 8'h0F;
|
2800 |
|
|
1'b1: fnSelect = 8'hF0;
|
2801 |
|
|
endcase
|
2802 |
|
|
`INC,
|
2803 |
|
|
`LWX,`SWX,`LWRX,`SWCX,`LVX,`SVX,`CASX:
|
2804 |
|
|
fnSelect = 8'hFF;
|
2805 |
|
|
`LVx: ;
|
2806 |
|
|
// case(ins[25:23])
|
2807 |
|
|
// `LVB,`LVBU:
|
2808 |
|
|
// case(adr[2:0])
|
2809 |
|
|
// 3'd0: fnSelect = 8'h01;
|
2810 |
|
|
// 3'd1: fnSelect = 8'h02;
|
2811 |
|
|
// 3'd2: fnSelect = 8'h04;
|
2812 |
|
|
// 3'd3: fnSelect = 8'h08;
|
2813 |
|
|
// 3'd4: fnSelect = 8'h10;
|
2814 |
|
|
// 3'd5: fnSelect = 8'h20;
|
2815 |
|
|
// 3'd6: fnSelect = 8'h40;
|
2816 |
|
|
// 3'd7: fnSelect = 8'h80;
|
2817 |
|
|
// endcase
|
2818 |
|
|
// `LVC,`LVCU:
|
2819 |
|
|
// case(adr[2:1])
|
2820 |
|
|
// 2'd0: fnSelect = 8'h03;
|
2821 |
|
|
// 2'd1: fnSelect = 8'h0C;
|
2822 |
|
|
// 2'd2: fnSelect = 8'h30;
|
2823 |
|
|
// 2'd3: fnSelect = 8'hC0;
|
2824 |
|
|
// endcase
|
2825 |
|
|
// `LVH,`LVHU:
|
2826 |
|
|
// case(adr[2])
|
2827 |
|
|
// 1'b0: fnSelect = 8'h0F;
|
2828 |
|
|
// 1'b1: fnSelect = 8'hF0;
|
2829 |
|
|
// endcase
|
2830 |
|
|
// `LVW:
|
2831 |
|
|
// fnSelect = 8'hFF;
|
2832 |
|
|
// endcase
|
2833 |
|
|
default: fnSelect = 8'h00;
|
2834 |
|
|
endcase
|
2835 |
|
|
else
|
2836 |
|
|
fnSelect = 8'h00;
|
2837 |
|
|
`LB,`LBU,`SB:
|
2838 |
|
|
case(adr[2:0])
|
2839 |
|
|
3'd0: fnSelect = 8'h01;
|
2840 |
|
|
3'd1: fnSelect = 8'h02;
|
2841 |
|
|
3'd2: fnSelect = 8'h04;
|
2842 |
|
|
3'd3: fnSelect = 8'h08;
|
2843 |
|
|
3'd4: fnSelect = 8'h10;
|
2844 |
|
|
3'd5: fnSelect = 8'h20;
|
2845 |
|
|
3'd6: fnSelect = 8'h40;
|
2846 |
|
|
3'd7: fnSelect = 8'h80;
|
2847 |
|
|
endcase
|
2848 |
|
|
`Lx,`LxU,`Sx:
|
2849 |
|
|
casez(ins[20:18])
|
2850 |
|
|
3'b100: fnSelect = 8'hFF;
|
2851 |
|
|
3'b?10: fnSelect = adr[2] ? 8'hF0 : 8'h0F;
|
2852 |
|
|
3'b??1:
|
2853 |
|
|
case(adr[2:1])
|
2854 |
|
|
2'd0: fnSelect = 8'h03;
|
2855 |
|
|
2'd1: fnSelect = 8'h0C;
|
2856 |
|
|
2'd2: fnSelect = 8'h30;
|
2857 |
|
|
2'd3: fnSelect = 8'hC0;
|
2858 |
|
|
endcase
|
2859 |
|
|
default: fnSelect = 8'h00;
|
2860 |
|
|
endcase
|
2861 |
|
|
`INC,
|
2862 |
|
|
`LWR,`SWC,`CAS: fnSelect = 8'hFF;
|
2863 |
|
|
`LV,`SV: fnSelect = 8'hFF;
|
2864 |
|
|
`AMO:
|
2865 |
|
|
case(ins[23:21])
|
2866 |
|
|
3'd0: fnSelect = {8'h01 << adr[2:0]};
|
2867 |
|
|
3'd1: fnSelect = {8'h03 << {adr[2:1],1'b0}};
|
2868 |
|
|
3'd2: fnSelect = {8'h0F << {adr[2],2'b00}};
|
2869 |
|
|
3'd3: fnSelect = 8'hFF;
|
2870 |
|
|
default: fnSelect = 8'hFF;
|
2871 |
|
|
endcase
|
2872 |
|
|
// `LVx:
|
2873 |
|
|
// `LVB,`LVBU:
|
2874 |
|
|
// case(adr[2:0])
|
2875 |
|
|
// 3'd0: fnSelect = 8'h01;
|
2876 |
|
|
// 3'd1: fnSelect = 8'h02;
|
2877 |
|
|
// 3'd2: fnSelect = 8'h04;
|
2878 |
|
|
// 3'd3: fnSelect = 8'h08;
|
2879 |
|
|
// 3'd4: fnSelect = 8'h10;
|
2880 |
|
|
// 3'd5: fnSelect = 8'h20;
|
2881 |
|
|
// 3'd6: fnSelect = 8'h40;
|
2882 |
|
|
// 3'd7: fnSelect = 8'h80;
|
2883 |
|
|
// endcase
|
2884 |
|
|
// `LVC,`LVCU:
|
2885 |
|
|
// case(adr[2:1])
|
2886 |
|
|
// 2'd0: fnSelect = 8'h03;
|
2887 |
|
|
// 2'd1: fnSelect = 8'h0C;
|
2888 |
|
|
// 2'd2: fnSelect = 8'h30;
|
2889 |
|
|
// 2'd3: fnSelect = 8'hC0;
|
2890 |
|
|
// endcase
|
2891 |
|
|
// `LVH,`LVHU:
|
2892 |
|
|
// case(adr[2])
|
2893 |
|
|
// 1'b0: fnSelect = 8'h0F;
|
2894 |
|
|
// 1'b1: fnSelect = 8'hF0;
|
2895 |
|
|
// endcase
|
2896 |
|
|
// `LVW:
|
2897 |
|
|
// fnSelect = 8'hFF;
|
2898 |
|
|
default: fnSelect = 8'h00;
|
2899 |
|
|
endcase
|
2900 |
|
|
end
|
2901 |
|
|
endfunction
|
2902 |
|
|
/*
|
2903 |
|
|
function [63:0] fnDatc;
|
2904 |
|
|
input [47:0] ins;
|
2905 |
|
|
input [63:0] dat;
|
2906 |
|
|
case(ins[`INSTRUCTION_OP])
|
2907 |
|
|
`R2:
|
2908 |
|
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
2909 |
|
|
case(ins[47:42])
|
2910 |
|
|
`FINDB: fnDatc = dat[7:0];
|
2911 |
|
|
`FINDC: fnDatc = dat[15:0];
|
2912 |
|
|
`FINDH: fnDatc = dat[31:0];
|
2913 |
|
|
`FINDW: fnDatc = dat[63:0];
|
2914 |
|
|
default: fnDatc = dat[63:0];
|
2915 |
|
|
endcase
|
2916 |
|
|
else
|
2917 |
|
|
fnDatc = dat[63:0];
|
2918 |
|
|
default: fnDatc = dat[63:0];
|
2919 |
|
|
endcase
|
2920 |
|
|
endfunction
|
2921 |
|
|
*/
|
2922 |
|
|
/*
|
2923 |
|
|
function [63:0] fnMemInc;
|
2924 |
|
|
input [47:0] ins;
|
2925 |
|
|
case(ins[`INSTRUCTION_OP])
|
2926 |
|
|
`R2:
|
2927 |
|
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
2928 |
|
|
case(ins[47:42])
|
2929 |
|
|
`FINDB: fnMemInc = 32'd1;
|
2930 |
|
|
`FINDC: fnMemInc = 32'd2;
|
2931 |
|
|
`FINDH: fnMemInc = 32'd4;
|
2932 |
|
|
`FINDW: fnMemInc = 32'd8;
|
2933 |
|
|
default: fnMemInc = 32'd8;
|
2934 |
|
|
endcase
|
2935 |
|
|
else
|
2936 |
|
|
fnMemInc = 32'd8;
|
2937 |
|
|
default: fnMemInc = 32'd8;
|
2938 |
|
|
endcase
|
2939 |
|
|
endfunction
|
2940 |
|
|
*/
|
2941 |
|
|
function [63:0] fnDati;
|
2942 |
|
|
input [47:0] ins;
|
2943 |
49 |
robfinch |
input [`ABITS] adr;
|
2944 |
48 |
robfinch |
input [63:0] dat;
|
2945 |
|
|
case(ins[`INSTRUCTION_OP])
|
2946 |
|
|
`MEMNDX:
|
2947 |
|
|
if (ins[`INSTRUCTION_L2]==2'b00)
|
2948 |
|
|
case(ins[`INSTRUCTION_S2])
|
2949 |
|
|
`LBX:
|
2950 |
|
|
case(adr[2:0])
|
2951 |
|
|
3'd0: fnDati = {{56{dat[7]}},dat[7:0]};
|
2952 |
|
|
3'd1: fnDati = {{56{dat[15]}},dat[15:8]};
|
2953 |
|
|
3'd2: fnDati = {{56{dat[23]}},dat[23:16]};
|
2954 |
|
|
3'd3: fnDati = {{56{dat[31]}},dat[31:24]};
|
2955 |
|
|
3'd4: fnDati = {{56{dat[39]}},dat[39:32]};
|
2956 |
|
|
3'd5: fnDati = {{56{dat[47]}},dat[47:40]};
|
2957 |
|
|
3'd6: fnDati = {{56{dat[55]}},dat[55:48]};
|
2958 |
|
|
3'd7: fnDati = {{56{dat[63]}},dat[63:56]};
|
2959 |
|
|
endcase
|
2960 |
|
|
`LBUX:
|
2961 |
|
|
case(adr[2:0])
|
2962 |
|
|
3'd0: fnDati = {{56{1'b0}},dat[7:0]};
|
2963 |
|
|
3'd1: fnDati = {{56{1'b0}},dat[15:8]};
|
2964 |
|
|
3'd2: fnDati = {{56{1'b0}},dat[23:16]};
|
2965 |
|
|
3'd3: fnDati = {{56{1'b0}},dat[31:24]};
|
2966 |
|
|
3'd4: fnDati = {{56{1'b0}},dat[39:32]};
|
2967 |
|
|
3'd5: fnDati = {{56{1'b0}},dat[47:40]};
|
2968 |
|
|
3'd6: fnDati = {{56{1'b0}},dat[55:48]};
|
2969 |
|
|
3'd7: fnDati = {{56{2'b0}},dat[63:56]};
|
2970 |
|
|
endcase
|
2971 |
|
|
`LCX:
|
2972 |
|
|
case(adr[2:1])
|
2973 |
|
|
2'd0: fnDati = {{48{dat[15]}},dat[15:0]};
|
2974 |
|
|
2'd1: fnDati = {{48{dat[31]}},dat[31:16]};
|
2975 |
|
|
2'd2: fnDati = {{48{dat[47]}},dat[47:32]};
|
2976 |
|
|
2'd3: fnDati = {{48{dat[63]}},dat[63:48]};
|
2977 |
|
|
endcase
|
2978 |
|
|
`LCUX:
|
2979 |
|
|
case(adr[2:1])
|
2980 |
|
|
2'd0: fnDati = {{48{1'b0}},dat[15:0]};
|
2981 |
|
|
2'd1: fnDati = {{48{1'b0}},dat[31:16]};
|
2982 |
|
|
2'd2: fnDati = {{48{1'b0}},dat[47:32]};
|
2983 |
|
|
2'd3: fnDati = {{48{1'b0}},dat[63:48]};
|
2984 |
|
|
endcase
|
2985 |
|
|
`LHX:
|
2986 |
|
|
case(adr[2])
|
2987 |
|
|
1'b0: fnDati = {{32{dat[31]}},dat[31:0]};
|
2988 |
|
|
1'b1: fnDati = {{32{dat[63]}},dat[63:32]};
|
2989 |
|
|
endcase
|
2990 |
|
|
`LHUX:
|
2991 |
|
|
case(adr[2])
|
2992 |
|
|
1'b0: fnDati = {{32{1'b0}},dat[31:0]};
|
2993 |
|
|
1'b1: fnDati = {{32{1'b0}},dat[63:32]};
|
2994 |
|
|
endcase
|
2995 |
|
|
`LWX,`LWRX,`LVX,`CAS: fnDati = dat;
|
2996 |
|
|
// `LVx:
|
2997 |
|
|
// case(ins[25:23])
|
2998 |
|
|
// `LVB:
|
2999 |
|
|
// case(adr[2:0])
|
3000 |
|
|
// 3'd0: fnDati = {{56{dat[7]}},dat[7:0]};
|
3001 |
|
|
// 3'd1: fnDati = {{56{dat[15]}},dat[15:8]};
|
3002 |
|
|
// 3'd2: fnDati = {{56{dat[23]}},dat[23:16]};
|
3003 |
|
|
// 3'd3: fnDati = {{56{dat[31]}},dat[31:24]};
|
3004 |
|
|
// 3'd4: fnDati = {{56{dat[39]}},dat[39:32]};
|
3005 |
|
|
// 3'd5: fnDati = {{56{dat[47]}},dat[47:40]};
|
3006 |
|
|
// 3'd6: fnDati = {{56{dat[55]}},dat[55:48]};
|
3007 |
|
|
// 3'd7: fnDati = {{56{dat[63]}},dat[63:56]};
|
3008 |
|
|
// endcase
|
3009 |
|
|
// `LVBU:
|
3010 |
|
|
// case(adr[2:0])
|
3011 |
|
|
// 3'd0: fnDati = {{56{1'b0}},dat[7:0]};
|
3012 |
|
|
// 3'd1: fnDati = {{56{1'b0}},dat[15:8]};
|
3013 |
|
|
// 3'd2: fnDati = {{56{1'b0}},dat[23:16]};
|
3014 |
|
|
// 3'd3: fnDati = {{56{1'b0}},dat[31:24]};
|
3015 |
|
|
// 3'd4: fnDati = {{56{1'b0}},dat[39:32]};
|
3016 |
|
|
// 3'd5: fnDati = {{56{1'b0}},dat[47:40]};
|
3017 |
|
|
// 3'd6: fnDati = {{56{1'b0}},dat[55:48]};
|
3018 |
|
|
// 3'd7: fnDati = {{56{2'b0}},dat[63:56]};
|
3019 |
|
|
// endcase
|
3020 |
|
|
// `LVC:
|
3021 |
|
|
// case(adr[2:1])
|
3022 |
|
|
// 2'd0: fnDati = {{48{dat[15]}},dat[15:0]};
|
3023 |
|
|
// 2'd1: fnDati = {{48{dat[31]}},dat[31:16]};
|
3024 |
|
|
// 2'd2: fnDati = {{48{dat[47]}},dat[47:32]};
|
3025 |
|
|
// 2'd3: fnDati = {{48{dat[63]}},dat[63:48]};
|
3026 |
|
|
// endcase
|
3027 |
|
|
// `LVCU:
|
3028 |
|
|
// case(adr[2:1])
|
3029 |
|
|
// 2'd0: fnDati = {{48{1'b0}},dat[15:0]};
|
3030 |
|
|
// 2'd1: fnDati = {{48{1'b0}},dat[31:16]};
|
3031 |
|
|
// 2'd2: fnDati = {{48{1'b0}},dat[47:32]};
|
3032 |
|
|
// 2'd3: fnDati = {{48{1'b0}},dat[63:48]};
|
3033 |
|
|
// endcase
|
3034 |
|
|
// `LVH:
|
3035 |
|
|
// case(adr[2])
|
3036 |
|
|
// 1'b0: fnDati = {{32{dat[31]}},dat[31:0]};
|
3037 |
|
|
// 1'b1: fnDati = {{32{dat[63]}},dat[63:32]};
|
3038 |
|
|
// endcase
|
3039 |
|
|
// `LVHU:
|
3040 |
|
|
// case(adr[2])
|
3041 |
|
|
// 1'b0: fnDati = {{32{1'b0}},dat[31:0]};
|
3042 |
|
|
// 1'b1: fnDati = {{32{1'b0}},dat[63:32]};
|
3043 |
|
|
// endcase
|
3044 |
|
|
// `LVW: fnDati = dat;
|
3045 |
|
|
// default: fnDati = dat;
|
3046 |
|
|
// endcase
|
3047 |
|
|
default: fnDati = dat;
|
3048 |
|
|
endcase
|
3049 |
|
|
else
|
3050 |
|
|
fnDati = dat;
|
3051 |
|
|
`LB:
|
3052 |
|
|
case(adr[2:0])
|
3053 |
|
|
3'd0: fnDati = {{56{dat[7]}},dat[7:0]};
|
3054 |
|
|
3'd1: fnDati = {{56{dat[15]}},dat[15:8]};
|
3055 |
|
|
3'd2: fnDati = {{56{dat[23]}},dat[23:16]};
|
3056 |
|
|
3'd3: fnDati = {{56{dat[31]}},dat[31:24]};
|
3057 |
|
|
3'd4: fnDati = {{56{dat[39]}},dat[39:32]};
|
3058 |
|
|
3'd5: fnDati = {{56{dat[47]}},dat[47:40]};
|
3059 |
|
|
3'd6: fnDati = {{56{dat[55]}},dat[55:48]};
|
3060 |
|
|
3'd7: fnDati = {{56{dat[63]}},dat[63:56]};
|
3061 |
|
|
endcase
|
3062 |
|
|
`LBU:
|
3063 |
|
|
case(adr[2:0])
|
3064 |
|
|
3'd0: fnDati = {{56{1'b0}},dat[7:0]};
|
3065 |
|
|
3'd1: fnDati = {{56{1'b0}},dat[15:8]};
|
3066 |
|
|
3'd2: fnDati = {{56{1'b0}},dat[23:16]};
|
3067 |
|
|
3'd3: fnDati = {{56{1'b0}},dat[31:24]};
|
3068 |
|
|
3'd4: fnDati = {{56{1'b0}},dat[39:32]};
|
3069 |
|
|
3'd5: fnDati = {{56{1'b0}},dat[47:40]};
|
3070 |
|
|
3'd6: fnDati = {{56{1'b0}},dat[55:48]};
|
3071 |
|
|
3'd7: fnDati = {{56{2'b0}},dat[63:56]};
|
3072 |
|
|
endcase
|
3073 |
|
|
`Lx:
|
3074 |
|
|
casez(ins[20:18])
|
3075 |
|
|
3'b100: fnDati = dat;
|
3076 |
|
|
3'b?10:
|
3077 |
|
|
case(adr[2])
|
3078 |
|
|
1'b0: fnDati = {{32{dat[31]}},dat[31:0]};
|
3079 |
|
|
1'b1: fnDati = {{32{dat[63]}},dat[63:32]};
|
3080 |
|
|
endcase
|
3081 |
|
|
3'b??1:
|
3082 |
|
|
case(adr[2:1])
|
3083 |
|
|
2'd0: fnDati = {{48{dat[15]}},dat[15:0]};
|
3084 |
|
|
2'd1: fnDati = {{48{dat[31]}},dat[31:16]};
|
3085 |
|
|
2'd2: fnDati = {{48{dat[47]}},dat[47:32]};
|
3086 |
|
|
2'd3: fnDati = {{48{dat[63]}},dat[63:48]};
|
3087 |
|
|
endcase
|
3088 |
|
|
endcase
|
3089 |
|
|
`LxU:
|
3090 |
|
|
casez(ins[20:18])
|
3091 |
|
|
3'b100: fnDati = dat;
|
3092 |
|
|
3'b?10:
|
3093 |
|
|
case(adr[2])
|
3094 |
|
|
1'b0: fnDati = {{32{1'b0}},dat[31:0]};
|
3095 |
|
|
1'b1: fnDati = {{32{1'b0}},dat[63:32]};
|
3096 |
|
|
endcase
|
3097 |
|
|
3'b??1:
|
3098 |
|
|
case(adr[2:1])
|
3099 |
|
|
2'd0: fnDati = {{48{1'b0}},dat[15:0]};
|
3100 |
|
|
2'd1: fnDati = {{48{1'b0}},dat[31:16]};
|
3101 |
|
|
2'd2: fnDati = {{48{1'b0}},dat[47:32]};
|
3102 |
|
|
2'd3: fnDati = {{48{1'b0}},dat[63:48]};
|
3103 |
|
|
endcase
|
3104 |
|
|
endcase
|
3105 |
|
|
`LWR,`LV,`CAS,`AMO: fnDati = dat;
|
3106 |
|
|
//`LVx:
|
3107 |
|
|
// case(ins[30:28])
|
3108 |
|
|
// `LVB:
|
3109 |
|
|
// case(adr[2:0])
|
3110 |
|
|
// 3'd0: fnDati = {{56{dat[7]}},dat[7:0]};
|
3111 |
|
|
// 3'd1: fnDati = {{56{dat[15]}},dat[15:8]};
|
3112 |
|
|
// 3'd2: fnDati = {{56{dat[23]}},dat[23:16]};
|
3113 |
|
|
// 3'd3: fnDati = {{56{dat[31]}},dat[31:24]};
|
3114 |
|
|
// 3'd4: fnDati = {{56{dat[39]}},dat[39:32]};
|
3115 |
|
|
// 3'd5: fnDati = {{56{dat[47]}},dat[47:40]};
|
3116 |
|
|
// 3'd6: fnDati = {{56{dat[55]}},dat[55:48]};
|
3117 |
|
|
// 3'd7: fnDati = {{56{dat[63]}},dat[63:56]};
|
3118 |
|
|
// endcase
|
3119 |
|
|
// `LVBU:
|
3120 |
|
|
// case(adr[2:0])
|
3121 |
|
|
// 3'd0: fnDati = {{56{1'b0}},dat[7:0]};
|
3122 |
|
|
// 3'd1: fnDati = {{56{1'b0}},dat[15:8]};
|
3123 |
|
|
// 3'd2: fnDati = {{56{1'b0}},dat[23:16]};
|
3124 |
|
|
// 3'd3: fnDati = {{56{1'b0}},dat[31:24]};
|
3125 |
|
|
// 3'd4: fnDati = {{56{1'b0}},dat[39:32]};
|
3126 |
|
|
// 3'd5: fnDati = {{56{1'b0}},dat[47:40]};
|
3127 |
|
|
// 3'd6: fnDati = {{56{1'b0}},dat[55:48]};
|
3128 |
|
|
// 3'd7: fnDati = {{56{2'b0}},dat[63:56]};
|
3129 |
|
|
// endcase
|
3130 |
|
|
// `LVC:
|
3131 |
|
|
// case(adr[2:1])
|
3132 |
|
|
// 2'd0: fnDati = {{48{dat[15]}},dat[15:0]};
|
3133 |
|
|
// 2'd1: fnDati = {{48{dat[31]}},dat[31:16]};
|
3134 |
|
|
// 2'd2: fnDati = {{48{dat[47]}},dat[47:32]};
|
3135 |
|
|
// 2'd3: fnDati = {{48{dat[63]}},dat[63:48]};
|
3136 |
|
|
// endcase
|
3137 |
|
|
// `LVCU:
|
3138 |
|
|
// case(adr[2:1])
|
3139 |
|
|
// 2'd0: fnDati = {{48{1'b0}},dat[15:0]};
|
3140 |
|
|
// 2'd1: fnDati = {{48{1'b0}},dat[31:16]};
|
3141 |
|
|
// 2'd2: fnDati = {{48{1'b0}},dat[47:32]};
|
3142 |
|
|
// 2'd3: fnDati = {{48{1'b0}},dat[63:48]};
|
3143 |
|
|
// endcase
|
3144 |
|
|
// `LVH:
|
3145 |
|
|
// case(adr[2])
|
3146 |
|
|
// 1'b0: fnDati = {{32{dat[31]}},dat[31:0]};
|
3147 |
|
|
// 1'b1: fnDati = {{32{dat[63]}},dat[63:32]};
|
3148 |
|
|
// endcase
|
3149 |
|
|
// `LVHU:
|
3150 |
|
|
// case(adr[2])
|
3151 |
|
|
// 1'b0: fnDati = {{32{1'b0}},dat[31:0]};
|
3152 |
|
|
// 1'b1: fnDati = {{32{1'b0}},dat[63:32]};
|
3153 |
|
|
// endcase
|
3154 |
|
|
//// `LVW: fnDati = dat;
|
3155 |
|
|
// default: fnDati = dat;
|
3156 |
|
|
// endcase
|
3157 |
|
|
default: fnDati = dat;
|
3158 |
|
|
endcase
|
3159 |
|
|
endfunction
|
3160 |
|
|
|
3161 |
|
|
function [63:0] fnDato;
|
3162 |
|
|
input [47:0] isn;
|
3163 |
|
|
input [63:0] dat;
|
3164 |
|
|
case(isn[`INSTRUCTION_OP])
|
3165 |
|
|
`MEMNDX:
|
3166 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
3167 |
|
|
case(isn[`INSTRUCTION_S2])
|
3168 |
|
|
`SBX: fnDato = {8{dat[7:0]}};
|
3169 |
|
|
`SCX: fnDato = {4{dat[15:0]}};
|
3170 |
|
|
`SHX: fnDato = {2{dat[31:0]}};
|
3171 |
|
|
default: fnDato = dat;
|
3172 |
|
|
endcase
|
3173 |
|
|
else
|
3174 |
|
|
fnDato = dat;
|
3175 |
|
|
`SB: fnDato = {8{dat[7:0]}};
|
3176 |
|
|
`Sx:
|
3177 |
49 |
robfinch |
casez(isn[20:18])
|
3178 |
48 |
robfinch |
3'b100: fnDato = dat;
|
3179 |
|
|
3'b?10: fnDato = {2{dat[31:0]}};
|
3180 |
|
|
3'b??1: fnDato = {4{dat[15:0]}};
|
3181 |
|
|
default: fnDato = dat;
|
3182 |
|
|
endcase
|
3183 |
|
|
`AMO:
|
3184 |
|
|
case(isn[23:21])
|
3185 |
|
|
3'd0: fnDato = {8{dat[7:0]}};
|
3186 |
|
|
3'd1: fnDato = {4{dat[15:0]}};
|
3187 |
|
|
3'd2: fnDato = {2{dat[31:0]}};
|
3188 |
|
|
3'd3: fnDato = dat;
|
3189 |
|
|
default: fnDato = dat;
|
3190 |
|
|
endcase
|
3191 |
|
|
default: fnDato = dat;
|
3192 |
|
|
endcase
|
3193 |
|
|
endfunction
|
3194 |
|
|
|
3195 |
|
|
// Indicate if the ALU instruction is valid immediately (single cycle operation)
|
3196 |
|
|
function IsSingleCycle;
|
3197 |
|
|
input [47:0] isn;
|
3198 |
|
|
IsSingleCycle = !(IsMul(isn)|IsDivmod(isn));
|
3199 |
|
|
endfunction
|
3200 |
|
|
|
3201 |
|
|
|
3202 |
|
|
`ifdef SUPPORT_SMT
|
3203 |
|
|
decoder8 iq0(.num({iqentry_tgt[0][8:7],iqentry_tgt[0][5:0]}), .out(iq0_out));
|
3204 |
|
|
decoder8 iq1(.num({iqentry_tgt[1][8:7],iqentry_tgt[1][5:0]}), .out(iq1_out));
|
3205 |
|
|
decoder8 iq2(.num({iqentry_tgt[2][8:7],iqentry_tgt[2][5:0]}), .out(iq2_out));
|
3206 |
|
|
decoder8 iq3(.num({iqentry_tgt[3][8:7],iqentry_tgt[3][5:0]}), .out(iq3_out));
|
3207 |
|
|
decoder8 iq4(.num({iqentry_tgt[4][8:7],iqentry_tgt[4][5:0]}), .out(iq4_out));
|
3208 |
|
|
decoder8 iq5(.num({iqentry_tgt[5][8:7],iqentry_tgt[5][5:0]}), .out(iq5_out));
|
3209 |
|
|
decoder8 iq6(.num({iqentry_tgt[6][8:7],iqentry_tgt[6][5:0]}), .out(iq6_out));
|
3210 |
|
|
decoder8 iq7(.num({iqentry_tgt[7][8:7],iqentry_tgt[7][5:0]}), .out(iq7_out));
|
3211 |
|
|
`else
|
3212 |
|
|
decoder7 iq0(.num({iqentry_tgt[0][7],iqentry_tgt[0][5:0]}), .out(iq0_out));
|
3213 |
|
|
decoder7 iq1(.num({iqentry_tgt[1][7],iqentry_tgt[1][5:0]}), .out(iq1_out));
|
3214 |
|
|
decoder7 iq2(.num({iqentry_tgt[2][7],iqentry_tgt[2][5:0]}), .out(iq2_out));
|
3215 |
|
|
decoder7 iq3(.num({iqentry_tgt[3][7],iqentry_tgt[3][5:0]}), .out(iq3_out));
|
3216 |
|
|
decoder7 iq4(.num({iqentry_tgt[4][7],iqentry_tgt[4][5:0]}), .out(iq4_out));
|
3217 |
|
|
decoder7 iq5(.num({iqentry_tgt[5][7],iqentry_tgt[5][5:0]}), .out(iq5_out));
|
3218 |
|
|
decoder7 iq6(.num({iqentry_tgt[6][7],iqentry_tgt[6][5:0]}), .out(iq6_out));
|
3219 |
|
|
decoder7 iq7(.num({iqentry_tgt[7][7],iqentry_tgt[7][5:0]}), .out(iq7_out));
|
3220 |
|
|
/*
|
3221 |
|
|
decoder6 iq0(.num({iqentry_tgt[0][5:0]}), .out(iq0_out));
|
3222 |
|
|
decoder6 iq1(.num({iqentry_tgt[1][5:0]}), .out(iq1_out));
|
3223 |
|
|
decoder6 iq2(.num({iqentry_tgt[2][5:0]}), .out(iq2_out));
|
3224 |
|
|
decoder6 iq3(.num({iqentry_tgt[3][5:0]}), .out(iq3_out));
|
3225 |
|
|
decoder6 iq4(.num({iqentry_tgt[4][5:0]}), .out(iq4_out));
|
3226 |
|
|
decoder6 iq5(.num({iqentry_tgt[5][5:0]}), .out(iq5_out));
|
3227 |
|
|
decoder6 iq6(.num({iqentry_tgt[6][5:0]}), .out(iq6_out));
|
3228 |
|
|
decoder6 iq7(.num({iqentry_tgt[7][5:0]}), .out(iq7_out));*/
|
3229 |
|
|
`endif
|
3230 |
|
|
|
3231 |
|
|
initial begin: Init
|
3232 |
|
|
//
|
3233 |
|
|
//
|
3234 |
|
|
// set up panic messages
|
3235 |
|
|
message[ `PANIC_NONE ] = "NONE ";
|
3236 |
|
|
message[ `PANIC_FETCHBUFBEQ ] = "FETCHBUFBEQ ";
|
3237 |
|
|
message[ `PANIC_INVALIDISLOT ] = "INVALIDISLOT ";
|
3238 |
|
|
message[ `PANIC_IDENTICALDRAMS ] = "IDENTICALDRAMS ";
|
3239 |
|
|
message[ `PANIC_OVERRUN ] = "OVERRUN ";
|
3240 |
|
|
message[ `PANIC_HALTINSTRUCTION ] = "HALTINSTRUCTION ";
|
3241 |
|
|
message[ `PANIC_INVALIDMEMOP ] = "INVALIDMEMOP ";
|
3242 |
|
|
message[ `PANIC_INVALIDFBSTATE ] = "INVALIDFBSTATE ";
|
3243 |
|
|
message[ `PANIC_INVALIDIQSTATE ] = "INVALIDIQSTATE ";
|
3244 |
|
|
message[ `PANIC_BRANCHBACK ] = "BRANCHBACK ";
|
3245 |
|
|
message[ `PANIC_MEMORYRACE ] = "MEMORYRACE ";
|
3246 |
|
|
message[ `PANIC_ALU0ONLY ] = "ALU0 Only ";
|
3247 |
|
|
|
3248 |
|
|
for (n = 0; n < 64; n = n + 1)
|
3249 |
|
|
codebuf[n] <= 48'h0;
|
3250 |
|
|
|
3251 |
|
|
end
|
3252 |
|
|
|
3253 |
|
|
// ---------------------------------------------------------------------------
|
3254 |
|
|
// FETCH
|
3255 |
|
|
// ---------------------------------------------------------------------------
|
3256 |
|
|
//
|
3257 |
|
|
assign fetchbuf0_mem = IsMem(fetchbuf0_instr);
|
3258 |
|
|
assign fetchbuf0_memld = IsMem(fetchbuf0_instr) & IsLoad(fetchbuf0_instr);
|
3259 |
|
|
assign fetchbuf0_rfw = IsRFW(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd);
|
3260 |
|
|
|
3261 |
|
|
assign fetchbuf1_mem = IsMem(fetchbuf1_instr);
|
3262 |
|
|
assign fetchbuf1_memld = IsMem(fetchbuf1_instr) & IsLoad(fetchbuf1_instr);
|
3263 |
|
|
assign fetchbuf1_rfw = IsRFW(fetchbuf1_instr,vqe1,vl,fetchbuf1_thrd);
|
3264 |
|
|
|
3265 |
|
|
FT64_fetchbuf #(AMSB,RSTPC) ufb1
|
3266 |
|
|
(
|
3267 |
49 |
robfinch |
.rst(rst),
|
3268 |
|
|
.clk4x(clk4x),
|
3269 |
|
|
.clk(clk),
|
3270 |
|
|
.fcu_clk(fcu_clk),
|
3271 |
|
|
.cs_i(adr_o[31:16]==16'hFFFF),
|
3272 |
|
|
.cyc_i(cyc_o),
|
3273 |
|
|
.stb_i(stb_o),
|
3274 |
|
|
.ack_o(dc_ack),
|
3275 |
|
|
.we_i(we_o),
|
3276 |
|
|
.adr_i(adr_o[15:0]),
|
3277 |
|
|
.dat_i(dat_o[31:0]),
|
3278 |
|
|
.hirq(hirq),
|
3279 |
|
|
.regLR(regLR),
|
3280 |
|
|
.thread_en(thread_en),
|
3281 |
|
|
.insn0(insn0),
|
3282 |
|
|
.insn1(insn1),
|
3283 |
|
|
.phit(phit),
|
3284 |
|
|
.threadx(threadx),
|
3285 |
|
|
.branchmiss(branchmiss),
|
3286 |
|
|
.misspc(misspc),
|
3287 |
|
|
.branchmiss_thrd(branchmiss_thrd),
|
3288 |
|
|
.predict_takenA(predict_takenA),
|
3289 |
|
|
.predict_takenB(predict_takenB),
|
3290 |
|
|
.predict_takenC(predict_takenC),
|
3291 |
|
|
.predict_takenD(predict_takenD),
|
3292 |
|
|
.predict_taken0(predict_taken0),
|
3293 |
|
|
.predict_taken1(predict_taken1),
|
3294 |
|
|
.queued1(queued1),
|
3295 |
|
|
.queued2(queued2),
|
3296 |
|
|
.queuedNop(queuedNop),
|
3297 |
|
|
.pc0(pc0),
|
3298 |
|
|
.pc1(pc1),
|
3299 |
|
|
.fetchbuf(fetchbuf),
|
3300 |
|
|
.fetchbufA_v(fetchbufA_v),
|
3301 |
|
|
.fetchbufB_v(fetchbufB_v),
|
3302 |
|
|
.fetchbufC_v(fetchbufC_v),
|
3303 |
|
|
.fetchbufD_v(fetchbufD_v),
|
3304 |
|
|
.fetchbufA_pc(fetchbufA_pc),
|
3305 |
|
|
.fetchbufB_pc(fetchbufB_pc),
|
3306 |
|
|
.fetchbufC_pc(fetchbufC_pc),
|
3307 |
|
|
.fetchbufD_pc(fetchbufD_pc),
|
3308 |
|
|
.fetchbufA_instr(fetchbufA_instr),
|
3309 |
|
|
.fetchbufB_instr(fetchbufB_instr),
|
3310 |
|
|
.fetchbufC_instr(fetchbufC_instr),
|
3311 |
|
|
.fetchbufD_instr(fetchbufD_instr),
|
3312 |
|
|
.fetchbuf0_instr(fetchbuf0_instr),
|
3313 |
|
|
.fetchbuf1_instr(fetchbuf1_instr),
|
3314 |
|
|
.fetchbuf0_thrd(fetchbuf0_thrd),
|
3315 |
|
|
.fetchbuf1_thrd(fetchbuf1_thrd),
|
3316 |
|
|
.fetchbuf0_pc(fetchbuf0_pc),
|
3317 |
|
|
.fetchbuf1_pc(fetchbuf1_pc),
|
3318 |
|
|
.fetchbuf0_v(fetchbuf0_v),
|
3319 |
|
|
.fetchbuf1_v(fetchbuf1_v),
|
3320 |
|
|
.fetchbuf0_insln(fetchbuf0_insln),
|
3321 |
|
|
.fetchbuf1_insln(fetchbuf1_insln),
|
3322 |
|
|
.codebuf0(codebuf[insn0[21:16]]),
|
3323 |
|
|
.codebuf1(codebuf[insn1[21:16]]),
|
3324 |
|
|
.btgtA(btgtA),
|
3325 |
|
|
.btgtB(btgtB),
|
3326 |
|
|
.btgtC(btgtC),
|
3327 |
|
|
.btgtD(btgtD),
|
3328 |
|
|
.nop_fetchbuf(nop_fetchbuf),
|
3329 |
|
|
.take_branch0(take_branch0),
|
3330 |
|
|
.take_branch1(take_branch1),
|
3331 |
|
|
.stompedRets(stompedOnRets),
|
3332 |
|
|
.panic(fb_panic)
|
3333 |
48 |
robfinch |
);
|
3334 |
|
|
|
3335 |
|
|
|
3336 |
|
|
|
3337 |
|
|
//initial begin: stop_at
|
3338 |
|
|
//#1000000; panic <= `PANIC_OVERRUN;
|
3339 |
|
|
//end
|
3340 |
|
|
|
3341 |
|
|
//
|
3342 |
|
|
// BRANCH-MISS LOGIC: livetarget
|
3343 |
|
|
//
|
3344 |
|
|
// livetarget implies that there is a not-to-be-stomped instruction that targets the register in question
|
3345 |
|
|
// therefore, if it is zero it implies the rf_v value should become VALID on a branchmiss
|
3346 |
|
|
//
|
3347 |
|
|
|
3348 |
|
|
generate begin : live_target
|
3349 |
|
|
for (g = 1; g < PREGS; g = g + 1) begin : lvtgt
|
3350 |
|
|
assign livetarget[g] = iqentry_0_livetarget[g] |
|
3351 |
|
|
iqentry_1_livetarget[g] |
|
3352 |
|
|
iqentry_2_livetarget[g] |
|
3353 |
|
|
iqentry_3_livetarget[g] |
|
3354 |
|
|
iqentry_4_livetarget[g] |
|
3355 |
|
|
iqentry_5_livetarget[g] |
|
3356 |
|
|
iqentry_6_livetarget[g] |
|
3357 |
|
|
iqentry_7_livetarget[g];
|
3358 |
|
|
end
|
3359 |
|
|
end
|
3360 |
|
|
endgenerate
|
3361 |
|
|
|
3362 |
|
|
assign iqentry_0_livetarget = {PREGS {iqentry_v[0]}} & {PREGS {~iqentry_stomp[0] && iqentry_thrd[0]==branchmiss_thrd}} & iq0_out,
|
3363 |
|
|
iqentry_1_livetarget = {PREGS {iqentry_v[1]}} & {PREGS {~iqentry_stomp[1] && iqentry_thrd[1]==branchmiss_thrd}} & iq1_out,
|
3364 |
|
|
iqentry_2_livetarget = {PREGS {iqentry_v[2]}} & {PREGS {~iqentry_stomp[2] && iqentry_thrd[2]==branchmiss_thrd}} & iq2_out,
|
3365 |
|
|
iqentry_3_livetarget = {PREGS {iqentry_v[3]}} & {PREGS {~iqentry_stomp[3] && iqentry_thrd[3]==branchmiss_thrd}} & iq3_out,
|
3366 |
|
|
iqentry_4_livetarget = {PREGS {iqentry_v[4]}} & {PREGS {~iqentry_stomp[4] && iqentry_thrd[4]==branchmiss_thrd}} & iq4_out,
|
3367 |
|
|
iqentry_5_livetarget = {PREGS {iqentry_v[5]}} & {PREGS {~iqentry_stomp[5] && iqentry_thrd[5]==branchmiss_thrd}} & iq5_out,
|
3368 |
|
|
iqentry_6_livetarget = {PREGS {iqentry_v[6]}} & {PREGS {~iqentry_stomp[6] && iqentry_thrd[6]==branchmiss_thrd}} & iq6_out,
|
3369 |
|
|
iqentry_7_livetarget = {PREGS {iqentry_v[7]}} & {PREGS {~iqentry_stomp[7] && iqentry_thrd[7]==branchmiss_thrd}} & iq7_out;
|
3370 |
|
|
|
3371 |
|
|
//
|
3372 |
|
|
// BRANCH-MISS LOGIC: latestID
|
3373 |
|
|
//
|
3374 |
|
|
// latestID is the instruction queue ID of the newest instruction (latest) that targets
|
3375 |
|
|
// a particular register. looks a lot like scheduling logic, but in reverse.
|
3376 |
|
|
//
|
3377 |
|
|
assign iqentry_0_cumulative = (missid==3'd0) ? iqentry_0_livetarget :
|
3378 |
|
|
(missid==3'd1) ? iqentry_0_livetarget |
|
3379 |
|
|
iqentry_1_livetarget :
|
3380 |
|
|
(missid==3'd2) ? iqentry_0_livetarget |
|
3381 |
|
|
iqentry_1_livetarget |
|
3382 |
|
|
iqentry_2_livetarget :
|
3383 |
|
|
(missid==3'd3) ? iqentry_0_livetarget |
|
3384 |
|
|
iqentry_1_livetarget |
|
3385 |
|
|
iqentry_2_livetarget |
|
3386 |
|
|
iqentry_3_livetarget :
|
3387 |
|
|
(missid==3'd4) ? iqentry_0_livetarget |
|
3388 |
|
|
iqentry_1_livetarget |
|
3389 |
|
|
iqentry_2_livetarget |
|
3390 |
|
|
iqentry_3_livetarget |
|
3391 |
|
|
iqentry_4_livetarget :
|
3392 |
|
|
(missid==3'd5) ? iqentry_0_livetarget |
|
3393 |
|
|
iqentry_1_livetarget |
|
3394 |
|
|
iqentry_2_livetarget |
|
3395 |
|
|
iqentry_3_livetarget |
|
3396 |
|
|
iqentry_4_livetarget |
|
3397 |
|
|
iqentry_5_livetarget :
|
3398 |
|
|
(missid==3'd6) ? iqentry_0_livetarget |
|
3399 |
|
|
iqentry_1_livetarget |
|
3400 |
|
|
iqentry_2_livetarget |
|
3401 |
|
|
iqentry_3_livetarget |
|
3402 |
|
|
iqentry_4_livetarget |
|
3403 |
|
|
iqentry_5_livetarget |
|
3404 |
|
|
iqentry_6_livetarget :
|
3405 |
|
|
(missid==3'd7) ? iqentry_0_livetarget |
|
3406 |
|
|
iqentry_1_livetarget |
|
3407 |
|
|
iqentry_2_livetarget |
|
3408 |
|
|
iqentry_3_livetarget |
|
3409 |
|
|
iqentry_4_livetarget |
|
3410 |
|
|
iqentry_5_livetarget |
|
3411 |
|
|
iqentry_6_livetarget |
|
3412 |
|
|
iqentry_7_livetarget :
|
3413 |
|
|
{PREGS{1'b0}};
|
3414 |
|
|
|
3415 |
|
|
assign iqentry_1_cumulative = (missid==3'd1) ? iqentry_1_livetarget :
|
3416 |
|
|
(missid==3'd2) ? iqentry_1_livetarget |
|
3417 |
|
|
iqentry_2_livetarget :
|
3418 |
|
|
(missid==3'd3) ? iqentry_1_livetarget |
|
3419 |
|
|
iqentry_2_livetarget |
|
3420 |
|
|
iqentry_3_livetarget :
|
3421 |
|
|
(missid==3'd4) ? iqentry_1_livetarget |
|
3422 |
|
|
iqentry_2_livetarget |
|
3423 |
|
|
iqentry_3_livetarget |
|
3424 |
|
|
iqentry_4_livetarget :
|
3425 |
|
|
(missid==3'd5) ? iqentry_1_livetarget |
|
3426 |
|
|
iqentry_2_livetarget |
|
3427 |
|
|
iqentry_3_livetarget |
|
3428 |
|
|
iqentry_4_livetarget |
|
3429 |
|
|
iqentry_5_livetarget :
|
3430 |
|
|
(missid==3'd6) ? iqentry_1_livetarget |
|
3431 |
|
|
iqentry_2_livetarget |
|
3432 |
|
|
iqentry_3_livetarget |
|
3433 |
|
|
iqentry_4_livetarget |
|
3434 |
|
|
iqentry_5_livetarget |
|
3435 |
|
|
iqentry_6_livetarget :
|
3436 |
|
|
(missid==3'd7) ? iqentry_1_livetarget |
|
3437 |
|
|
iqentry_2_livetarget |
|
3438 |
|
|
iqentry_3_livetarget |
|
3439 |
|
|
iqentry_4_livetarget |
|
3440 |
|
|
iqentry_5_livetarget |
|
3441 |
|
|
iqentry_6_livetarget |
|
3442 |
|
|
iqentry_7_livetarget :
|
3443 |
|
|
(missid==3'd0) ? iqentry_1_livetarget |
|
3444 |
|
|
iqentry_2_livetarget |
|
3445 |
|
|
iqentry_3_livetarget |
|
3446 |
|
|
iqentry_4_livetarget |
|
3447 |
|
|
iqentry_5_livetarget |
|
3448 |
|
|
iqentry_6_livetarget |
|
3449 |
|
|
iqentry_7_livetarget |
|
3450 |
|
|
iqentry_0_livetarget :
|
3451 |
|
|
{PREGS{1'b0}};
|
3452 |
|
|
|
3453 |
|
|
assign iqentry_2_cumulative = (missid==3'd2) ? iqentry_2_livetarget :
|
3454 |
|
|
(missid==3'd3) ? iqentry_2_livetarget |
|
3455 |
|
|
iqentry_3_livetarget :
|
3456 |
|
|
(missid==3'd4) ? iqentry_2_livetarget |
|
3457 |
|
|
iqentry_3_livetarget |
|
3458 |
|
|
iqentry_4_livetarget :
|
3459 |
|
|
(missid==3'd5) ? iqentry_2_livetarget |
|
3460 |
|
|
iqentry_3_livetarget |
|
3461 |
|
|
iqentry_4_livetarget |
|
3462 |
|
|
iqentry_5_livetarget :
|
3463 |
|
|
(missid==3'd6) ? iqentry_2_livetarget |
|
3464 |
|
|
iqentry_3_livetarget |
|
3465 |
|
|
iqentry_4_livetarget |
|
3466 |
|
|
iqentry_5_livetarget |
|
3467 |
|
|
iqentry_6_livetarget :
|
3468 |
|
|
(missid==3'd7) ? iqentry_2_livetarget |
|
3469 |
|
|
iqentry_3_livetarget |
|
3470 |
|
|
iqentry_4_livetarget |
|
3471 |
|
|
iqentry_5_livetarget |
|
3472 |
|
|
iqentry_6_livetarget |
|
3473 |
|
|
iqentry_7_livetarget :
|
3474 |
|
|
(missid==3'd0) ? iqentry_2_livetarget |
|
3475 |
|
|
iqentry_3_livetarget |
|
3476 |
|
|
iqentry_4_livetarget |
|
3477 |
|
|
iqentry_5_livetarget |
|
3478 |
|
|
iqentry_6_livetarget |
|
3479 |
|
|
iqentry_7_livetarget |
|
3480 |
|
|
iqentry_0_livetarget :
|
3481 |
|
|
(missid==3'd1) ? iqentry_2_livetarget |
|
3482 |
|
|
iqentry_3_livetarget |
|
3483 |
|
|
iqentry_4_livetarget |
|
3484 |
|
|
iqentry_5_livetarget |
|
3485 |
|
|
iqentry_6_livetarget |
|
3486 |
|
|
iqentry_7_livetarget |
|
3487 |
|
|
iqentry_0_livetarget |
|
3488 |
|
|
iqentry_1_livetarget :
|
3489 |
|
|
{PREGS{1'b0}};
|
3490 |
|
|
|
3491 |
|
|
assign iqentry_3_cumulative = (missid==3'd3) ? iqentry_3_livetarget :
|
3492 |
|
|
(missid==3'd4) ? iqentry_3_livetarget |
|
3493 |
|
|
iqentry_4_livetarget :
|
3494 |
|
|
(missid==3'd5) ? iqentry_3_livetarget |
|
3495 |
|
|
iqentry_4_livetarget |
|
3496 |
|
|
iqentry_5_livetarget :
|
3497 |
|
|
(missid==3'd6) ? iqentry_3_livetarget |
|
3498 |
|
|
iqentry_4_livetarget |
|
3499 |
|
|
iqentry_5_livetarget |
|
3500 |
|
|
iqentry_6_livetarget :
|
3501 |
|
|
(missid==3'd7) ? iqentry_3_livetarget |
|
3502 |
|
|
iqentry_4_livetarget |
|
3503 |
|
|
iqentry_5_livetarget |
|
3504 |
|
|
iqentry_6_livetarget |
|
3505 |
|
|
iqentry_7_livetarget :
|
3506 |
|
|
(missid==3'd0) ? iqentry_3_livetarget |
|
3507 |
|
|
iqentry_4_livetarget |
|
3508 |
|
|
iqentry_5_livetarget |
|
3509 |
|
|
iqentry_6_livetarget |
|
3510 |
|
|
iqentry_7_livetarget |
|
3511 |
|
|
iqentry_0_livetarget :
|
3512 |
|
|
(missid==3'd1) ? iqentry_3_livetarget |
|
3513 |
|
|
iqentry_4_livetarget |
|
3514 |
|
|
iqentry_5_livetarget |
|
3515 |
|
|
iqentry_6_livetarget |
|
3516 |
|
|
iqentry_7_livetarget |
|
3517 |
|
|
iqentry_0_livetarget |
|
3518 |
|
|
iqentry_1_livetarget :
|
3519 |
|
|
(missid==3'd2) ? iqentry_3_livetarget |
|
3520 |
|
|
iqentry_4_livetarget |
|
3521 |
|
|
iqentry_5_livetarget |
|
3522 |
|
|
iqentry_6_livetarget |
|
3523 |
|
|
iqentry_7_livetarget |
|
3524 |
|
|
iqentry_0_livetarget |
|
3525 |
|
|
iqentry_1_livetarget |
|
3526 |
|
|
iqentry_2_livetarget :
|
3527 |
|
|
{PREGS{1'b0}};
|
3528 |
|
|
|
3529 |
|
|
assign iqentry_4_cumulative = (missid==3'd4) ? iqentry_4_livetarget :
|
3530 |
|
|
(missid==3'd5) ? iqentry_4_livetarget |
|
3531 |
|
|
iqentry_5_livetarget :
|
3532 |
|
|
(missid==3'd6) ? iqentry_4_livetarget |
|
3533 |
|
|
iqentry_5_livetarget |
|
3534 |
|
|
iqentry_6_livetarget :
|
3535 |
|
|
(missid==3'd7) ? iqentry_4_livetarget |
|
3536 |
|
|
iqentry_5_livetarget |
|
3537 |
|
|
iqentry_6_livetarget |
|
3538 |
|
|
iqentry_7_livetarget :
|
3539 |
|
|
(missid==3'd0) ? iqentry_4_livetarget |
|
3540 |
|
|
iqentry_5_livetarget |
|
3541 |
|
|
iqentry_6_livetarget |
|
3542 |
|
|
iqentry_7_livetarget |
|
3543 |
|
|
iqentry_0_livetarget :
|
3544 |
|
|
(missid==3'd1) ? iqentry_4_livetarget |
|
3545 |
|
|
iqentry_5_livetarget |
|
3546 |
|
|
iqentry_6_livetarget |
|
3547 |
|
|
iqentry_7_livetarget |
|
3548 |
|
|
iqentry_0_livetarget |
|
3549 |
|
|
iqentry_1_livetarget :
|
3550 |
|
|
(missid==3'd2) ? iqentry_4_livetarget |
|
3551 |
|
|
iqentry_5_livetarget |
|
3552 |
|
|
iqentry_6_livetarget |
|
3553 |
|
|
iqentry_7_livetarget |
|
3554 |
|
|
iqentry_0_livetarget |
|
3555 |
|
|
iqentry_1_livetarget |
|
3556 |
|
|
iqentry_2_livetarget :
|
3557 |
|
|
(missid==3'd3) ? iqentry_4_livetarget |
|
3558 |
|
|
iqentry_5_livetarget |
|
3559 |
|
|
iqentry_6_livetarget |
|
3560 |
|
|
iqentry_7_livetarget |
|
3561 |
|
|
iqentry_0_livetarget |
|
3562 |
|
|
iqentry_1_livetarget |
|
3563 |
|
|
iqentry_2_livetarget |
|
3564 |
|
|
iqentry_3_livetarget :
|
3565 |
|
|
{PREGS{1'b0}};
|
3566 |
|
|
|
3567 |
|
|
assign iqentry_5_cumulative = (missid==3'd5) ? iqentry_5_livetarget :
|
3568 |
|
|
(missid==3'd6) ? iqentry_5_livetarget |
|
3569 |
|
|
iqentry_6_livetarget :
|
3570 |
|
|
(missid==3'd7) ? iqentry_5_livetarget |
|
3571 |
|
|
iqentry_6_livetarget |
|
3572 |
|
|
iqentry_7_livetarget :
|
3573 |
|
|
(missid==3'd0) ? iqentry_5_livetarget |
|
3574 |
|
|
iqentry_6_livetarget |
|
3575 |
|
|
iqentry_7_livetarget |
|
3576 |
|
|
iqentry_0_livetarget :
|
3577 |
|
|
(missid==3'd1) ? iqentry_5_livetarget |
|
3578 |
|
|
iqentry_6_livetarget |
|
3579 |
|
|
iqentry_7_livetarget |
|
3580 |
|
|
iqentry_0_livetarget |
|
3581 |
|
|
iqentry_1_livetarget :
|
3582 |
|
|
(missid==3'd2) ? iqentry_5_livetarget |
|
3583 |
|
|
iqentry_6_livetarget |
|
3584 |
|
|
iqentry_7_livetarget |
|
3585 |
|
|
iqentry_0_livetarget |
|
3586 |
|
|
iqentry_1_livetarget |
|
3587 |
|
|
iqentry_2_livetarget :
|
3588 |
|
|
(missid==3'd3) ? iqentry_5_livetarget |
|
3589 |
|
|
iqentry_6_livetarget |
|
3590 |
|
|
iqentry_7_livetarget |
|
3591 |
|
|
iqentry_0_livetarget |
|
3592 |
|
|
iqentry_1_livetarget |
|
3593 |
|
|
iqentry_2_livetarget |
|
3594 |
|
|
iqentry_3_livetarget :
|
3595 |
|
|
(missid==3'd4) ? iqentry_5_livetarget |
|
3596 |
|
|
iqentry_6_livetarget |
|
3597 |
|
|
iqentry_7_livetarget |
|
3598 |
|
|
iqentry_0_livetarget |
|
3599 |
|
|
iqentry_1_livetarget |
|
3600 |
|
|
iqentry_2_livetarget |
|
3601 |
|
|
iqentry_3_livetarget |
|
3602 |
|
|
iqentry_4_livetarget :
|
3603 |
|
|
{PREGS{1'b0}};
|
3604 |
|
|
assign iqentry_6_cumulative = (missid==3'd6) ? iqentry_6_livetarget :
|
3605 |
|
|
(missid==3'd7) ? iqentry_6_livetarget |
|
3606 |
|
|
iqentry_7_livetarget :
|
3607 |
|
|
(missid==3'd0) ? iqentry_6_livetarget |
|
3608 |
|
|
iqentry_7_livetarget |
|
3609 |
|
|
iqentry_0_livetarget :
|
3610 |
|
|
(missid==3'd1) ? iqentry_6_livetarget |
|
3611 |
|
|
iqentry_7_livetarget |
|
3612 |
|
|
iqentry_0_livetarget |
|
3613 |
|
|
iqentry_1_livetarget :
|
3614 |
|
|
(missid==3'd2) ? iqentry_6_livetarget |
|
3615 |
|
|
iqentry_7_livetarget |
|
3616 |
|
|
iqentry_0_livetarget |
|
3617 |
|
|
iqentry_1_livetarget |
|
3618 |
|
|
iqentry_2_livetarget :
|
3619 |
|
|
(missid==3'd3) ? iqentry_6_livetarget |
|
3620 |
|
|
iqentry_7_livetarget |
|
3621 |
|
|
iqentry_0_livetarget |
|
3622 |
|
|
iqentry_1_livetarget |
|
3623 |
|
|
iqentry_2_livetarget |
|
3624 |
|
|
iqentry_3_livetarget :
|
3625 |
|
|
(missid==3'd4) ? iqentry_6_livetarget |
|
3626 |
|
|
iqentry_7_livetarget |
|
3627 |
|
|
iqentry_0_livetarget |
|
3628 |
|
|
iqentry_1_livetarget |
|
3629 |
|
|
iqentry_2_livetarget |
|
3630 |
|
|
iqentry_3_livetarget |
|
3631 |
|
|
iqentry_4_livetarget :
|
3632 |
|
|
(missid==3'd5) ? iqentry_6_livetarget |
|
3633 |
|
|
iqentry_7_livetarget |
|
3634 |
|
|
iqentry_0_livetarget |
|
3635 |
|
|
iqentry_1_livetarget |
|
3636 |
|
|
iqentry_2_livetarget |
|
3637 |
|
|
iqentry_3_livetarget |
|
3638 |
|
|
iqentry_4_livetarget |
|
3639 |
|
|
iqentry_5_livetarget :
|
3640 |
|
|
{PREGS{1'b0}};
|
3641 |
|
|
|
3642 |
|
|
assign iqentry_7_cumulative = (missid==3'd7) ? iqentry_7_livetarget :
|
3643 |
|
|
(missid==3'd0) ? iqentry_7_livetarget |
|
3644 |
|
|
iqentry_0_livetarget :
|
3645 |
|
|
(missid==3'd1) ? iqentry_7_livetarget |
|
3646 |
|
|
iqentry_0_livetarget |
|
3647 |
|
|
iqentry_1_livetarget :
|
3648 |
|
|
(missid==3'd2) ? iqentry_7_livetarget |
|
3649 |
|
|
iqentry_0_livetarget |
|
3650 |
|
|
iqentry_1_livetarget |
|
3651 |
|
|
iqentry_2_livetarget :
|
3652 |
|
|
(missid==3'd3) ? iqentry_7_livetarget |
|
3653 |
|
|
iqentry_0_livetarget |
|
3654 |
|
|
iqentry_1_livetarget |
|
3655 |
|
|
iqentry_2_livetarget |
|
3656 |
|
|
iqentry_3_livetarget :
|
3657 |
|
|
(missid==3'd4) ? iqentry_7_livetarget |
|
3658 |
|
|
iqentry_0_livetarget |
|
3659 |
|
|
iqentry_1_livetarget |
|
3660 |
|
|
iqentry_2_livetarget |
|
3661 |
|
|
iqentry_3_livetarget |
|
3662 |
|
|
iqentry_4_livetarget :
|
3663 |
|
|
(missid==3'd5) ? iqentry_7_livetarget |
|
3664 |
|
|
iqentry_0_livetarget |
|
3665 |
|
|
iqentry_1_livetarget |
|
3666 |
|
|
iqentry_2_livetarget |
|
3667 |
|
|
iqentry_3_livetarget |
|
3668 |
|
|
iqentry_4_livetarget |
|
3669 |
|
|
iqentry_5_livetarget :
|
3670 |
|
|
(missid==3'd6) ? iqentry_7_livetarget |
|
3671 |
|
|
iqentry_0_livetarget |
|
3672 |
|
|
iqentry_1_livetarget |
|
3673 |
|
|
iqentry_2_livetarget |
|
3674 |
|
|
iqentry_3_livetarget |
|
3675 |
|
|
iqentry_4_livetarget |
|
3676 |
|
|
iqentry_5_livetarget |
|
3677 |
|
|
iqentry_6_livetarget :
|
3678 |
|
|
{PREGS{1'b0}};
|
3679 |
|
|
|
3680 |
|
|
assign iqentry_0_latestID = (missid == 3'd0 || ((iqentry_0_livetarget & iqentry_1_cumulative) == {PREGS{1'b0}}))
|
3681 |
|
|
? iqentry_0_livetarget
|
3682 |
|
|
: {PREGS{1'b0}};
|
3683 |
|
|
|
3684 |
|
|
assign iqentry_1_latestID = (missid == 3'd1 || ((iqentry_1_livetarget & iqentry_2_cumulative) == {PREGS{1'b0}}))
|
3685 |
|
|
? iqentry_1_livetarget
|
3686 |
|
|
: {PREGS{1'b0}};
|
3687 |
|
|
|
3688 |
|
|
assign iqentry_2_latestID = (missid == 3'd2 || ((iqentry_2_livetarget & iqentry_3_cumulative) == {PREGS{1'b0}}))
|
3689 |
|
|
? iqentry_2_livetarget
|
3690 |
|
|
: {PREGS{1'b0}};
|
3691 |
|
|
|
3692 |
|
|
assign iqentry_3_latestID = (missid == 3'd3 || ((iqentry_3_livetarget & iqentry_4_cumulative) == {PREGS{1'b0}}))
|
3693 |
|
|
? iqentry_3_livetarget
|
3694 |
|
|
: {PREGS{1'b0}};
|
3695 |
|
|
|
3696 |
|
|
assign iqentry_4_latestID = (missid == 3'd4 || ((iqentry_4_livetarget & iqentry_5_cumulative) == {PREGS{1'b0}}))
|
3697 |
|
|
? iqentry_4_livetarget
|
3698 |
|
|
: {PREGS{1'b0}};
|
3699 |
|
|
|
3700 |
|
|
assign iqentry_5_latestID = (missid == 3'd5 || ((iqentry_5_livetarget & iqentry_6_cumulative) == {PREGS{1'b0}}))
|
3701 |
|
|
? iqentry_5_livetarget
|
3702 |
|
|
: {PREGS{1'b0}};
|
3703 |
|
|
|
3704 |
|
|
assign iqentry_6_latestID = (missid == 3'd6 || ((iqentry_6_livetarget & iqentry_7_cumulative) == {PREGS{1'b0}}))
|
3705 |
|
|
? iqentry_6_livetarget
|
3706 |
|
|
: {PREGS{1'b0}};
|
3707 |
|
|
|
3708 |
|
|
assign iqentry_7_latestID = (missid == 3'd7 || ((iqentry_7_livetarget & iqentry_0_cumulative) == {PREGS{1'b0}}))
|
3709 |
|
|
? iqentry_7_livetarget
|
3710 |
|
|
: {PREGS{1'b0}};
|
3711 |
|
|
|
3712 |
49 |
robfinch |
assign iqentry_source[0] = | iqentry_0_latestID,
|
3713 |
|
|
iqentry_source[1] = | iqentry_1_latestID,
|
3714 |
|
|
iqentry_source[2] = | iqentry_2_latestID,
|
3715 |
|
|
iqentry_source[3] = | iqentry_3_latestID,
|
3716 |
|
|
iqentry_source[4] = | iqentry_4_latestID,
|
3717 |
|
|
iqentry_source[5] = | iqentry_5_latestID,
|
3718 |
|
|
iqentry_source[6] = | iqentry_6_latestID,
|
3719 |
|
|
iqentry_source[7] = | iqentry_7_latestID;
|
3720 |
48 |
robfinch |
|
3721 |
|
|
|
3722 |
|
|
reg vqueued2;
|
3723 |
|
|
assign Ra0 = fnRa(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
3724 |
|
|
assign Rb0 = fnRb(fetchbuf0_instr,1'b0,vqe0,rfoa0[5:0],rfoa1[5:0],fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
3725 |
|
|
assign Rc0 = fnRc(fetchbuf0_instr,vqe0,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
3726 |
|
|
assign Rt0 = fnRt(fetchbuf0_instr,vqet0,vl,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
|
3727 |
|
|
assign Ra1 = fnRa(fetchbuf1_instr,vqueued2 ? vqe0 + 1 : vqe1,vl,fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
|
3728 |
|
|
assign Rb1 = fnRb(fetchbuf1_instr,1'b1,vqueued2 ? vqe0 + 1 : vqe1,rfoa0[5:0],rfoa1[5:0],fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
|
3729 |
|
|
assign Rc1 = fnRc(fetchbuf1_instr,vqueued2 ? vqe0 + 1 : vqe1,fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
|
3730 |
|
|
assign Rt1 = fnRt(fetchbuf1_instr,vqueued2 ? vqet0 + 1 : vqet1,vl,fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
|
3731 |
|
|
|
3732 |
49 |
robfinch |
//
|
3733 |
|
|
// additional logic for ISSUE
|
3734 |
|
|
//
|
3735 |
|
|
// for the moment, we look at ALU-input buffers to allow back-to-back issue of
|
3736 |
|
|
// dependent instructions ... we do not, however, look ahead for DRAM requests
|
3737 |
|
|
// that will become valid in the next cycle. instead, these have to propagate
|
3738 |
|
|
// their results into the IQ entry directly, at which point it becomes issue-able
|
3739 |
|
|
//
|
3740 |
48 |
robfinch |
|
3741 |
49 |
robfinch |
// note that, for all intents & purposes, iqentry_done == iqentry_agen ... no need to duplicate
|
3742 |
48 |
robfinch |
|
3743 |
|
|
wire [QENTRIES-1:0] args_valid;
|
3744 |
|
|
wire [QENTRIES-1:0] could_issue;
|
3745 |
|
|
wire [QENTRIES-1:0] could_issueid;
|
3746 |
|
|
|
3747 |
|
|
generate begin : issue_logic
|
3748 |
|
|
for (g = 0; g < QENTRIES; g = g + 1)
|
3749 |
|
|
begin
|
3750 |
|
|
assign args_valid[g] =
|
3751 |
|
|
(iqentry_a1_v[g]
|
3752 |
49 |
robfinch |
`ifdef FU_BYPASS
|
3753 |
48 |
robfinch |
|| (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
|
3754 |
49 |
robfinch |
|| ((iqentry_a1_s[g] == alu1_sourceid && alu1_dataready) && (`NUM_ALU > 1))
|
3755 |
|
|
|| ((iqentry_a1_s[g] == fpu1_sourceid && fpu1_dataready) && (`NUM_FPU > 0))
|
3756 |
|
|
`endif
|
3757 |
|
|
)
|
3758 |
48 |
robfinch |
&& (iqentry_a2_v[g]
|
3759 |
|
|
|| (iqentry_mem[g] & ~iqentry_agen[g] & ~iqentry_memndx[g]) // a2 needs to be valid for indexed instruction
|
3760 |
49 |
robfinch |
`ifdef FU_BYPASS
|
3761 |
48 |
robfinch |
|| (iqentry_a2_s[g] == alu0_sourceid && alu0_dataready)
|
3762 |
49 |
robfinch |
|| ((iqentry_a2_s[g] == alu1_sourceid && alu1_dataready) && (`NUM_ALU > 1))
|
3763 |
|
|
|| ((iqentry_a2_s[g] == fpu1_sourceid && fpu1_dataready) && (`NUM_FPU > 0))
|
3764 |
|
|
`endif
|
3765 |
|
|
)
|
3766 |
48 |
robfinch |
&& (iqentry_a3_v[g]
|
3767 |
|
|
// || (iqentry_mem[g] & ~iqentry_agen[g])
|
3768 |
49 |
robfinch |
`ifdef FU_BYPASS
|
3769 |
48 |
robfinch |
|| (iqentry_a3_s[g] == alu0_sourceid && alu0_dataready)
|
3770 |
49 |
robfinch |
|| ((iqentry_a3_s[g] == alu1_sourceid && alu1_dataready) && (`NUM_ALU > 1))
|
3771 |
|
|
`endif
|
3772 |
|
|
)
|
3773 |
48 |
robfinch |
;
|
3774 |
|
|
|
3775 |
|
|
assign could_issue[g] = iqentry_v[g] && !iqentry_done[g] && !iqentry_out[g]
|
3776 |
|
|
&& args_valid[g]
|
3777 |
|
|
&& iqentry_iv[g]
|
3778 |
|
|
&& (iqentry_mem[g] ? !iqentry_agen[g] : 1'b1);
|
3779 |
|
|
|
3780 |
|
|
assign could_issueid[g] = iqentry_v[g] && !iqentry_iv[g];
|
3781 |
|
|
// && (iqentry_a1_v[g]
|
3782 |
|
|
// || (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
|
3783 |
|
|
// || (iqentry_a1_s[g] == alu1_sourceid && alu1_dataready));
|
3784 |
|
|
|
3785 |
|
|
end
|
3786 |
|
|
end
|
3787 |
|
|
endgenerate
|
3788 |
|
|
|
3789 |
|
|
// The (old) simulator didn't handle the asynchronous race loop properly in the
|
3790 |
|
|
// original code. It would issue two instructions to the same islot. So the
|
3791 |
|
|
// issue logic has been re-written to eliminate the asynchronous loop.
|
3792 |
|
|
// Can't issue to the ALU if it's busy doing a long running operation like a
|
3793 |
|
|
// divide.
|
3794 |
|
|
// ToDo: fix the memory synchronization, see fp_issue below
|
3795 |
|
|
|
3796 |
|
|
wire [`QBITS] heads [QENTRIES-1:0];
|
3797 |
|
|
assign heads[0] = head0;
|
3798 |
|
|
assign heads[1] = head1;
|
3799 |
|
|
assign heads[2] = head2;
|
3800 |
|
|
assign heads[3] = head3;
|
3801 |
|
|
assign heads[4] = head4;
|
3802 |
|
|
assign heads[5] = head5;
|
3803 |
|
|
assign heads[6] = head6;
|
3804 |
|
|
assign heads[7] = head7;
|
3805 |
|
|
|
3806 |
|
|
always @*
|
3807 |
|
|
begin
|
3808 |
49 |
robfinch |
iqentry_id1issue = {QENTRIES{1'b0}};
|
3809 |
48 |
robfinch |
if (id1_available) begin
|
3810 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
3811 |
49 |
robfinch |
if (could_issueid[heads[n]] && iqentry_id1issue=={QENTRIES{1'b0}})
|
3812 |
48 |
robfinch |
iqentry_id1issue[heads[n]] = `TRUE;
|
3813 |
|
|
end
|
3814 |
49 |
robfinch |
end
|
3815 |
|
|
generate begin : gIDUIssue
|
3816 |
|
|
if (`NUM_IDU > 1) begin
|
3817 |
|
|
always @*
|
3818 |
|
|
begin
|
3819 |
|
|
iqentry_id2issue = {QENTRIES{1'b0}};
|
3820 |
|
|
if (id2_available) begin
|
3821 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
3822 |
|
|
if (could_issueid[heads[n]] && !iqentry_id1issue[heads[n]] && iqentry_id2issue=={QENTRIES{1'b0}})
|
3823 |
|
|
iqentry_id2issue[heads[n]] = `TRUE;
|
3824 |
|
|
end
|
3825 |
|
|
end
|
3826 |
48 |
robfinch |
end
|
3827 |
49 |
robfinch |
if (`NUM_IDU > 2) begin
|
3828 |
|
|
always @*
|
3829 |
|
|
begin
|
3830 |
|
|
iqentry_id3issue = {QENTRIES{1'b0}};
|
3831 |
|
|
if (id3_available) begin
|
3832 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
3833 |
|
|
if (could_issueid[heads[n]]
|
3834 |
|
|
&& !iqentry_id1issue[heads[n]]
|
3835 |
|
|
&& !iqentry_id2issue[heads[n]]
|
3836 |
|
|
&& iqentry_id3issue=={QENTRIES{1'b0}})
|
3837 |
|
|
iqentry_id3issue[heads[n]] = `TRUE;
|
3838 |
|
|
end
|
3839 |
|
|
end
|
3840 |
|
|
end
|
3841 |
48 |
robfinch |
end
|
3842 |
49 |
robfinch |
endgenerate
|
3843 |
48 |
robfinch |
|
3844 |
|
|
always @*
|
3845 |
|
|
begin
|
3846 |
49 |
robfinch |
iqentry_alu0_issue = {QENTRIES{1'b0}};
|
3847 |
|
|
iqentry_alu1_issue = {QENTRIES{1'b0}};
|
3848 |
48 |
robfinch |
|
3849 |
|
|
if (alu0_available & alu0_idle) begin
|
3850 |
|
|
if (could_issue[head0] && iqentry_alu[head0]) begin
|
3851 |
|
|
iqentry_alu0_issue[head0] = `TRUE;
|
3852 |
|
|
end
|
3853 |
|
|
else if (could_issue[head1] && iqentry_alu[head1])
|
3854 |
|
|
begin
|
3855 |
|
|
iqentry_alu0_issue[head1] = `TRUE;
|
3856 |
|
|
end
|
3857 |
|
|
else if (could_issue[head2] && iqentry_alu[head2]
|
3858 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3859 |
|
|
)
|
3860 |
|
|
begin
|
3861 |
|
|
iqentry_alu0_issue[head2] = `TRUE;
|
3862 |
|
|
end
|
3863 |
|
|
else if (could_issue[head3] && iqentry_alu[head3]
|
3864 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3865 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
3866 |
|
|
((!iqentry_v[head0])
|
3867 |
|
|
&& (!iqentry_v[head1]))
|
3868 |
|
|
)
|
3869 |
|
|
) begin
|
3870 |
|
|
iqentry_alu0_issue[head3] = `TRUE;
|
3871 |
|
|
end
|
3872 |
|
|
else if (could_issue[head4] && iqentry_alu[head4]
|
3873 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3874 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
3875 |
|
|
((!iqentry_v[head0])
|
3876 |
|
|
&& (!iqentry_v[head1]))
|
3877 |
|
|
)
|
3878 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
3879 |
|
|
((!iqentry_v[head0])
|
3880 |
|
|
&& (!iqentry_v[head1])
|
3881 |
|
|
&& (!iqentry_v[head2]))
|
3882 |
|
|
)
|
3883 |
|
|
) begin
|
3884 |
|
|
iqentry_alu0_issue[head4] = `TRUE;
|
3885 |
|
|
end
|
3886 |
|
|
else if (could_issue[head5] && iqentry_alu[head5]
|
3887 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3888 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
3889 |
|
|
((!iqentry_v[head0])
|
3890 |
|
|
&& (!iqentry_v[head1]))
|
3891 |
|
|
)
|
3892 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
3893 |
|
|
((!iqentry_v[head0])
|
3894 |
|
|
&& (!iqentry_v[head1])
|
3895 |
|
|
&& (!iqentry_v[head2]))
|
3896 |
|
|
)
|
3897 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
3898 |
|
|
((!iqentry_v[head0])
|
3899 |
|
|
&& (!iqentry_v[head1])
|
3900 |
|
|
&& (!iqentry_v[head2])
|
3901 |
|
|
&& (!iqentry_v[head3]))
|
3902 |
|
|
)
|
3903 |
|
|
) begin
|
3904 |
|
|
iqentry_alu0_issue[head5] = `TRUE;
|
3905 |
|
|
end
|
3906 |
|
|
`ifdef FULL_ISSUE_LOGIC
|
3907 |
|
|
else if (could_issue[head6] && iqentry_alu[head6]
|
3908 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3909 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
3910 |
|
|
((!iqentry_v[head0])
|
3911 |
|
|
&& (!iqentry_v[head1]))
|
3912 |
|
|
)
|
3913 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
3914 |
|
|
((!iqentry_v[head0])
|
3915 |
|
|
&& (!iqentry_v[head1])
|
3916 |
|
|
&& (!iqentry_v[head2]))
|
3917 |
|
|
)
|
3918 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
3919 |
|
|
((!iqentry_v[head0])
|
3920 |
|
|
&& (!iqentry_v[head1])
|
3921 |
|
|
&& (!iqentry_v[head2])
|
3922 |
|
|
&& (!iqentry_v[head3]))
|
3923 |
|
|
)
|
3924 |
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
3925 |
|
|
((!iqentry_v[head0])
|
3926 |
|
|
&& (!iqentry_v[head1])
|
3927 |
|
|
&& (!iqentry_v[head2])
|
3928 |
|
|
&& (!iqentry_v[head3])
|
3929 |
|
|
&& (!iqentry_v[head4]))
|
3930 |
|
|
)
|
3931 |
|
|
) begin
|
3932 |
|
|
iqentry_alu0_issue[head6] = `TRUE;
|
3933 |
|
|
end
|
3934 |
|
|
else if (could_issue[head7] && iqentry_alu[head7]
|
3935 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3936 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
3937 |
|
|
((!iqentry_v[head0])
|
3938 |
|
|
&& (!iqentry_v[head1]))
|
3939 |
|
|
)
|
3940 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
3941 |
|
|
((!iqentry_v[head0])
|
3942 |
|
|
&& (!iqentry_v[head1])
|
3943 |
|
|
&& (!iqentry_v[head2]))
|
3944 |
|
|
)
|
3945 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
3946 |
|
|
((!iqentry_v[head0])
|
3947 |
|
|
&& (!iqentry_v[head1])
|
3948 |
|
|
&& (!iqentry_v[head2])
|
3949 |
|
|
&& (!iqentry_v[head3]))
|
3950 |
|
|
)
|
3951 |
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
3952 |
|
|
((!iqentry_v[head0])
|
3953 |
|
|
&& (!iqentry_v[head1])
|
3954 |
|
|
&& (!iqentry_v[head2])
|
3955 |
|
|
&& (!iqentry_v[head3])
|
3956 |
|
|
&& (!iqentry_v[head4]))
|
3957 |
|
|
)
|
3958 |
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
3959 |
|
|
((!iqentry_v[head0])
|
3960 |
|
|
&& (!iqentry_v[head1])
|
3961 |
|
|
&& (!iqentry_v[head2])
|
3962 |
|
|
&& (!iqentry_v[head3])
|
3963 |
|
|
&& (!iqentry_v[head4])
|
3964 |
|
|
&& (!iqentry_v[head5]))
|
3965 |
|
|
)
|
3966 |
|
|
) begin
|
3967 |
|
|
iqentry_alu0_issue[head7] = `TRUE;
|
3968 |
|
|
end
|
3969 |
|
|
`endif
|
3970 |
|
|
end
|
3971 |
|
|
|
3972 |
49 |
robfinch |
if (alu1_available && alu1_idle && `NUM_ALU > 1) begin
|
3973 |
48 |
robfinch |
if ((could_issue & ~iqentry_alu0_issue & ~iqentry_alu0) != 8'h00) begin
|
3974 |
|
|
if (could_issue[head0] && iqentry_alu[head0]
|
3975 |
|
|
&& !iqentry_alu0[head0] // alu0only
|
3976 |
|
|
&& !iqentry_alu0_issue[head0]) begin
|
3977 |
|
|
iqentry_alu1_issue[head0] = `TRUE;
|
3978 |
|
|
end
|
3979 |
|
|
else if (could_issue[head1] && !iqentry_alu0_issue[head1] && iqentry_alu[head1]
|
3980 |
|
|
&& !iqentry_alu0[head1])
|
3981 |
|
|
begin
|
3982 |
|
|
iqentry_alu1_issue[head1] = `TRUE;
|
3983 |
|
|
end
|
3984 |
|
|
else if (could_issue[head2] && !iqentry_alu0_issue[head2] && iqentry_alu[head2]
|
3985 |
|
|
&& !iqentry_alu0[head2]
|
3986 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3987 |
|
|
)
|
3988 |
|
|
begin
|
3989 |
|
|
iqentry_alu1_issue[head2] = `TRUE;
|
3990 |
|
|
end
|
3991 |
|
|
else if (could_issue[head3] && !iqentry_alu0_issue[head3] && iqentry_alu[head3]
|
3992 |
|
|
&& !iqentry_alu0[head3]
|
3993 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
3994 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
3995 |
|
|
((!iqentry_v[head0])
|
3996 |
|
|
&& (!iqentry_v[head1]))
|
3997 |
|
|
)
|
3998 |
|
|
) begin
|
3999 |
|
|
iqentry_alu1_issue[head3] = `TRUE;
|
4000 |
|
|
end
|
4001 |
|
|
else if (could_issue[head4] && !iqentry_alu0_issue[head4] && iqentry_alu[head4]
|
4002 |
|
|
&& !iqentry_alu0[head4]
|
4003 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4004 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4005 |
|
|
((!iqentry_v[head0])
|
4006 |
|
|
&& (!iqentry_v[head1]))
|
4007 |
|
|
)
|
4008 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4009 |
|
|
((!iqentry_v[head0])
|
4010 |
|
|
&& (!iqentry_v[head1])
|
4011 |
|
|
&& (!iqentry_v[head2]))
|
4012 |
|
|
)
|
4013 |
|
|
) begin
|
4014 |
|
|
iqentry_alu1_issue[head4] = `TRUE;
|
4015 |
|
|
end
|
4016 |
|
|
else if (could_issue[head5] && !iqentry_alu0_issue[head5] && iqentry_alu[head5]
|
4017 |
|
|
&& !iqentry_alu0[head5]
|
4018 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4019 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4020 |
|
|
((!iqentry_v[head0])
|
4021 |
|
|
&& (!iqentry_v[head1]))
|
4022 |
|
|
)
|
4023 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4024 |
|
|
((!iqentry_v[head0])
|
4025 |
|
|
&& (!iqentry_v[head1])
|
4026 |
|
|
&& (!iqentry_v[head2]))
|
4027 |
|
|
)
|
4028 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
4029 |
|
|
((!iqentry_v[head0])
|
4030 |
|
|
&& (!iqentry_v[head1])
|
4031 |
|
|
&& (!iqentry_v[head2])
|
4032 |
|
|
&& (!iqentry_v[head3]))
|
4033 |
|
|
)
|
4034 |
|
|
) begin
|
4035 |
|
|
iqentry_alu1_issue[head5] = `TRUE;
|
4036 |
|
|
end
|
4037 |
|
|
`ifdef FULL_ISSUE_LOGIC
|
4038 |
|
|
else if (could_issue[head6] && !iqentry_alu0_issue[head6] && iqentry_alu[head6]
|
4039 |
|
|
&& !iqentry_alu0[head6]
|
4040 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4041 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4042 |
|
|
((!iqentry_v[head0])
|
4043 |
|
|
&& (!iqentry_v[head1]))
|
4044 |
|
|
)
|
4045 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4046 |
|
|
((!iqentry_v[head0])
|
4047 |
|
|
&& (!iqentry_v[head1])
|
4048 |
|
|
&& (!iqentry_v[head2]))
|
4049 |
|
|
)
|
4050 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
4051 |
|
|
((!iqentry_v[head0])
|
4052 |
|
|
&& (!iqentry_v[head1])
|
4053 |
|
|
&& (!iqentry_v[head2])
|
4054 |
|
|
&& (!iqentry_v[head3]))
|
4055 |
|
|
)
|
4056 |
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
4057 |
|
|
((!iqentry_v[head0])
|
4058 |
|
|
&& (!iqentry_v[head1])
|
4059 |
|
|
&& (!iqentry_v[head2])
|
4060 |
|
|
&& (!iqentry_v[head3])
|
4061 |
|
|
&& (!iqentry_v[head4]))
|
4062 |
|
|
)
|
4063 |
|
|
) begin
|
4064 |
|
|
iqentry_alu1_issue[head6] = `TRUE;
|
4065 |
|
|
end
|
4066 |
|
|
else if (could_issue[head7] && !iqentry_alu0_issue[head7] && iqentry_alu[head7]
|
4067 |
|
|
&& !iqentry_alu0[head7]
|
4068 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4069 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4070 |
|
|
((!iqentry_v[head0])
|
4071 |
|
|
&& (!iqentry_v[head1]))
|
4072 |
|
|
)
|
4073 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4074 |
|
|
((!iqentry_v[head0])
|
4075 |
|
|
&& (!iqentry_v[head1])
|
4076 |
|
|
&& (!iqentry_v[head2]))
|
4077 |
|
|
)
|
4078 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
4079 |
|
|
((!iqentry_v[head0])
|
4080 |
|
|
&& (!iqentry_v[head1])
|
4081 |
|
|
&& (!iqentry_v[head2])
|
4082 |
|
|
&& (!iqentry_v[head3]))
|
4083 |
|
|
)
|
4084 |
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
4085 |
|
|
((!iqentry_v[head0])
|
4086 |
|
|
&& (!iqentry_v[head1])
|
4087 |
|
|
&& (!iqentry_v[head2])
|
4088 |
|
|
&& (!iqentry_v[head3])
|
4089 |
|
|
&& (!iqentry_v[head4]))
|
4090 |
|
|
)
|
4091 |
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
4092 |
|
|
((!iqentry_v[head0])
|
4093 |
|
|
&& (!iqentry_v[head1])
|
4094 |
|
|
&& (!iqentry_v[head2])
|
4095 |
|
|
&& (!iqentry_v[head3])
|
4096 |
|
|
&& (!iqentry_v[head4])
|
4097 |
|
|
&& (!iqentry_v[head5]))
|
4098 |
|
|
)
|
4099 |
|
|
) begin
|
4100 |
|
|
iqentry_alu1_issue[head7] = `TRUE;
|
4101 |
|
|
end
|
4102 |
|
|
`endif
|
4103 |
|
|
end
|
4104 |
|
|
// aluissue(alu0_idle,8'h00,2'b00);
|
4105 |
|
|
// aluissue(alu1_idle,iqentry_alu0,2'b01);
|
4106 |
|
|
end
|
4107 |
|
|
end
|
4108 |
|
|
|
4109 |
|
|
always @*
|
4110 |
|
|
begin
|
4111 |
49 |
robfinch |
iqentry_fpu1_issue = {QENTRIES{1'b0}};
|
4112 |
|
|
// fpu1issue(fpu1_idle,2'b00);
|
4113 |
|
|
if (fpu1_idle && `NUM_FPU > 0) begin
|
4114 |
48 |
robfinch |
if (could_issue[head0] && iqentry_fpu[head0]) begin
|
4115 |
49 |
robfinch |
iqentry_fpu1_issue[head0] = `TRUE;
|
4116 |
48 |
robfinch |
end
|
4117 |
|
|
else if (could_issue[head1] && iqentry_fpu[head1])
|
4118 |
|
|
begin
|
4119 |
49 |
robfinch |
iqentry_fpu1_issue[head1] = `TRUE;
|
4120 |
48 |
robfinch |
end
|
4121 |
|
|
else if (could_issue[head2] && iqentry_fpu[head2]
|
4122 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4123 |
|
|
) begin
|
4124 |
49 |
robfinch |
iqentry_fpu1_issue[head2] = `TRUE;
|
4125 |
48 |
robfinch |
end
|
4126 |
|
|
else if (could_issue[head3] && iqentry_fpu[head3]
|
4127 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4128 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4129 |
|
|
((!iqentry_v[head0])
|
4130 |
|
|
&& (!iqentry_v[head1]))
|
4131 |
|
|
)
|
4132 |
|
|
) begin
|
4133 |
49 |
robfinch |
iqentry_fpu1_issue[head3] = `TRUE;
|
4134 |
48 |
robfinch |
end
|
4135 |
|
|
else if (could_issue[head4] && iqentry_fpu[head4]
|
4136 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4137 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4138 |
|
|
((!iqentry_v[head0])
|
4139 |
|
|
&& (!iqentry_v[head1]))
|
4140 |
|
|
)
|
4141 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4142 |
|
|
((!iqentry_v[head0])
|
4143 |
|
|
&& (!iqentry_v[head1])
|
4144 |
|
|
&& (!iqentry_v[head2]))
|
4145 |
|
|
)
|
4146 |
|
|
) begin
|
4147 |
49 |
robfinch |
iqentry_fpu1_issue[head4] = `TRUE;
|
4148 |
48 |
robfinch |
end
|
4149 |
|
|
else if (could_issue[head5] && iqentry_fpu[head5]
|
4150 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4151 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4152 |
|
|
((!iqentry_v[head0])
|
4153 |
|
|
&& (!iqentry_v[head1]))
|
4154 |
|
|
)
|
4155 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4156 |
|
|
((!iqentry_v[head0])
|
4157 |
|
|
&& (!iqentry_v[head1])
|
4158 |
|
|
&& (!iqentry_v[head2]))
|
4159 |
|
|
)
|
4160 |
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
4161 |
|
|
((!iqentry_v[head0])
|
4162 |
|
|
&& (!iqentry_v[head1])
|
4163 |
|
|
&& (!iqentry_v[head2])
|
4164 |
|
|
&& (!iqentry_v[head3]))
|
4165 |
|
|
)
|
4166 |
|
|
) begin
|
4167 |
49 |
robfinch |
iqentry_fpu1_issue[head5] = `TRUE;
|
4168 |
48 |
robfinch |
end
|
4169 |
|
|
`ifdef FULL_ISSUE_LOGIC
|
4170 |
|
|
else if (could_issue[head6] && iqentry_fpu[head6]
|
4171 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4172 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4173 |
|
|
((!iqentry_v[head0])
|
4174 |
|
|
&& (!iqentry_v[head1]))
|
4175 |
|
|
)
|
4176 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4177 |
|
|
((!iqentry_v[head0])
|
4178 |
|
|
&& (!iqentry_v[head1])
|
4179 |
|
|
&& (!iqentry_v[head2]))
|
4180 |
|
|
)
|
4181 |
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
4182 |
|
|
((!iqentry_v[head0])
|
4183 |
|
|
&& (!iqentry_v[head1])
|
4184 |
|
|
&& (!iqentry_v[head2])
|
4185 |
|
|
&& (!iqentry_v[head3]))
|
4186 |
|
|
)
|
4187 |
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
4188 |
|
|
((!iqentry_v[head0])
|
4189 |
|
|
&& (!iqentry_v[head1])
|
4190 |
|
|
&& (!iqentry_v[head2])
|
4191 |
|
|
&& (!iqentry_v[head3])
|
4192 |
|
|
&& (!iqentry_v[head4]))
|
4193 |
|
|
)
|
4194 |
|
|
) begin
|
4195 |
49 |
robfinch |
iqentry_fpu1_issue[head6] = `TRUE;
|
4196 |
48 |
robfinch |
end
|
4197 |
|
|
else if (could_issue[head7] && iqentry_fpu[head7]
|
4198 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4199 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4200 |
|
|
((!iqentry_v[head0])
|
4201 |
|
|
&& (!iqentry_v[head1]))
|
4202 |
|
|
)
|
4203 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4204 |
|
|
((!iqentry_v[head0])
|
4205 |
|
|
&& (!iqentry_v[head1])
|
4206 |
|
|
&& (!iqentry_v[head2]))
|
4207 |
|
|
)
|
4208 |
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
4209 |
|
|
((!iqentry_v[head0])
|
4210 |
|
|
&& (!iqentry_v[head1])
|
4211 |
|
|
&& (!iqentry_v[head2])
|
4212 |
|
|
&& (!iqentry_v[head3]))
|
4213 |
|
|
)
|
4214 |
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
4215 |
|
|
((!iqentry_v[head0])
|
4216 |
|
|
&& (!iqentry_v[head1])
|
4217 |
|
|
&& (!iqentry_v[head2])
|
4218 |
|
|
&& (!iqentry_v[head3])
|
4219 |
|
|
&& (!iqentry_v[head4]))
|
4220 |
|
|
)
|
4221 |
|
|
&& (!(iqentry_v[head6] && (iqentry_sync[head6] || iqentry_fsync[head6])) ||
|
4222 |
|
|
((!iqentry_v[head0])
|
4223 |
|
|
&& (!iqentry_v[head1])
|
4224 |
|
|
&& (!iqentry_v[head2])
|
4225 |
|
|
&& (!iqentry_v[head3])
|
4226 |
|
|
&& (!iqentry_v[head4])
|
4227 |
|
|
&& (!iqentry_v[head5]))
|
4228 |
|
|
)
|
4229 |
|
|
)
|
4230 |
|
|
begin
|
4231 |
49 |
robfinch |
iqentry_fpu1_issue[head7] = `TRUE;
|
4232 |
48 |
robfinch |
end
|
4233 |
|
|
`endif
|
4234 |
|
|
end
|
4235 |
|
|
end
|
4236 |
|
|
|
4237 |
49 |
robfinch |
always @*
|
4238 |
|
|
begin
|
4239 |
|
|
iqentry_fpu2_issue = {QENTRIES{1'b0}};
|
4240 |
|
|
// fpu2issue(fpu2_idle,2'b00);
|
4241 |
|
|
if (fpu2_idle && `NUM_FPU > 1) begin
|
4242 |
|
|
if (could_issue[head0] && iqentry_fpu[head0] && !iqentry_fpu1_issue[head0]) begin
|
4243 |
|
|
iqentry_fpu2_issue[head0] = `TRUE;
|
4244 |
|
|
end
|
4245 |
|
|
else if (could_issue[head1] && iqentry_fpu[head1] && !iqentry_fpu1_issue[head1])
|
4246 |
|
|
begin
|
4247 |
|
|
iqentry_fpu2_issue[head1] = `TRUE;
|
4248 |
|
|
end
|
4249 |
|
|
else if (could_issue[head2] && iqentry_fpu[head2] && !iqentry_fpu1_issue[head2]
|
4250 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4251 |
|
|
) begin
|
4252 |
|
|
iqentry_fpu2_issue[head2] = `TRUE;
|
4253 |
|
|
end
|
4254 |
|
|
else if (could_issue[head3] && iqentry_fpu[head3] && !iqentry_fpu1_issue[head3]
|
4255 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4256 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4257 |
|
|
((!iqentry_v[head0])
|
4258 |
|
|
&& (!iqentry_v[head1]))
|
4259 |
|
|
)
|
4260 |
|
|
) begin
|
4261 |
|
|
iqentry_fpu2_issue[head3] = `TRUE;
|
4262 |
|
|
end
|
4263 |
|
|
else if (could_issue[head4] && iqentry_fpu[head4] && !iqentry_fpu1_issue[head4]
|
4264 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4265 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4266 |
|
|
((!iqentry_v[head0])
|
4267 |
|
|
&& (!iqentry_v[head1]))
|
4268 |
|
|
)
|
4269 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4270 |
|
|
((!iqentry_v[head0])
|
4271 |
|
|
&& (!iqentry_v[head1])
|
4272 |
|
|
&& (!iqentry_v[head2]))
|
4273 |
|
|
)
|
4274 |
|
|
) begin
|
4275 |
|
|
iqentry_fpu2_issue[head4] = `TRUE;
|
4276 |
|
|
end
|
4277 |
|
|
else if (could_issue[head5] && iqentry_fpu[head5] && !iqentry_fpu1_issue[head5]
|
4278 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4279 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4280 |
|
|
((!iqentry_v[head0])
|
4281 |
|
|
&& (!iqentry_v[head1]))
|
4282 |
|
|
)
|
4283 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4284 |
|
|
((!iqentry_v[head0])
|
4285 |
|
|
&& (!iqentry_v[head1])
|
4286 |
|
|
&& (!iqentry_v[head2]))
|
4287 |
|
|
)
|
4288 |
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
4289 |
|
|
((!iqentry_v[head0])
|
4290 |
|
|
&& (!iqentry_v[head1])
|
4291 |
|
|
&& (!iqentry_v[head2])
|
4292 |
|
|
&& (!iqentry_v[head3]))
|
4293 |
|
|
)
|
4294 |
|
|
) begin
|
4295 |
|
|
iqentry_fpu2_issue[head5] = `TRUE;
|
4296 |
|
|
end
|
4297 |
|
|
`ifdef FULL_ISSUE_LOGIC
|
4298 |
|
|
else if (could_issue[head6] && iqentry_fpu[head6] && !iqentry_fpu1_issue[head6]
|
4299 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4300 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4301 |
|
|
((!iqentry_v[head0])
|
4302 |
|
|
&& (!iqentry_v[head1]))
|
4303 |
|
|
)
|
4304 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4305 |
|
|
((!iqentry_v[head0])
|
4306 |
|
|
&& (!iqentry_v[head1])
|
4307 |
|
|
&& (!iqentry_v[head2]))
|
4308 |
|
|
)
|
4309 |
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
4310 |
|
|
((!iqentry_v[head0])
|
4311 |
|
|
&& (!iqentry_v[head1])
|
4312 |
|
|
&& (!iqentry_v[head2])
|
4313 |
|
|
&& (!iqentry_v[head3]))
|
4314 |
|
|
)
|
4315 |
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
4316 |
|
|
((!iqentry_v[head0])
|
4317 |
|
|
&& (!iqentry_v[head1])
|
4318 |
|
|
&& (!iqentry_v[head2])
|
4319 |
|
|
&& (!iqentry_v[head3])
|
4320 |
|
|
&& (!iqentry_v[head4]))
|
4321 |
|
|
)
|
4322 |
|
|
) begin
|
4323 |
|
|
iqentry_fpu2_issue[head6] = `TRUE;
|
4324 |
|
|
end
|
4325 |
|
|
else if (could_issue[head7] && iqentry_fpu[head7] && !iqentry_fpu1_issue[head7]
|
4326 |
|
|
&& (!(iqentry_v[head1] && (iqentry_sync[head1] || iqentry_fsync[head1])) || !iqentry_v[head0])
|
4327 |
|
|
&& (!(iqentry_v[head2] && (iqentry_sync[head2] || iqentry_fsync[head2])) ||
|
4328 |
|
|
((!iqentry_v[head0])
|
4329 |
|
|
&& (!iqentry_v[head1]))
|
4330 |
|
|
)
|
4331 |
|
|
&& (!(iqentry_v[head3] && (iqentry_sync[head3] || iqentry_fsync[head3])) ||
|
4332 |
|
|
((!iqentry_v[head0])
|
4333 |
|
|
&& (!iqentry_v[head1])
|
4334 |
|
|
&& (!iqentry_v[head2]))
|
4335 |
|
|
)
|
4336 |
|
|
&& (!(iqentry_v[head4] && (iqentry_sync[head4] || iqentry_fsync[head4])) ||
|
4337 |
|
|
((!iqentry_v[head0])
|
4338 |
|
|
&& (!iqentry_v[head1])
|
4339 |
|
|
&& (!iqentry_v[head2])
|
4340 |
|
|
&& (!iqentry_v[head3]))
|
4341 |
|
|
)
|
4342 |
|
|
&& (!(iqentry_v[head5] && (iqentry_sync[head5] || iqentry_fsync[head5])) ||
|
4343 |
|
|
((!iqentry_v[head0])
|
4344 |
|
|
&& (!iqentry_v[head1])
|
4345 |
|
|
&& (!iqentry_v[head2])
|
4346 |
|
|
&& (!iqentry_v[head3])
|
4347 |
|
|
&& (!iqentry_v[head4]))
|
4348 |
|
|
)
|
4349 |
|
|
&& (!(iqentry_v[head6] && (iqentry_sync[head6] || iqentry_fsync[head6])) ||
|
4350 |
|
|
((!iqentry_v[head0])
|
4351 |
|
|
&& (!iqentry_v[head1])
|
4352 |
|
|
&& (!iqentry_v[head2])
|
4353 |
|
|
&& (!iqentry_v[head3])
|
4354 |
|
|
&& (!iqentry_v[head4])
|
4355 |
|
|
&& (!iqentry_v[head5]))
|
4356 |
|
|
)
|
4357 |
|
|
)
|
4358 |
|
|
begin
|
4359 |
|
|
iqentry_fpu2_issue[head7] = `TRUE;
|
4360 |
|
|
end
|
4361 |
|
|
`endif
|
4362 |
|
|
end
|
4363 |
|
|
end
|
4364 |
48 |
robfinch |
|
4365 |
|
|
wire [QENTRIES-1:0] nextqd;
|
4366 |
|
|
// Next queue id
|
4367 |
|
|
|
4368 |
|
|
reg [`QBITS] nid0;
|
4369 |
|
|
always @*
|
4370 |
|
|
if (iqentry_thrd[1]==iqentry_thrd[0])
|
4371 |
|
|
nid0 = 3'd1;
|
4372 |
|
|
else if (iqentry_thrd[2]==iqentry_thrd[0])
|
4373 |
|
|
nid0 = 3'd2;
|
4374 |
|
|
else if (iqentry_thrd[3]==iqentry_thrd[0])
|
4375 |
|
|
nid0 = 3'd3;
|
4376 |
|
|
else if (iqentry_thrd[4]==iqentry_thrd[0])
|
4377 |
|
|
nid0 = 3'd4;
|
4378 |
|
|
else if (iqentry_thrd[5]==iqentry_thrd[0])
|
4379 |
|
|
nid0 = 3'd5;
|
4380 |
|
|
else if (iqentry_thrd[6]==iqentry_thrd[0])
|
4381 |
|
|
nid0 = 3'd6;
|
4382 |
|
|
else if (iqentry_thrd[7]==iqentry_thrd[0])
|
4383 |
|
|
nid0 = 3'd7;
|
4384 |
|
|
else
|
4385 |
|
|
nid0 = 3'd0;
|
4386 |
|
|
|
4387 |
|
|
reg [`QBITS] nid1;
|
4388 |
|
|
always @*
|
4389 |
|
|
if (iqentry_thrd[2]==iqentry_thrd[1])
|
4390 |
|
|
nid1 = 3'd2;
|
4391 |
|
|
else if (iqentry_thrd[3]==iqentry_thrd[1])
|
4392 |
|
|
nid1 = 3'd3;
|
4393 |
|
|
else if (iqentry_thrd[4]==iqentry_thrd[1])
|
4394 |
|
|
nid1 = 3'd4;
|
4395 |
|
|
else if (iqentry_thrd[5]==iqentry_thrd[1])
|
4396 |
|
|
nid1 = 3'd5;
|
4397 |
|
|
else if (iqentry_thrd[6]==iqentry_thrd[1])
|
4398 |
|
|
nid1 = 3'd6;
|
4399 |
|
|
else if (iqentry_thrd[7]==iqentry_thrd[1])
|
4400 |
|
|
nid1 = 3'd7;
|
4401 |
|
|
else if (iqentry_thrd[0]==iqentry_thrd[1])
|
4402 |
|
|
nid1 = 3'd0;
|
4403 |
|
|
else
|
4404 |
|
|
nid1 = 3'd1;
|
4405 |
|
|
|
4406 |
|
|
reg [`QBITS] nid2;
|
4407 |
|
|
always @*
|
4408 |
|
|
if (iqentry_thrd[3]==iqentry_thrd[2])
|
4409 |
|
|
nid2 = 3'd3;
|
4410 |
|
|
else if (iqentry_thrd[4]==iqentry_thrd[2])
|
4411 |
|
|
nid2 = 3'd4;
|
4412 |
|
|
else if (iqentry_thrd[5]==iqentry_thrd[2])
|
4413 |
|
|
nid2 = 3'd5;
|
4414 |
|
|
else if (iqentry_thrd[6]==iqentry_thrd[2])
|
4415 |
|
|
nid2 = 3'd6;
|
4416 |
|
|
else if (iqentry_thrd[7]==iqentry_thrd[2])
|
4417 |
|
|
nid2 = 3'd7;
|
4418 |
|
|
else if (iqentry_thrd[0]==iqentry_thrd[2])
|
4419 |
|
|
nid2 = 3'd0;
|
4420 |
|
|
else if (iqentry_thrd[1]==iqentry_thrd[2])
|
4421 |
|
|
nid2 = 3'd1;
|
4422 |
|
|
else
|
4423 |
|
|
nid2 = 3'd2;
|
4424 |
|
|
|
4425 |
|
|
reg [`QBITS] nid3;
|
4426 |
|
|
always @*
|
4427 |
|
|
if (iqentry_thrd[4]==iqentry_thrd[3])
|
4428 |
|
|
nid3 = 3'd4;
|
4429 |
|
|
else if (iqentry_thrd[5]==iqentry_thrd[3])
|
4430 |
|
|
nid3 = 3'd5;
|
4431 |
|
|
else if (iqentry_thrd[6]==iqentry_thrd[3])
|
4432 |
|
|
nid3 = 3'd6;
|
4433 |
|
|
else if (iqentry_thrd[7]==iqentry_thrd[3])
|
4434 |
|
|
nid3 = 3'd7;
|
4435 |
|
|
else if (iqentry_thrd[0]==iqentry_thrd[3])
|
4436 |
|
|
nid3 = 3'd0;
|
4437 |
|
|
else if (iqentry_thrd[1]==iqentry_thrd[3])
|
4438 |
|
|
nid3 = 3'd1;
|
4439 |
|
|
else if (iqentry_thrd[2]==iqentry_thrd[3])
|
4440 |
|
|
nid3 = 3'd2;
|
4441 |
|
|
else
|
4442 |
|
|
nid3 = 3'd3;
|
4443 |
|
|
|
4444 |
|
|
reg [`QBITS] nid4;
|
4445 |
|
|
always @*
|
4446 |
|
|
if (iqentry_thrd[5]==iqentry_thrd[4])
|
4447 |
|
|
nid4 = 3'd5;
|
4448 |
|
|
else if (iqentry_thrd[6]==iqentry_thrd[4])
|
4449 |
|
|
nid4 = 3'd6;
|
4450 |
|
|
else if (iqentry_thrd[7]==iqentry_thrd[4])
|
4451 |
|
|
nid4 = 3'd7;
|
4452 |
|
|
else if (iqentry_thrd[0]==iqentry_thrd[4])
|
4453 |
|
|
nid4 = 3'd0;
|
4454 |
|
|
else if (iqentry_thrd[1]==iqentry_thrd[4])
|
4455 |
|
|
nid4 = 3'd1;
|
4456 |
|
|
else if (iqentry_thrd[2]==iqentry_thrd[4])
|
4457 |
|
|
nid4 = 3'd2;
|
4458 |
|
|
else if (iqentry_thrd[3]==iqentry_thrd[4])
|
4459 |
|
|
nid4 = 3'd3;
|
4460 |
|
|
else
|
4461 |
|
|
nid4 = 3'd4;
|
4462 |
|
|
|
4463 |
|
|
reg [`QBITS] nid5;
|
4464 |
|
|
always @*
|
4465 |
|
|
if (iqentry_thrd[6]==iqentry_thrd[5])
|
4466 |
|
|
nid5 = 3'd6;
|
4467 |
|
|
else if (iqentry_thrd[7]==iqentry_thrd[5])
|
4468 |
|
|
nid5 = 3'd7;
|
4469 |
|
|
else if (iqentry_thrd[0]==iqentry_thrd[5])
|
4470 |
|
|
nid5 = 3'd0;
|
4471 |
|
|
else if (iqentry_thrd[1]==iqentry_thrd[5])
|
4472 |
|
|
nid5 = 3'd1;
|
4473 |
|
|
else if (iqentry_thrd[2]==iqentry_thrd[5])
|
4474 |
|
|
nid5 = 3'd2;
|
4475 |
|
|
else if (iqentry_thrd[3]==iqentry_thrd[5])
|
4476 |
|
|
nid5 = 3'd3;
|
4477 |
|
|
else if (iqentry_thrd[4]==iqentry_thrd[5])
|
4478 |
|
|
nid5 = 3'd4;
|
4479 |
|
|
else
|
4480 |
|
|
nid5 = 3'd5;
|
4481 |
|
|
|
4482 |
|
|
reg [`QBITS] nid6;
|
4483 |
|
|
always @*
|
4484 |
|
|
if (iqentry_thrd[7]==iqentry_thrd[6])
|
4485 |
|
|
nid6 = 3'd7;
|
4486 |
|
|
else if (iqentry_thrd[0]==iqentry_thrd[6])
|
4487 |
|
|
nid6 = 3'd0;
|
4488 |
|
|
else if (iqentry_thrd[1]==iqentry_thrd[6])
|
4489 |
|
|
nid6 = 3'd1;
|
4490 |
|
|
else if (iqentry_thrd[2]==iqentry_thrd[6])
|
4491 |
|
|
nid6 = 3'd2;
|
4492 |
|
|
else if (iqentry_thrd[3]==iqentry_thrd[6])
|
4493 |
|
|
nid6 = 3'd3;
|
4494 |
|
|
else if (iqentry_thrd[4]==iqentry_thrd[6])
|
4495 |
|
|
nid6 = 3'd4;
|
4496 |
|
|
else if (iqentry_thrd[5]==iqentry_thrd[6])
|
4497 |
|
|
nid6 = 3'd5;
|
4498 |
|
|
else
|
4499 |
|
|
nid6 = 3'd6;
|
4500 |
|
|
|
4501 |
|
|
reg [`QBITS] nid7;
|
4502 |
|
|
always @*
|
4503 |
|
|
if (iqentry_thrd[0]==iqentry_thrd[7])
|
4504 |
|
|
nid7 = 3'd0;
|
4505 |
|
|
else if (iqentry_thrd[1]==iqentry_thrd[7])
|
4506 |
|
|
nid7 = 3'd1;
|
4507 |
|
|
else if (iqentry_thrd[2]==iqentry_thrd[7])
|
4508 |
|
|
nid7 = 3'd2;
|
4509 |
|
|
else if (iqentry_thrd[3]==iqentry_thrd[7])
|
4510 |
|
|
nid7 = 3'd3;
|
4511 |
|
|
else if (iqentry_thrd[4]==iqentry_thrd[7])
|
4512 |
|
|
nid7 = 3'd4;
|
4513 |
|
|
else if (iqentry_thrd[5]==iqentry_thrd[7])
|
4514 |
|
|
nid7 = 3'd5;
|
4515 |
|
|
else if (iqentry_thrd[6]==iqentry_thrd[7])
|
4516 |
|
|
nid7 = 3'd6;
|
4517 |
|
|
else
|
4518 |
|
|
nid7 = 3'd7;
|
4519 |
|
|
|
4520 |
|
|
// Search the queue for the next entry on the same thread.
|
4521 |
|
|
reg [`QBITS] nid;
|
4522 |
|
|
always @*
|
4523 |
|
|
if (iqentry_thrd[idp1(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
4524 |
|
|
nid = idp1(fcu_id);
|
4525 |
|
|
else if (iqentry_thrd[idp2(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
4526 |
|
|
nid = idp2(fcu_id);
|
4527 |
|
|
else if (iqentry_thrd[idp3(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
4528 |
|
|
nid = idp3(fcu_id);
|
4529 |
|
|
else if (iqentry_thrd[idp4(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
4530 |
|
|
nid = idp4(fcu_id);
|
4531 |
|
|
else if (iqentry_thrd[idp5(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
4532 |
|
|
nid = idp5(fcu_id);
|
4533 |
|
|
else if (iqentry_thrd[idp6(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
4534 |
|
|
nid = idp6(fcu_id);
|
4535 |
|
|
else if (iqentry_thrd[idp7(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
|
4536 |
|
|
nid = idp7(fcu_id);
|
4537 |
|
|
else
|
4538 |
|
|
nid = fcu_id;
|
4539 |
|
|
|
4540 |
|
|
|
4541 |
|
|
assign nextqd[0] = iqentry_sn[nid0] > iqentry_sn[0] || iqentry_v[0];
|
4542 |
|
|
assign nextqd[1] = iqentry_sn[nid1] > iqentry_sn[1] || iqentry_v[1];
|
4543 |
|
|
assign nextqd[2] = iqentry_sn[nid2] > iqentry_sn[2] || iqentry_v[2];
|
4544 |
|
|
assign nextqd[3] = iqentry_sn[nid3] > iqentry_sn[3] || iqentry_v[3];
|
4545 |
|
|
assign nextqd[4] = iqentry_sn[nid4] > iqentry_sn[4] || iqentry_v[4];
|
4546 |
|
|
assign nextqd[5] = iqentry_sn[nid5] > iqentry_sn[5] || iqentry_v[5];
|
4547 |
|
|
assign nextqd[6] = iqentry_sn[nid6] > iqentry_sn[6] || iqentry_v[6];
|
4548 |
|
|
assign nextqd[7] = iqentry_sn[nid7] > iqentry_sn[7] || iqentry_v[7];
|
4549 |
|
|
|
4550 |
|
|
//assign nextqd = 8'hFF;
|
4551 |
|
|
|
4552 |
|
|
// Don't issue to the fcu until the following instruction is enqueued.
|
4553 |
|
|
// However, if the queue is full then issue anyway. A branch miss will likely occur.
|
4554 |
|
|
always @*//(could_issue or head0 or head1 or head2 or head3 or head4 or head5 or head6 or head7)
|
4555 |
|
|
begin
|
4556 |
49 |
robfinch |
iqentry_fcu_issue = {QENTRIES{1'b0}};
|
4557 |
48 |
robfinch |
if (fcu_done) begin
|
4558 |
|
|
if (could_issue[head0] && iqentry_fc[head0] && nextqd[head0]) begin
|
4559 |
|
|
iqentry_fcu_issue[head0] = `TRUE;
|
4560 |
|
|
end
|
4561 |
|
|
else if (could_issue[head1] && iqentry_fc[head1] && nextqd[head1])
|
4562 |
|
|
begin
|
4563 |
|
|
iqentry_fcu_issue[head1] = `TRUE;
|
4564 |
|
|
end
|
4565 |
|
|
else if (could_issue[head2] && iqentry_fc[head2] && nextqd[head2]
|
4566 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4567 |
|
|
) begin
|
4568 |
|
|
iqentry_fcu_issue[head2] = `TRUE;
|
4569 |
|
|
end
|
4570 |
|
|
else if (could_issue[head3] && iqentry_fc[head3] && nextqd[head3]
|
4571 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4572 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4573 |
|
|
((!iqentry_v[head0])
|
4574 |
|
|
&& (!iqentry_v[head1]))
|
4575 |
|
|
)
|
4576 |
|
|
) begin
|
4577 |
|
|
iqentry_fcu_issue[head3] = `TRUE;
|
4578 |
|
|
end
|
4579 |
|
|
else if (could_issue[head4] && iqentry_fc[head4] && nextqd[head4]
|
4580 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4581 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4582 |
|
|
((!iqentry_v[head0])
|
4583 |
|
|
&& (!iqentry_v[head1]))
|
4584 |
|
|
)
|
4585 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4586 |
|
|
((!iqentry_v[head0])
|
4587 |
|
|
&& (!iqentry_v[head1])
|
4588 |
|
|
&& (!iqentry_v[head2]))
|
4589 |
|
|
)
|
4590 |
|
|
) begin
|
4591 |
|
|
iqentry_fcu_issue[head4] = `TRUE;
|
4592 |
|
|
end
|
4593 |
|
|
else if (could_issue[head5] && iqentry_fc[head5] && nextqd[head5]
|
4594 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4595 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4596 |
|
|
((!iqentry_v[head0])
|
4597 |
|
|
&& (!iqentry_v[head1]))
|
4598 |
|
|
)
|
4599 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4600 |
|
|
((!iqentry_v[head0])
|
4601 |
|
|
&& (!iqentry_v[head1])
|
4602 |
|
|
&& (!iqentry_v[head2]))
|
4603 |
|
|
)
|
4604 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
4605 |
|
|
((!iqentry_v[head0])
|
4606 |
|
|
&& (!iqentry_v[head1])
|
4607 |
|
|
&& (!iqentry_v[head2])
|
4608 |
|
|
&& (!iqentry_v[head3]))
|
4609 |
|
|
)
|
4610 |
|
|
) begin
|
4611 |
|
|
iqentry_fcu_issue[head5] = `TRUE;
|
4612 |
|
|
end
|
4613 |
|
|
|
4614 |
|
|
`ifdef FULL_ISSUE_LOGIC
|
4615 |
|
|
else if (could_issue[head6] && iqentry_fc[head6] && nextqd[head6]
|
4616 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4617 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4618 |
|
|
((!iqentry_v[head0])
|
4619 |
|
|
&& (!iqentry_v[head1]))
|
4620 |
|
|
)
|
4621 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4622 |
|
|
((!iqentry_v[head0])
|
4623 |
|
|
&& (!iqentry_v[head1])
|
4624 |
|
|
&& (!iqentry_v[head2]))
|
4625 |
|
|
)
|
4626 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
4627 |
|
|
((!iqentry_v[head0])
|
4628 |
|
|
&& (!iqentry_v[head1])
|
4629 |
|
|
&& (!iqentry_v[head2])
|
4630 |
|
|
&& (!iqentry_v[head3]))
|
4631 |
|
|
)
|
4632 |
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
4633 |
|
|
((!iqentry_v[head0])
|
4634 |
|
|
&& (!iqentry_v[head1])
|
4635 |
|
|
&& (!iqentry_v[head2])
|
4636 |
|
|
&& (!iqentry_v[head3])
|
4637 |
|
|
&& (!iqentry_v[head4]))
|
4638 |
|
|
)
|
4639 |
|
|
) begin
|
4640 |
|
|
iqentry_fcu_issue[head6] = `TRUE;
|
4641 |
|
|
end
|
4642 |
|
|
|
4643 |
|
|
else if (could_issue[head7] && iqentry_fc[head7]
|
4644 |
|
|
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0])
|
4645 |
|
|
&& (!(iqentry_v[head2] && iqentry_sync[head2]) ||
|
4646 |
|
|
((!iqentry_v[head0])
|
4647 |
|
|
&& (!iqentry_v[head1]))
|
4648 |
|
|
)
|
4649 |
|
|
&& (!(iqentry_v[head3] && iqentry_sync[head3]) ||
|
4650 |
|
|
((!iqentry_v[head0])
|
4651 |
|
|
&& (!iqentry_v[head1])
|
4652 |
|
|
&& (!iqentry_v[head2]))
|
4653 |
|
|
)
|
4654 |
|
|
&& (!(iqentry_v[head4] && iqentry_sync[head4]) ||
|
4655 |
|
|
((!iqentry_v[head0])
|
4656 |
|
|
&& (!iqentry_v[head1])
|
4657 |
|
|
&& (!iqentry_v[head2])
|
4658 |
|
|
&& (!iqentry_v[head3]))
|
4659 |
|
|
)
|
4660 |
|
|
&& (!(iqentry_v[head5] && iqentry_sync[head5]) ||
|
4661 |
|
|
((!iqentry_v[head0])
|
4662 |
|
|
&& (!iqentry_v[head1])
|
4663 |
|
|
&& (!iqentry_v[head2])
|
4664 |
|
|
&& (!iqentry_v[head3])
|
4665 |
|
|
&& (!iqentry_v[head4]))
|
4666 |
|
|
)
|
4667 |
|
|
&& (!(iqentry_v[head6] && iqentry_sync[head6]) ||
|
4668 |
|
|
((!iqentry_v[head0])
|
4669 |
|
|
&& (!iqentry_v[head1])
|
4670 |
|
|
&& (!iqentry_v[head2])
|
4671 |
|
|
&& (!iqentry_v[head3])
|
4672 |
|
|
&& (!iqentry_v[head4])
|
4673 |
|
|
&& (!iqentry_v[head5]))
|
4674 |
|
|
)
|
4675 |
|
|
) begin
|
4676 |
|
|
iqentry_fcu_issue[head7] = `TRUE;
|
4677 |
|
|
end
|
4678 |
|
|
`endif
|
4679 |
|
|
end
|
4680 |
|
|
end
|
4681 |
|
|
|
4682 |
|
|
//
|
4683 |
|
|
// determine if the instructions ready to issue can, in fact, issue.
|
4684 |
|
|
// "ready" means that the instruction has valid operands but has not gone yet
|
4685 |
|
|
reg [1:0] issue_count, missue_count;
|
4686 |
|
|
always @*
|
4687 |
|
|
begin
|
4688 |
|
|
issue_count = 0;
|
4689 |
|
|
memissue[ head0 ] = iqentry_memready[ head0 ]; // first in line ... go as soon as ready
|
4690 |
|
|
if (memissue[head0])
|
4691 |
|
|
issue_count = issue_count + 1;
|
4692 |
|
|
|
4693 |
|
|
memissue[ head1 ] = ~iqentry_stomp[head1] && iqentry_memready[ head1 ] // addr and data are valid
|
4694 |
49 |
robfinch |
&& issue_count < `NUM_MEM
|
4695 |
48 |
robfinch |
// ... and no preceding instruction is ready to go
|
4696 |
|
|
//&& ~iqentry_memready[head0]
|
4697 |
|
|
// ... and there is no address-overlap with any preceding instruction
|
4698 |
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
4699 |
49 |
robfinch |
|| (iqentry_a1_v[head0] && iqentry_a1[head1][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
4700 |
48 |
robfinch |
// ... if a release, any prior memory ops must be done before this one
|
4701 |
|
|
&& (iqentry_rl[head1] ? iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0] : 1'b1)
|
4702 |
|
|
// ... if a preivous op has the aquire bit set
|
4703 |
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
4704 |
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
4705 |
|
|
&& (iqentry_load[head1] ||
|
4706 |
|
|
!(iqentry_fc[head0]||iqentry_canex[head0]));
|
4707 |
|
|
if (memissue[head1])
|
4708 |
|
|
issue_count = issue_count + 1;
|
4709 |
|
|
|
4710 |
|
|
memissue[ head2 ] = ~iqentry_stomp[head2] && iqentry_memready[ head2 ] // addr and data are valid
|
4711 |
|
|
// ... and no preceding instruction is ready to go
|
4712 |
49 |
robfinch |
&& issue_count < `NUM_MEM
|
4713 |
48 |
robfinch |
//&& ~iqentry_memready[head0]
|
4714 |
|
|
//&& ~iqentry_memready[head1]
|
4715 |
|
|
// ... and there is no address-overlap with any preceding instruction
|
4716 |
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
4717 |
49 |
robfinch |
|| (iqentry_a1_v[head0] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
4718 |
48 |
robfinch |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
4719 |
49 |
robfinch |
|| (iqentry_a1_v[head1] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
4720 |
48 |
robfinch |
// ... if a release, any prior memory ops must be done before this one
|
4721 |
|
|
&& (iqentry_rl[head2] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
4722 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
4723 |
|
|
: 1'b1)
|
4724 |
|
|
// ... if a preivous op has the aquire bit set
|
4725 |
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
4726 |
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
4727 |
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
4728 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
4729 |
|
|
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
4730 |
48 |
robfinch |
// ... and, if it is a SW, there is no chance of it being undone
|
4731 |
|
|
&& (iqentry_load[head2] ||
|
4732 |
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
4733 |
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1]));
|
4734 |
|
|
if (memissue[head2])
|
4735 |
|
|
issue_count = issue_count + 1;
|
4736 |
|
|
|
4737 |
|
|
memissue[ head3 ] = ~iqentry_stomp[head3] && iqentry_memready[ head3 ] // addr and data are valid
|
4738 |
|
|
// ... and no preceding instruction is ready to go
|
4739 |
49 |
robfinch |
&& issue_count < `NUM_MEM
|
4740 |
48 |
robfinch |
//&& ~iqentry_memready[head0]
|
4741 |
|
|
//&& ~iqentry_memready[head1]
|
4742 |
|
|
//&& ~iqentry_memready[head2]
|
4743 |
|
|
// ... and there is no address-overlap with any preceding instruction
|
4744 |
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
4745 |
49 |
robfinch |
|| (iqentry_a1_v[head0] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
4746 |
48 |
robfinch |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
4747 |
49 |
robfinch |
|| (iqentry_a1_v[head1] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
4748 |
48 |
robfinch |
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
4749 |
49 |
robfinch |
|| (iqentry_a1_v[head2] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
4750 |
48 |
robfinch |
// ... if a release, any prior memory ops must be done before this one
|
4751 |
|
|
&& (iqentry_rl[head3] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
4752 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
4753 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
4754 |
|
|
: 1'b1)
|
4755 |
|
|
// ... if a preivous op has the aquire bit set
|
4756 |
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
4757 |
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
4758 |
|
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
4759 |
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
4760 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
4761 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
4762 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4763 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
4764 |
|
|
)
|
4765 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
4766 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
4767 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4768 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
4769 |
|
|
)
|
4770 |
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
4771 |
|
|
&& (iqentry_load[head3] ||
|
4772 |
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
4773 |
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1])
|
4774 |
|
|
&& !(iqentry_fc[head2]||iqentry_canex[head2]));
|
4775 |
|
|
if (memissue[head3])
|
4776 |
|
|
issue_count = issue_count + 1;
|
4777 |
|
|
|
4778 |
|
|
memissue[ head4 ] = ~iqentry_stomp[head4] && iqentry_memready[ head4 ] // addr and data are valid
|
4779 |
|
|
// ... and no preceding instruction is ready to go
|
4780 |
49 |
robfinch |
&& issue_count < `NUM_MEM
|
4781 |
48 |
robfinch |
//&& ~iqentry_memready[head0]
|
4782 |
|
|
//&& ~iqentry_memready[head1]
|
4783 |
|
|
//&& ~iqentry_memready[head2]
|
4784 |
|
|
//&& ~iqentry_memready[head3]
|
4785 |
|
|
// ... and there is no address-overlap with any preceding instruction
|
4786 |
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
4787 |
49 |
robfinch |
|| (iqentry_a1_v[head0] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
4788 |
48 |
robfinch |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
4789 |
49 |
robfinch |
|| (iqentry_a1_v[head1] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
4790 |
48 |
robfinch |
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
4791 |
49 |
robfinch |
|| (iqentry_a1_v[head2] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
4792 |
48 |
robfinch |
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
4793 |
49 |
robfinch |
|| (iqentry_a1_v[head3] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
4794 |
48 |
robfinch |
// ... if a release, any prior memory ops must be done before this one
|
4795 |
|
|
&& (iqentry_rl[head4] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
4796 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
4797 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
4798 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
4799 |
|
|
: 1'b1)
|
4800 |
|
|
// ... if a preivous op has the aquire bit set
|
4801 |
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
4802 |
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
4803 |
|
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
4804 |
|
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
4805 |
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
4806 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
4807 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
4808 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4809 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
4810 |
|
|
)
|
4811 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
4812 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4813 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
4814 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
4815 |
|
|
)
|
4816 |
|
|
&& (!(iqentry_v[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
4817 |
49 |
robfinch |
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
4818 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4819 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
4820 |
|
|
)
|
4821 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
4822 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4823 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
4824 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
4825 |
|
|
)
|
4826 |
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
4827 |
|
|
&& (iqentry_load[head4] ||
|
4828 |
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
4829 |
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1])
|
4830 |
|
|
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
4831 |
|
|
&& !(iqentry_fc[head3]||iqentry_canex[head3]));
|
4832 |
|
|
if (memissue[head4])
|
4833 |
|
|
issue_count = issue_count + 1;
|
4834 |
|
|
|
4835 |
|
|
memissue[ head5 ] = ~iqentry_stomp[head5] && iqentry_memready[ head5 ] // addr and data are valid
|
4836 |
|
|
// ... and no preceding instruction is ready to go
|
4837 |
49 |
robfinch |
&& issue_count < `NUM_MEM
|
4838 |
48 |
robfinch |
//&& ~iqentry_memready[head0]
|
4839 |
|
|
//&& ~iqentry_memready[head1]
|
4840 |
|
|
//&& ~iqentry_memready[head2]
|
4841 |
|
|
//&& ~iqentry_memready[head3]
|
4842 |
|
|
//&& ~iqentry_memready[head4]
|
4843 |
|
|
// ... and there is no address-overlap with any preceding instruction
|
4844 |
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
4845 |
49 |
robfinch |
|| (iqentry_a1_v[head0] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
4846 |
48 |
robfinch |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
4847 |
49 |
robfinch |
|| (iqentry_a1_v[head1] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
4848 |
48 |
robfinch |
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
4849 |
49 |
robfinch |
|| (iqentry_a1_v[head2] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
4850 |
48 |
robfinch |
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
4851 |
49 |
robfinch |
|| (iqentry_a1_v[head3] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
4852 |
48 |
robfinch |
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
4853 |
49 |
robfinch |
|| (iqentry_a1_v[head4] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
4854 |
48 |
robfinch |
// ... if a release, any prior memory ops must be done before this one
|
4855 |
|
|
&& (iqentry_rl[head5] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
4856 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
4857 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
4858 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
4859 |
|
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
4860 |
|
|
: 1'b1)
|
4861 |
|
|
// ... if a preivous op has the aquire bit set
|
4862 |
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
4863 |
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
4864 |
|
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
4865 |
|
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
4866 |
|
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
4867 |
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
4868 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
4869 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
4870 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4871 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
4872 |
|
|
)
|
4873 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
4874 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4875 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
4876 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
4877 |
|
|
)
|
4878 |
49 |
robfinch |
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
4879 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4880 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
4881 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
4882 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
4883 |
|
|
)
|
4884 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
4885 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
4886 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4887 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
4888 |
|
|
)
|
4889 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
4890 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4891 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
4892 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
4893 |
|
|
)
|
4894 |
49 |
robfinch |
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
4895 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4896 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
4897 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
4898 |
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
4899 |
|
|
)
|
4900 |
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
4901 |
|
|
&& (iqentry_load[head5] ||
|
4902 |
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
4903 |
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1])
|
4904 |
|
|
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
4905 |
|
|
&& !(iqentry_fc[head3]||iqentry_canex[head3])
|
4906 |
|
|
&& !(iqentry_fc[head4]||iqentry_canex[head4]));
|
4907 |
|
|
if (memissue[head5])
|
4908 |
|
|
issue_count = issue_count + 1;
|
4909 |
|
|
|
4910 |
|
|
`ifdef FULL_ISSUE_LOGIC
|
4911 |
|
|
memissue[ head6 ] = ~iqentry_stomp[head6] && iqentry_memready[ head6 ] // addr and data are valid
|
4912 |
|
|
// ... and no preceding instruction is ready to go
|
4913 |
49 |
robfinch |
&& issue_count < `NUM_MEM
|
4914 |
48 |
robfinch |
//&& ~iqentry_memready[head0]
|
4915 |
|
|
//&& ~iqentry_memready[head1]
|
4916 |
|
|
//&& ~iqentry_memready[head2]
|
4917 |
|
|
//&& ~iqentry_memready[head3]
|
4918 |
|
|
//&& ~iqentry_memready[head4]
|
4919 |
|
|
//&& ~iqentry_memready[head5]
|
4920 |
|
|
// ... and there is no address-overlap with any preceding instruction
|
4921 |
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
4922 |
49 |
robfinch |
|| (iqentry_a1_v[head0] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
4923 |
48 |
robfinch |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
4924 |
49 |
robfinch |
|| (iqentry_a1_v[head1] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
4925 |
48 |
robfinch |
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
4926 |
49 |
robfinch |
|| (iqentry_a1_v[head2] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
4927 |
48 |
robfinch |
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
4928 |
49 |
robfinch |
|| (iqentry_a1_v[head3] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
4929 |
48 |
robfinch |
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
4930 |
49 |
robfinch |
|| (iqentry_a1_v[head4] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
4931 |
48 |
robfinch |
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
4932 |
49 |
robfinch |
|| (iqentry_a1_v[head5] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head5][AMSB:3]))
|
4933 |
48 |
robfinch |
&& (iqentry_rl[head6] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
4934 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
4935 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
4936 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
4937 |
|
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
4938 |
|
|
&& (iqentry_done[head5] || !iqentry_v[head5] || !iqentry_mem[head5])
|
4939 |
|
|
: 1'b1)
|
4940 |
|
|
// ... if a preivous op has the aquire bit set
|
4941 |
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
4942 |
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
4943 |
|
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
4944 |
|
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
4945 |
|
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
4946 |
|
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
4947 |
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
4948 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
4949 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
4950 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4951 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
4952 |
|
|
)
|
4953 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
4954 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4955 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
4956 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
4957 |
|
|
)
|
4958 |
49 |
robfinch |
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
4959 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4960 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
4961 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
4962 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
4963 |
|
|
)
|
4964 |
49 |
robfinch |
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) ||
|
4965 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
4966 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
4967 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
4968 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
4969 |
|
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
4970 |
|
|
)
|
4971 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
4972 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
4973 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4974 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
4975 |
|
|
)
|
4976 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
4977 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4978 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
4979 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
4980 |
|
|
)
|
4981 |
49 |
robfinch |
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
4982 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4983 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
4984 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
4985 |
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
4986 |
|
|
)
|
4987 |
49 |
robfinch |
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) ||
|
4988 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
4989 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
4990 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
4991 |
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
4992 |
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
4993 |
|
|
)
|
4994 |
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
4995 |
|
|
&& (iqentry_load[head6] ||
|
4996 |
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
4997 |
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1])
|
4998 |
|
|
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
4999 |
|
|
&& !(iqentry_fc[head3]||iqentry_canex[head3])
|
5000 |
|
|
&& !(iqentry_fc[head4]||iqentry_canex[head4])
|
5001 |
|
|
&& !(iqentry_fc[head5]||iqentry_canex[head5]));
|
5002 |
|
|
if (memissue[head6])
|
5003 |
|
|
issue_count = issue_count + 1;
|
5004 |
|
|
|
5005 |
|
|
memissue[ head7 ] = ~iqentry_stomp[head7] && iqentry_memready[ head7 ] // addr and data are valid
|
5006 |
|
|
// ... and no preceding instruction is ready to go
|
5007 |
49 |
robfinch |
&& issue_count < `NUM_MEM
|
5008 |
48 |
robfinch |
//&& ~iqentry_memready[head0]
|
5009 |
|
|
//&& ~iqentry_memready[head1]
|
5010 |
|
|
//&& ~iqentry_memready[head2]
|
5011 |
|
|
//&& ~iqentry_memready[head3]
|
5012 |
|
|
//&& ~iqentry_memready[head4]
|
5013 |
|
|
//&& ~iqentry_memready[head5]
|
5014 |
|
|
//&& ~iqentry_memready[head6]
|
5015 |
|
|
// ... and there is no address-overlap with any preceding instruction
|
5016 |
|
|
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|
5017 |
49 |
robfinch |
|| (iqentry_a1_v[head0] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head0][AMSB:3]))
|
5018 |
48 |
robfinch |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|
5019 |
49 |
robfinch |
|| (iqentry_a1_v[head1] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head1][AMSB:3]))
|
5020 |
48 |
robfinch |
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|
5021 |
49 |
robfinch |
|| (iqentry_a1_v[head2] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head2][AMSB:3]))
|
5022 |
48 |
robfinch |
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|
5023 |
49 |
robfinch |
|| (iqentry_a1_v[head3] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head3][AMSB:3]))
|
5024 |
48 |
robfinch |
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|
5025 |
49 |
robfinch |
|| (iqentry_a1_v[head4] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head4][AMSB:3]))
|
5026 |
48 |
robfinch |
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|
5027 |
49 |
robfinch |
|| (iqentry_a1_v[head5] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head5][AMSB:3]))
|
5028 |
48 |
robfinch |
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6])
|
5029 |
49 |
robfinch |
|| (iqentry_a1_v[head6] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head6][AMSB:3]))
|
5030 |
48 |
robfinch |
&& (iqentry_rl[head7] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
|
5031 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
|
5032 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
|
5033 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3])
|
5034 |
|
|
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4])
|
5035 |
|
|
&& (iqentry_done[head5] || !iqentry_v[head5] || !iqentry_mem[head5])
|
5036 |
|
|
&& (iqentry_done[head6] || !iqentry_v[head6] || !iqentry_mem[head6])
|
5037 |
|
|
: 1'b1)
|
5038 |
|
|
// ... if a preivous op has the aquire bit set
|
5039 |
|
|
&& !(iqentry_aq[head0] && iqentry_v[head0])
|
5040 |
|
|
&& !(iqentry_aq[head1] && iqentry_v[head1])
|
5041 |
|
|
&& !(iqentry_aq[head2] && iqentry_v[head2])
|
5042 |
|
|
&& !(iqentry_aq[head3] && iqentry_v[head3])
|
5043 |
|
|
&& !(iqentry_aq[head4] && iqentry_v[head4])
|
5044 |
|
|
&& !(iqentry_aq[head5] && iqentry_v[head5])
|
5045 |
|
|
&& !(iqentry_aq[head6] && iqentry_v[head6])
|
5046 |
|
|
// ... and there isn't a barrier, or everything before the barrier is done or invalid
|
5047 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0]))
|
5048 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) ||
|
5049 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
5050 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1]))
|
5051 |
|
|
)
|
5052 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) ||
|
5053 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
5054 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
5055 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2]))
|
5056 |
|
|
)
|
5057 |
49 |
robfinch |
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) ||
|
5058 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
5059 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
5060 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
5061 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3]))
|
5062 |
|
|
)
|
5063 |
49 |
robfinch |
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) ||
|
5064 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
5065 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
5066 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
5067 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
5068 |
|
|
&& (iqentry_done[head4] || !iqentry_v[head4]))
|
5069 |
|
|
)
|
5070 |
49 |
robfinch |
&& (!(iqentry_iv[head6] && iqentry_memsb[head6]) ||
|
5071 |
48 |
robfinch |
((iqentry_done[head0] || !iqentry_v[head0])
|
5072 |
|
|
&& (iqentry_done[head1] || !iqentry_v[head1])
|
5073 |
|
|
&& (iqentry_done[head2] || !iqentry_v[head2])
|
5074 |
|
|
&& (iqentry_done[head3] || !iqentry_v[head3])
|
5075 |
|
|
&& (iqentry_done[head4] || !iqentry_v[head4])
|
5076 |
|
|
&& (iqentry_done[head5] || !iqentry_v[head5]))
|
5077 |
|
|
)
|
5078 |
49 |
robfinch |
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]))
|
5079 |
|
|
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) ||
|
5080 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
5081 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]))
|
5082 |
|
|
)
|
5083 |
49 |
robfinch |
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) ||
|
5084 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
5085 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
5086 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]))
|
5087 |
|
|
)
|
5088 |
49 |
robfinch |
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) ||
|
5089 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
5090 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
5091 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
5092 |
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]))
|
5093 |
|
|
)
|
5094 |
49 |
robfinch |
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) ||
|
5095 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
5096 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
5097 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
5098 |
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
5099 |
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]))
|
5100 |
|
|
)
|
5101 |
49 |
robfinch |
&& (!(iqentry_iv[head6] && iqentry_memdb[head6]) ||
|
5102 |
48 |
robfinch |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])
|
5103 |
|
|
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])
|
5104 |
|
|
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])
|
5105 |
|
|
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])
|
5106 |
|
|
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])
|
5107 |
|
|
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5]))
|
5108 |
|
|
)
|
5109 |
|
|
// ... and, if it is a SW, there is no chance of it being undone
|
5110 |
|
|
&& (iqentry_load[head7] ||
|
5111 |
|
|
!(iqentry_fc[head0]||iqentry_canex[head0])
|
5112 |
|
|
&& !(iqentry_fc[head1]||iqentry_canex[head1])
|
5113 |
|
|
&& !(iqentry_fc[head2]||iqentry_canex[head2])
|
5114 |
|
|
&& !(iqentry_fc[head3]||iqentry_canex[head3])
|
5115 |
|
|
&& !(iqentry_fc[head4]||iqentry_canex[head4])
|
5116 |
|
|
&& !(iqentry_fc[head5]||iqentry_canex[head5])
|
5117 |
|
|
&& !(iqentry_fc[head6]||iqentry_canex[head6]));
|
5118 |
|
|
`endif
|
5119 |
|
|
end
|
5120 |
|
|
|
5121 |
49 |
robfinch |
reg [2:0] wbptr;
|
5122 |
|
|
always @*
|
5123 |
|
|
begin
|
5124 |
|
|
// Crashes sim
|
5125 |
|
|
// wbptr <= `WB_DEPTH-1;
|
5126 |
|
|
// if (wb_v==8'h0)
|
5127 |
|
|
// wbptr <= 3'd0;
|
5128 |
|
|
// else
|
5129 |
|
|
// begin
|
5130 |
|
|
// for (n = `WB_DEPTH-2; n >= 0; n = n - 1)
|
5131 |
|
|
// if (wb_v[n] && wbptr==`WB_DEPTH-1)
|
5132 |
|
|
// wbptr <= n + 1;
|
5133 |
|
|
// end
|
5134 |
|
|
if (wb_v[6])
|
5135 |
|
|
wbptr <= 3'd7;
|
5136 |
|
|
else if (wb_v[5])
|
5137 |
|
|
wbptr <= 3'd6;
|
5138 |
|
|
else if (wb_v[4])
|
5139 |
|
|
wbptr <= 3'd5;
|
5140 |
|
|
else if (wb_v[3])
|
5141 |
|
|
wbptr <= 3'd4;
|
5142 |
|
|
else if (wb_v[2])
|
5143 |
|
|
wbptr <= 3'd3;
|
5144 |
|
|
else if (wb_v[1])
|
5145 |
|
|
wbptr <= 3'd2;
|
5146 |
|
|
else if (wb_v[0])
|
5147 |
|
|
wbptr <= 3'd1;
|
5148 |
|
|
else
|
5149 |
|
|
wbptr <= 3'd0;
|
5150 |
|
|
end
|
5151 |
|
|
|
5152 |
48 |
robfinch |
// Stomp logic for branch miss.
|
5153 |
|
|
|
5154 |
|
|
FT64_stomp #(QENTRIES) ustmp1
|
5155 |
|
|
(
|
5156 |
|
|
.branchmiss(branchmiss),
|
5157 |
|
|
.branchmiss_thrd(branchmiss_thrd),
|
5158 |
|
|
.missid(missid),
|
5159 |
|
|
.head0(head0),
|
5160 |
|
|
.thrd(iqentry_thrd),
|
5161 |
|
|
.iqentry_v(iqentry_v),
|
5162 |
|
|
.stomp(iqentry_stomp)
|
5163 |
|
|
);
|
5164 |
|
|
|
5165 |
|
|
always @*
|
5166 |
|
|
begin
|
5167 |
51 |
robfinch |
if (iqentry_stomp[0] && iqentry_ret[0])
|
5168 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5169 |
51 |
robfinch |
if (iqentry_stomp[1] && iqentry_ret[1])
|
5170 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5171 |
51 |
robfinch |
if (iqentry_stomp[2] && iqentry_ret[2])
|
5172 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5173 |
51 |
robfinch |
if (iqentry_stomp[3] && iqentry_ret[3])
|
5174 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5175 |
51 |
robfinch |
if (iqentry_stomp[4] && iqentry_ret[4])
|
5176 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5177 |
51 |
robfinch |
if (iqentry_stomp[5] && iqentry_ret[5])
|
5178 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5179 |
51 |
robfinch |
if (iqentry_stomp[6] && iqentry_ret[6])
|
5180 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5181 |
51 |
robfinch |
if (iqentry_stomp[7] && iqentry_ret[7])
|
5182 |
48 |
robfinch |
stompedOnRets = stompedOnRets + 4'd1;
|
5183 |
|
|
end
|
5184 |
|
|
|
5185 |
49 |
robfinch |
reg id1_vi, id2_vi, id3_vi;
|
5186 |
|
|
wire [4:0] id1_ido, id2_ido, id3_ido;
|
5187 |
|
|
wire id1_vo, id2_vo, id3_vo;
|
5188 |
|
|
wire id1_clk, id2_clk, id3_clk;
|
5189 |
48 |
robfinch |
|
5190 |
49 |
robfinch |
// Always at least one decoder
|
5191 |
50 |
robfinch |
assign id1_clk = clk_i;
|
5192 |
|
|
//BUFGCE uclkb2
|
5193 |
|
|
//(
|
5194 |
|
|
// .I(clk_i),
|
5195 |
|
|
// .CE(id1_available),
|
5196 |
|
|
// .O(id1_clk)
|
5197 |
|
|
//);
|
5198 |
48 |
robfinch |
|
5199 |
|
|
FT64_idecoder uid1
|
5200 |
|
|
(
|
5201 |
|
|
.clk(id1_clk),
|
5202 |
|
|
.idv_i(id1_vi),
|
5203 |
|
|
.id_i(id1_id),
|
5204 |
|
|
.instr(id1_instr),
|
5205 |
|
|
.ven(id1_ven),
|
5206 |
|
|
.vl(id1_vl),
|
5207 |
|
|
.thrd(id1_thrd),
|
5208 |
|
|
.predict_taken(id1_pt),
|
5209 |
|
|
.Rt(id1_Rt),
|
5210 |
|
|
.bus(id1_bus),
|
5211 |
|
|
.id_o(id1_ido),
|
5212 |
|
|
.idv_o(id1_vo)
|
5213 |
|
|
);
|
5214 |
|
|
|
5215 |
49 |
robfinch |
generate begin : gIDUInst
|
5216 |
|
|
if (`NUM_IDU > 1) begin
|
5217 |
50 |
robfinch |
//BUFGCE uclkb3
|
5218 |
|
|
//(
|
5219 |
|
|
// .I(clk_i),
|
5220 |
|
|
// .CE(id2_available),
|
5221 |
|
|
// .O(id2_clk)
|
5222 |
|
|
//);
|
5223 |
|
|
assign id2_clk = clk_i;
|
5224 |
48 |
robfinch |
|
5225 |
|
|
FT64_idecoder uid2
|
5226 |
|
|
(
|
5227 |
|
|
.clk(id2_clk),
|
5228 |
|
|
.idv_i(id2_vi),
|
5229 |
|
|
.id_i(id2_id),
|
5230 |
|
|
.instr(id2_instr),
|
5231 |
|
|
.ven(id2_ven),
|
5232 |
|
|
.vl(id2_vl),
|
5233 |
|
|
.thrd(id2_thrd),
|
5234 |
|
|
.predict_taken(id2_pt),
|
5235 |
|
|
.Rt(id2_Rt),
|
5236 |
|
|
.bus(id2_bus),
|
5237 |
|
|
.id_o(id2_ido),
|
5238 |
|
|
.idv_o(id2_vo)
|
5239 |
|
|
);
|
5240 |
49 |
robfinch |
end
|
5241 |
|
|
if (`NUM_IDU > 2) begin
|
5242 |
50 |
robfinch |
//BUFGCE uclkb4
|
5243 |
|
|
//(
|
5244 |
|
|
// .I(clk_i),
|
5245 |
|
|
// .CE(id3_available),
|
5246 |
|
|
// .O(id3_clk)
|
5247 |
|
|
//);
|
5248 |
|
|
assign id3_clk = clk_i;
|
5249 |
48 |
robfinch |
|
5250 |
49 |
robfinch |
FT64_idecoder uid2
|
5251 |
|
|
(
|
5252 |
|
|
.clk(id3_clk),
|
5253 |
|
|
.idv_i(id3_vi),
|
5254 |
|
|
.id_i(id3_id),
|
5255 |
|
|
.instr(id3_instr),
|
5256 |
|
|
.ven(id3_ven),
|
5257 |
|
|
.vl(id3_vl),
|
5258 |
|
|
.thrd(id3_thrd),
|
5259 |
|
|
.predict_taken(id3_pt),
|
5260 |
|
|
.Rt(id3_Rt),
|
5261 |
|
|
.bus(id3_bus),
|
5262 |
|
|
.id_o(id3_ido),
|
5263 |
|
|
.idv_o(id3_vo)
|
5264 |
|
|
);
|
5265 |
|
|
end
|
5266 |
|
|
end
|
5267 |
|
|
endgenerate
|
5268 |
|
|
|
5269 |
48 |
robfinch |
//
|
5270 |
|
|
// EXECUTE
|
5271 |
|
|
//
|
5272 |
|
|
reg [63:0] csr_r;
|
5273 |
|
|
always @*
|
5274 |
|
|
read_csr(alu0_instr[29:18],csr_r,alu0_thrd);
|
5275 |
|
|
FT64_alu #(.BIG(1'b1),.SUP_VECTOR(SUP_VECTOR)) ualu0 (
|
5276 |
|
|
.rst(rst),
|
5277 |
|
|
.clk(clk),
|
5278 |
|
|
.ld(alu0_ld),
|
5279 |
|
|
.abort(1'b0),
|
5280 |
|
|
.instr(alu0_instr),
|
5281 |
|
|
.a(alu0_argA),
|
5282 |
|
|
.b(alu0_argB),
|
5283 |
|
|
.c(alu0_argC),
|
5284 |
|
|
.pc(alu0_pc),
|
5285 |
|
|
// .imm(alu0_argI),
|
5286 |
|
|
.tgt(alu0_tgt),
|
5287 |
|
|
.ven(alu0_ven),
|
5288 |
|
|
.vm(vm[alu0_instr[25:23]]),
|
5289 |
|
|
.sbl(sbl),
|
5290 |
|
|
.sbu(sbu),
|
5291 |
|
|
.csr(csr_r),
|
5292 |
|
|
.o(alu0_bus),
|
5293 |
|
|
.ob(alu0b_bus),
|
5294 |
|
|
.done(alu0_done),
|
5295 |
|
|
.idle(alu0_idle),
|
5296 |
|
|
.excen(aec[4:0]),
|
5297 |
|
|
.exc(alu0_exc),
|
5298 |
|
|
.thrd(alu0_thrd),
|
5299 |
|
|
.mem(alu0_mem),
|
5300 |
|
|
.shift48(alu0_shft48)
|
5301 |
|
|
);
|
5302 |
49 |
robfinch |
generate begin : gAluInst
|
5303 |
|
|
if (`NUM_ALU > 1) begin
|
5304 |
48 |
robfinch |
FT64_alu #(.BIG(1'b0),.SUP_VECTOR(SUP_VECTOR)) ualu1 (
|
5305 |
|
|
.rst(rst),
|
5306 |
|
|
.clk(clk),
|
5307 |
|
|
.ld(alu1_ld),
|
5308 |
|
|
.abort(1'b0),
|
5309 |
|
|
.instr(alu1_instr),
|
5310 |
|
|
.a(alu1_argA),
|
5311 |
|
|
.b(alu1_argB),
|
5312 |
|
|
.c(alu1_argC),
|
5313 |
|
|
.pc(alu1_pc),
|
5314 |
|
|
//.imm(alu1_argI),
|
5315 |
|
|
.tgt(alu1_tgt),
|
5316 |
|
|
.ven(alu1_ven),
|
5317 |
|
|
.vm(vm[alu1_instr[25:23]]),
|
5318 |
|
|
.sbl(sbl),
|
5319 |
|
|
.sbu(sbu),
|
5320 |
|
|
.csr(64'd0),
|
5321 |
|
|
.o(alu1_bus),
|
5322 |
|
|
.ob(alu1b_bus),
|
5323 |
|
|
.done(alu1_done),
|
5324 |
|
|
.idle(alu1_idle),
|
5325 |
|
|
.excen(aec[4:0]),
|
5326 |
|
|
.exc(alu1_exc),
|
5327 |
|
|
.thrd(1'b0),
|
5328 |
|
|
.mem(alu1_mem),
|
5329 |
|
|
.shift48(alu1_shft48)
|
5330 |
|
|
);
|
5331 |
49 |
robfinch |
end
|
5332 |
|
|
end
|
5333 |
|
|
endgenerate
|
5334 |
|
|
|
5335 |
|
|
generate begin : gFPUInst
|
5336 |
|
|
if (`NUM_FPU > 0) begin
|
5337 |
|
|
wire fpu1_clk;
|
5338 |
50 |
robfinch |
//BUFGCE ufpc1
|
5339 |
|
|
//(
|
5340 |
|
|
// .I(clk_i),
|
5341 |
|
|
// .CE(fpu1_available),
|
5342 |
|
|
// .O(fpu1_clk)
|
5343 |
|
|
//);
|
5344 |
|
|
assign fpu1_clk = clk_i;
|
5345 |
|
|
|
5346 |
48 |
robfinch |
fpUnit ufp1
|
5347 |
|
|
(
|
5348 |
|
|
.rst(rst),
|
5349 |
49 |
robfinch |
.clk(fpu1_clk),
|
5350 |
48 |
robfinch |
.clk4x(clk4x),
|
5351 |
|
|
.ce(1'b1),
|
5352 |
49 |
robfinch |
.ir(fpu1_instr),
|
5353 |
|
|
.ld(fpu1_ld),
|
5354 |
|
|
.a(fpu1_argA),
|
5355 |
|
|
.b(fpu1_argB),
|
5356 |
|
|
.imm(fpu1_argI),
|
5357 |
|
|
.o(fpu1_bus),
|
5358 |
48 |
robfinch |
.csr_i(),
|
5359 |
51 |
robfinch |
.status(fpu_status),
|
5360 |
48 |
robfinch |
.exception(),
|
5361 |
49 |
robfinch |
.done(fpu1_done)
|
5362 |
48 |
robfinch |
);
|
5363 |
49 |
robfinch |
end
|
5364 |
|
|
if (`NUM_FPU > 1) begin
|
5365 |
|
|
wire fpu2_clk;
|
5366 |
50 |
robfinch |
//BUFGCE ufpc2
|
5367 |
|
|
//(
|
5368 |
|
|
// .I(clk_i),
|
5369 |
|
|
// .CE(fpu2_available),
|
5370 |
|
|
// .O(fpu2_clk)
|
5371 |
|
|
//);
|
5372 |
|
|
assign fpu2_clk = clk_i;
|
5373 |
49 |
robfinch |
fpUnit ufp1
|
5374 |
|
|
(
|
5375 |
|
|
.rst(rst),
|
5376 |
|
|
.clk(fpu2_clk),
|
5377 |
|
|
.clk4x(clk4x),
|
5378 |
|
|
.ce(1'b1),
|
5379 |
|
|
.ir(fpu2_instr),
|
5380 |
|
|
.ld(fpu2_ld),
|
5381 |
|
|
.a(fpu2_argA),
|
5382 |
|
|
.b(fpu2_argB),
|
5383 |
|
|
.imm(fpu2_argI),
|
5384 |
|
|
.o(fpu2_bus),
|
5385 |
|
|
.csr_i(),
|
5386 |
51 |
robfinch |
.status(fpu_status),
|
5387 |
49 |
robfinch |
.exception(),
|
5388 |
|
|
.done(fpu2_done)
|
5389 |
|
|
);
|
5390 |
|
|
end
|
5391 |
|
|
end
|
5392 |
|
|
endgenerate
|
5393 |
48 |
robfinch |
|
5394 |
51 |
robfinch |
assign fpu_exc = (fpu1_available|fpu2_available) ?
|
5395 |
|
|
((|fpu1_status[15:0] || |fpu2_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
|
5396 |
49 |
robfinch |
|
5397 |
48 |
robfinch |
assign alu0_v = alu0_dataready,
|
5398 |
|
|
alu1_v = alu1_dataready;
|
5399 |
|
|
assign alu0_id = alu0_sourceid,
|
5400 |
|
|
alu1_id = alu1_sourceid;
|
5401 |
49 |
robfinch |
assign fpu1_v = fpu1_dataready;
|
5402 |
|
|
assign fpu1_id = fpu1_sourceid;
|
5403 |
|
|
assign fpu2_v = fpu2_dataready;
|
5404 |
|
|
assign fpu2_id = fpu2_sourceid;
|
5405 |
48 |
robfinch |
|
5406 |
|
|
`ifdef SUPPORT_SMT
|
5407 |
|
|
wire [1:0] olm = ol[fcu_thrd];
|
5408 |
|
|
`else
|
5409 |
|
|
wire [1:0] olm = ol;
|
5410 |
|
|
`endif
|
5411 |
|
|
|
5412 |
|
|
assign fcu_v = fcu_dataready;
|
5413 |
|
|
assign fcu_id = fcu_sourceid;
|
5414 |
|
|
|
5415 |
|
|
wire [4:0] fcmpo;
|
5416 |
|
|
wire fnanx;
|
5417 |
|
|
fp_cmp_unit ufcmp1 (fcu_argA, fcu_argB, fcmpo, fnanx);
|
5418 |
|
|
|
5419 |
|
|
wire fcu_takb;
|
5420 |
|
|
|
5421 |
|
|
always @*
|
5422 |
|
|
begin
|
5423 |
|
|
fcu_exc <= `FLT_NONE;
|
5424 |
|
|
casez(fcu_instr[`INSTRUCTION_OP])
|
5425 |
|
|
`CHK: begin
|
5426 |
|
|
if (fcu_instr[21])
|
5427 |
|
|
fcu_exc <= fcu_argA >= fcu_argB && fcu_argA < fcu_argC ? `FLT_NONE : `FLT_CHK;
|
5428 |
|
|
end
|
5429 |
|
|
`REX:
|
5430 |
|
|
case(olm)
|
5431 |
|
|
`OL_USER: fcu_exc <= `FLT_PRIV;
|
5432 |
|
|
default: ;
|
5433 |
|
|
endcase
|
5434 |
|
|
endcase
|
5435 |
|
|
end
|
5436 |
|
|
|
5437 |
|
|
FT64_EvalBranch ube1
|
5438 |
|
|
(
|
5439 |
|
|
.instr(fcu_instr),
|
5440 |
|
|
.a(fcu_argA),
|
5441 |
|
|
.b(fcu_argB),
|
5442 |
|
|
.c(fcu_argC),
|
5443 |
|
|
.takb(fcu_takb)
|
5444 |
|
|
);
|
5445 |
|
|
|
5446 |
|
|
FT64_FCU_Calc ufcuc1
|
5447 |
|
|
(
|
5448 |
|
|
.ol(olm),
|
5449 |
|
|
.instr(fcu_instr),
|
5450 |
|
|
.tvec(tvec[fcu_instr[14:13]]),
|
5451 |
|
|
.a(fcu_argA),
|
5452 |
|
|
.i(fcu_argI),
|
5453 |
|
|
.pc(fcu_pc),
|
5454 |
|
|
.im(im),
|
5455 |
|
|
.waitctr(waitctr),
|
5456 |
|
|
.bus(fcu_bus)
|
5457 |
|
|
);
|
5458 |
|
|
|
5459 |
|
|
always @*
|
5460 |
|
|
begin
|
5461 |
|
|
case(fcu_instr[`INSTRUCTION_OP])
|
5462 |
|
|
`R2: fcu_misspc = fcu_argB; // RTI (we don't bother fully decoding this as it's the only R2)
|
5463 |
|
|
`RET: fcu_misspc = fcu_argB;
|
5464 |
|
|
`REX: fcu_misspc = fcu_bus;
|
5465 |
|
|
`BRK: fcu_misspc = {tvec[0][31:8], 1'b0, olm, 5'h0};
|
5466 |
|
|
`JAL: fcu_misspc = fcu_argA + fcu_argI;
|
5467 |
|
|
//`CHK: fcu_misspc = fcu_nextpc + fcu_argI; // Handled as an instruction exception
|
5468 |
|
|
// Default: branch
|
5469 |
|
|
default: fcu_misspc = fcu_takb ? fcu_nextpc + fcu_brdisp : fcu_nextpc;
|
5470 |
|
|
endcase
|
5471 |
|
|
fcu_misspc[0] = 1'b0;
|
5472 |
|
|
end
|
5473 |
|
|
|
5474 |
|
|
// To avoid false branch mispredicts the branch isn't evaluated until the
|
5475 |
|
|
// following instruction queues. The address of the next instruction is
|
5476 |
|
|
// looked at to see if the BTB predicted correctly.
|
5477 |
|
|
|
5478 |
51 |
robfinch |
wire fcu_brk_miss = (fcu_brk || fcu_rti) && fcu_v;
|
5479 |
|
|
wire fcu_ret_miss = fcu_ret && fcu_v && (fcu_argB != iqentry_pc[nid]);
|
5480 |
|
|
wire fcu_jal_miss = fcu_jal && fcu_v && fcu_argA + fcu_argI != iqentry_pc[nid];
|
5481 |
48 |
robfinch |
wire fcu_followed = iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]];
|
5482 |
|
|
always @*
|
5483 |
|
|
if (fcu_dataready) begin
|
5484 |
|
|
// if (fcu_timeout[7])
|
5485 |
|
|
// fcu_branchmiss = TRUE;
|
5486 |
|
|
// Break and RTI switch register sets, and so are always treated as a branch miss in order to
|
5487 |
|
|
// flush the pipeline. Hardware interrupts also stream break instructions so they need to
|
5488 |
|
|
// flushed from the queue so the interrupt is recognized only once.
|
5489 |
|
|
// BRK and RTI are handled as excmiss types which are processed during the commit stage.
|
5490 |
|
|
// else
|
5491 |
|
|
if (fcu_brk_miss)
|
5492 |
|
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
5493 |
|
|
// the following instruction is queued
|
5494 |
|
|
else
|
5495 |
|
|
if (fcu_followed) begin
|
5496 |
|
|
`ifdef SUPPORT_SMT
|
5497 |
|
|
if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol[fcu_thrd]) && fcu_v)
|
5498 |
|
|
`else
|
5499 |
|
|
if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol) && fcu_v)
|
5500 |
|
|
`endif
|
5501 |
|
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
5502 |
|
|
else if (fcu_ret_miss)
|
5503 |
|
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
5504 |
51 |
robfinch |
else if (fcu_branch && fcu_v && (((fcu_takb && (~fcu_bt || (fcu_misspc != iqentry_pc[nid]))) ||
|
5505 |
48 |
robfinch |
(~fcu_takb && ( fcu_bt || (fcu_pc + 32'd4 != iqentry_pc[nid])))) || iqentry_v[nid]))
|
5506 |
|
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
5507 |
|
|
else if (fcu_jal_miss)
|
5508 |
|
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
5509 |
|
|
else if (fcu_instr[`INSTRUCTION_OP] == `CHK && ~fcu_takb && fcu_v)
|
5510 |
|
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
5511 |
|
|
else
|
5512 |
|
|
fcu_branchmiss = FALSE;
|
5513 |
|
|
end
|
5514 |
|
|
else begin
|
5515 |
|
|
// Stuck at the head and can't finish because there's still an uncommitted instruction in the queue.
|
5516 |
|
|
// -> cause a branch miss to clear the queue.
|
5517 |
|
|
if (iqentry_v[nid] && !IsCall(fcu_instr) && !IsJmp(fcu_instr) && fcu_v)
|
5518 |
|
|
fcu_branchmiss = TRUE & ~fcu_clearbm;
|
5519 |
|
|
else
|
5520 |
|
|
/*
|
5521 |
|
|
if (fcu_id==head0 && iqentry_v[idp1(head0)]) begin
|
5522 |
|
|
if ((fcu_bus[0] && (~fcu_bt || (fcu_misspc == iqentry_pc[nid]))) ||
|
5523 |
|
|
(~fcu_bus[0] && ( fcu_bt || (fcu_pc + 32'd4 == iqentry_pc[nid]))))
|
5524 |
|
|
fcu_branchmiss = FALSE;
|
5525 |
|
|
else
|
5526 |
|
|
fcu_branchmiss = TRUE;
|
5527 |
|
|
end
|
5528 |
|
|
else if (fcu_id==head1 && iqentry_v[idp2(head1)]) begin
|
5529 |
|
|
if ((fcu_bus[0] && (~fcu_bt || (fcu_misspc == iqentry_pc[nid]))) ||
|
5530 |
|
|
(~fcu_bus[0] && ( fcu_bt || (fcu_pc + 32'd4 == iqentry_pc[nid]))))
|
5531 |
|
|
fcu_branchmiss = FALSE;
|
5532 |
|
|
else
|
5533 |
|
|
fcu_branchmiss = TRUE;
|
5534 |
|
|
end
|
5535 |
|
|
else*/
|
5536 |
|
|
fcu_branchmiss = FALSE;
|
5537 |
|
|
end
|
5538 |
|
|
end
|
5539 |
|
|
else
|
5540 |
|
|
fcu_branchmiss = FALSE;
|
5541 |
|
|
|
5542 |
|
|
// Flow control ops don't issue until the next instruction queues.
|
5543 |
|
|
// The fcu_timeout tracks how long the flow control op has been in the "out" state.
|
5544 |
|
|
// It should never be that way more than a couple of cycles. Sometimes the fcu_wr pulse got missed
|
5545 |
|
|
// because the following instruction got stomped on during a branchmiss, hence iqentry_v isn't true.
|
5546 |
|
|
wire fcu_wr = (fcu_v && iqentry_v[nid] && iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]]);// // && iqentry_v[nid]
|
5547 |
|
|
// && fcu_instr==iqentry_instr[fcu_id[`QBITS]]);// || fcu_timeout==8'h05;
|
5548 |
|
|
|
5549 |
|
|
FT64_RMW_alu urmwalu0 (rmw_instr, rmw_argA, rmw_argB, rmw_argC, rmw_res);
|
5550 |
|
|
|
5551 |
|
|
//assign fcu_done = IsWait(fcu_instr) ? ((waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]]) :
|
5552 |
|
|
// fcu_v && iqentry_v[idp1(fcu_id)] && iqentry_sn[idp1(fcu_id)]==iqentry_sn[fcu_id[`QBITS]]+5'd1;
|
5553 |
|
|
|
5554 |
|
|
// An exception in a committing instruction takes precedence
|
5555 |
|
|
/*
|
5556 |
|
|
Too slow. Needs to be registered
|
5557 |
|
|
assign branchmiss = excmiss|fcu_branchmiss,
|
5558 |
|
|
misspc = excmiss ? excmisspc : fcu_misspc,
|
5559 |
|
|
missid = excmiss ? (|iqentry_exc[head0] ? head0 : head1) : fcu_sourceid;
|
5560 |
|
|
assign branchmiss_thrd = excmiss ? excthrd : fcu_thrd;
|
5561 |
|
|
*/
|
5562 |
|
|
|
5563 |
|
|
//
|
5564 |
|
|
// additional DRAM-enqueue logic
|
5565 |
|
|
|
5566 |
|
|
assign dram_avail = (dram0 == `DRAMSLOT_AVAIL || dram1 == `DRAMSLOT_AVAIL || dram2 == `DRAMSLOT_AVAIL);
|
5567 |
|
|
|
5568 |
|
|
assign iqentry_memopsvalid[0] = (iqentry_mem[0] & iqentry_a2_v[0] & iqentry_agen[0]),
|
5569 |
|
|
iqentry_memopsvalid[1] = (iqentry_mem[1] & iqentry_a2_v[1] & iqentry_agen[1]),
|
5570 |
|
|
iqentry_memopsvalid[2] = (iqentry_mem[2] & iqentry_a2_v[2] & iqentry_agen[2]),
|
5571 |
|
|
iqentry_memopsvalid[3] = (iqentry_mem[3] & iqentry_a2_v[3] & iqentry_agen[3]),
|
5572 |
|
|
iqentry_memopsvalid[4] = (iqentry_mem[4] & iqentry_a2_v[4] & iqentry_agen[4]),
|
5573 |
|
|
iqentry_memopsvalid[5] = (iqentry_mem[5] & iqentry_a2_v[5] & iqentry_agen[5]),
|
5574 |
|
|
iqentry_memopsvalid[6] = (iqentry_mem[6] & iqentry_a2_v[6] & iqentry_agen[6]),
|
5575 |
|
|
iqentry_memopsvalid[7] = (iqentry_mem[7] & iqentry_a2_v[7] & iqentry_agen[7]);
|
5576 |
|
|
|
5577 |
|
|
assign iqentry_memready[0] = (iqentry_v[0] & iqentry_memopsvalid[0] & ~iqentry_memissue[0] & ~iqentry_done[0] & ~iqentry_out[0] & ~iqentry_stomp[0]),
|
5578 |
|
|
iqentry_memready[1] = (iqentry_v[1] & iqentry_memopsvalid[1] & ~iqentry_memissue[1] & ~iqentry_done[1] & ~iqentry_out[1] & ~iqentry_stomp[1]),
|
5579 |
|
|
iqentry_memready[2] = (iqentry_v[2] & iqentry_memopsvalid[2] & ~iqentry_memissue[2] & ~iqentry_done[2] & ~iqentry_out[2] & ~iqentry_stomp[2]),
|
5580 |
|
|
iqentry_memready[3] = (iqentry_v[3] & iqentry_memopsvalid[3] & ~iqentry_memissue[3] & ~iqentry_done[3] & ~iqentry_out[3] & ~iqentry_stomp[3]),
|
5581 |
|
|
iqentry_memready[4] = (iqentry_v[4] & iqentry_memopsvalid[4] & ~iqentry_memissue[4] & ~iqentry_done[4] & ~iqentry_out[4] & ~iqentry_stomp[4]),
|
5582 |
|
|
iqentry_memready[5] = (iqentry_v[5] & iqentry_memopsvalid[5] & ~iqentry_memissue[5] & ~iqentry_done[5] & ~iqentry_out[5] & ~iqentry_stomp[5]),
|
5583 |
|
|
iqentry_memready[6] = (iqentry_v[6] & iqentry_memopsvalid[6] & ~iqentry_memissue[6] & ~iqentry_done[6] & ~iqentry_out[6] & ~iqentry_stomp[6]),
|
5584 |
|
|
iqentry_memready[7] = (iqentry_v[7] & iqentry_memopsvalid[7] & ~iqentry_memissue[7] & ~iqentry_done[7] & ~iqentry_out[7] & ~iqentry_stomp[7]);
|
5585 |
|
|
|
5586 |
50 |
robfinch |
assign outstanding_stores = (dram0 && dram0_store) ||
|
5587 |
|
|
(dram1 && dram1_store) ||
|
5588 |
|
|
(dram2 && dram2_store);
|
5589 |
48 |
robfinch |
|
5590 |
|
|
//
|
5591 |
|
|
// additional COMMIT logic
|
5592 |
|
|
//
|
5593 |
|
|
always @*
|
5594 |
|
|
begin
|
5595 |
|
|
commit0_v <= ({iqentry_v[head0], iqentry_cmt[head0]} == 2'b11 && ~|panic);
|
5596 |
|
|
commit0_id <= {iqentry_mem[head0], head0}; // if a memory op, it has a DRAM-bus id
|
5597 |
|
|
commit0_tgt <= iqentry_tgt[head0];
|
5598 |
|
|
commit0_we <= iqentry_we[head0];
|
5599 |
|
|
commit0_bus <= iqentry_res[head0];
|
5600 |
49 |
robfinch |
if (`NUM_CMT > 1) begin
|
5601 |
|
|
commit1_v <= ({iqentry_v[head0], iqentry_cmt[head0]} != 2'b10
|
5602 |
|
|
&& {iqentry_v[head1], iqentry_cmt[head1]} == 2'b11
|
5603 |
|
|
&& ~|panic);
|
5604 |
|
|
commit1_id <= {iqentry_mem[head1], head1};
|
5605 |
|
|
commit1_tgt <= iqentry_tgt[head1];
|
5606 |
|
|
commit1_we <= iqentry_we[head1];
|
5607 |
|
|
commit1_bus <= iqentry_res[head1];
|
5608 |
|
|
end
|
5609 |
|
|
else begin
|
5610 |
|
|
commit1_tgt <= 12'h000;
|
5611 |
|
|
commit1_we <= 8'h00;
|
5612 |
|
|
end
|
5613 |
48 |
robfinch |
end
|
5614 |
|
|
|
5615 |
51 |
robfinch |
assign int_commit = (commit0_v && iqentry_irq[head0]) ||
|
5616 |
|
|
(commit0_v && commit1_v && iqentry_irq[head1] && `NUM_CMT > 1);
|
5617 |
48 |
robfinch |
|
5618 |
|
|
// Detect if a given register will become valid during the current cycle.
|
5619 |
|
|
// We want a signal that is active during the current clock cycle for the read
|
5620 |
|
|
// through register file, which trims a cycle off register access for every
|
5621 |
|
|
// instruction. But two different kinds of assignment statements can't be
|
5622 |
|
|
// placed under the same always block, it's a bad practice and may not work.
|
5623 |
|
|
// So a signal is created here with it's own always block.
|
5624 |
|
|
reg [AREGS-1:0] regIsValid;
|
5625 |
|
|
always @*
|
5626 |
|
|
begin
|
5627 |
|
|
for (n = 1; n < AREGS; n = n + 1)
|
5628 |
|
|
begin
|
5629 |
|
|
regIsValid[n] = rf_v[n];
|
5630 |
|
|
if (branchmiss)
|
5631 |
|
|
if (~livetarget[n]) begin
|
5632 |
|
|
if (branchmiss_thrd) begin
|
5633 |
|
|
if (n >= 128)
|
5634 |
|
|
regIsValid[n] = `VAL;
|
5635 |
|
|
end
|
5636 |
|
|
else begin
|
5637 |
|
|
if (n < 128)
|
5638 |
|
|
regIsValid[n] = `VAL;
|
5639 |
|
|
end
|
5640 |
|
|
end
|
5641 |
|
|
if (commit0_v && n=={commit0_tgt[7:0]})
|
5642 |
|
|
regIsValid[n] = regIsValid[n] | (rf_source[ {commit0_tgt[7:0]} ] == commit0_id
|
5643 |
|
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit0_id[`QBITS] ]));
|
5644 |
49 |
robfinch |
if (commit1_v && n=={commit1_tgt[7:0]} && `NUM_CMT > 1)
|
5645 |
48 |
robfinch |
regIsValid[n] = regIsValid[n] | (rf_source[ {commit1_tgt[7:0]} ] == commit1_id
|
5646 |
|
|
|| (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit1_id[`QBITS] ]));
|
5647 |
|
|
end
|
5648 |
|
|
regIsValid[0] = `VAL;
|
5649 |
|
|
end
|
5650 |
|
|
|
5651 |
|
|
// Wait until the cycle after Ra becomes valid to give time to read
|
5652 |
|
|
// the vector element from the register file.
|
5653 |
|
|
reg rf_vra0, rf_vra1;
|
5654 |
|
|
/*always @(posedge clk)
|
5655 |
|
|
rf_vra0 <= regIsValid[Ra0s];
|
5656 |
|
|
always @(posedge clk)
|
5657 |
|
|
rf_vra1 <= regIsValid[Ra1s];
|
5658 |
|
|
*/
|
5659 |
|
|
// Check how many instructions can be queued. This might be fewer than the
|
5660 |
|
|
// number ready to queue from the fetch stage if queue slots aren't
|
5661 |
|
|
// available or if there are no more physical registers left for remapping.
|
5662 |
|
|
// The fetch stage needs to know how many instructions will queue so this
|
5663 |
|
|
// logic is placed here.
|
5664 |
|
|
// NOPs are filtered out and do not enter the instruction queue. The core
|
5665 |
|
|
// will stream NOPs on a cache miss and they would mess up the queue order
|
5666 |
|
|
// if there are immediate prefixes in the queue.
|
5667 |
|
|
// For the VEX instruction, the instruction can't queue until register Ra
|
5668 |
|
|
// is valid, because register Ra is used to specify the vector element to
|
5669 |
|
|
// read.
|
5670 |
|
|
wire q2open = iqentry_v[tail0]==`INV && iqentry_v[tail1]==`INV;
|
5671 |
|
|
wire q3open = iqentry_v[tail0]==`INV && iqentry_v[tail1]==`INV && iqentry_v[idp1(tail1)]==`INV;
|
5672 |
|
|
always @*
|
5673 |
|
|
begin
|
5674 |
|
|
canq1 <= FALSE;
|
5675 |
|
|
canq2 <= FALSE;
|
5676 |
|
|
queued1 <= FALSE;
|
5677 |
|
|
queued2 <= FALSE;
|
5678 |
|
|
queuedNop <= FALSE;
|
5679 |
|
|
vqueued2 <= FALSE;
|
5680 |
|
|
if (!branchmiss) begin
|
5681 |
|
|
// Two available
|
5682 |
|
|
if (fetchbuf1_v & fetchbuf0_v) begin
|
5683 |
|
|
// Is there a pair of NOPs ? (cache miss)
|
5684 |
|
|
if ((fetchbuf0_instr[`INSTRUCTION_OP]==`NOP) && (fetchbuf1_instr[`INSTRUCTION_OP]==`NOP))
|
5685 |
|
|
queuedNop <= TRUE;
|
5686 |
|
|
else begin
|
5687 |
|
|
// If it's a predicted branch queue only the first instruction, the second
|
5688 |
|
|
// instruction will be stomped on.
|
5689 |
|
|
if (take_branch0 && fetchbuf1_thrd==fetchbuf0_thrd) begin
|
5690 |
|
|
if (iqentry_v[tail0]==`INV) begin
|
5691 |
|
|
canq1 <= TRUE;
|
5692 |
|
|
queued1 <= TRUE;
|
5693 |
|
|
end
|
5694 |
|
|
end
|
5695 |
|
|
// This is where a single NOP is allowed through to simplify the code. A
|
5696 |
|
|
// single NOP can't be a cache miss. Otherwise it would be necessary to queue
|
5697 |
|
|
// fetchbuf1 on tail0 it would add a nightmare to the enqueue code.
|
5698 |
|
|
// Not a branch and there are two instructions fetched, see whether or not
|
5699 |
|
|
// both instructions can be queued.
|
5700 |
|
|
else begin
|
5701 |
|
|
if (iqentry_v[tail0]==`INV) begin
|
5702 |
|
|
canq1 <= !IsVex(fetchbuf0_instr) || rf_vra0 || !SUP_VECTOR;
|
5703 |
|
|
queued1 <= (
|
5704 |
|
|
((!IsVex(fetchbuf0_instr) || rf_vra0) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
|
5705 |
|
|
if (iqentry_v[tail1]==`INV) begin
|
5706 |
|
|
canq2 <= ((!IsVex(fetchbuf1_instr) || rf_vra1)) || !SUP_VECTOR;
|
5707 |
|
|
queued2 <= (
|
5708 |
|
|
(!IsVector(fetchbuf1_instr) && (!IsVex(fetchbuf1_instr) || rf_vra1) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
|
5709 |
|
|
vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
|
5710 |
|
|
end
|
5711 |
|
|
end
|
5712 |
|
|
// If an irq is active during a vector instruction fetch, claim the vector instruction
|
5713 |
|
|
// is finished queueing even though it may not be. It'll pick up where it left off after
|
5714 |
|
|
// the exception is processed.
|
5715 |
|
|
if (hirq) begin
|
5716 |
|
|
if (IsVector(fetchbuf0_instr) && IsVector(fetchbuf1_instr) && vechain) begin
|
5717 |
|
|
queued1 <= TRUE;
|
5718 |
|
|
queued2 <= TRUE;
|
5719 |
|
|
end
|
5720 |
|
|
else if (IsVector(fetchbuf0_instr)) begin
|
5721 |
|
|
queued1 <= TRUE;
|
5722 |
|
|
if (vqe0 < vl-2)
|
5723 |
|
|
queued2 <= TRUE;
|
5724 |
|
|
else
|
5725 |
|
|
queued2 <= iqentry_v[tail1]==`INV;
|
5726 |
|
|
end
|
5727 |
|
|
end
|
5728 |
|
|
end
|
5729 |
|
|
end
|
5730 |
|
|
end
|
5731 |
|
|
// One available
|
5732 |
|
|
else if (fetchbuf0_v) begin
|
5733 |
|
|
if (fetchbuf0_instr[`INSTRUCTION_OP]!=`NOP) begin
|
5734 |
|
|
if (iqentry_v[tail0]==`INV) begin
|
5735 |
|
|
canq1 <= !IsVex(fetchbuf0_instr) || rf_vra0 || !SUP_VECTOR;
|
5736 |
|
|
queued1 <=
|
5737 |
|
|
(((!IsVex(fetchbuf0_instr) || rf_vra0) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
|
5738 |
|
|
end
|
5739 |
|
|
if (iqentry_v[tail1]==`INV) begin
|
5740 |
|
|
canq2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && SUP_VECTOR;
|
5741 |
|
|
vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
|
5742 |
|
|
end
|
5743 |
|
|
if (hirq) begin
|
5744 |
|
|
if (IsVector(fetchbuf0_instr)) begin
|
5745 |
|
|
queued1 <= TRUE;
|
5746 |
|
|
if (vqe0 < vl-2)
|
5747 |
|
|
queued2 <= iqentry_v[tail1]==`INV;
|
5748 |
|
|
end
|
5749 |
|
|
end
|
5750 |
|
|
end
|
5751 |
|
|
else
|
5752 |
|
|
queuedNop <= TRUE;
|
5753 |
|
|
end
|
5754 |
|
|
else if (fetchbuf1_v) begin
|
5755 |
|
|
if (fetchbuf1_instr[`INSTRUCTION_OP]!=`NOP) begin
|
5756 |
|
|
if (iqentry_v[tail0]==`INV) begin
|
5757 |
|
|
canq1 <= !IsVex(fetchbuf1_instr) || rf_vra1 || !SUP_VECTOR;
|
5758 |
|
|
queued1 <= (
|
5759 |
|
|
((!IsVex(fetchbuf1_instr) || rf_vra1) && (!IsVector(fetchbuf1_instr))) || !SUP_VECTOR);
|
5760 |
|
|
end
|
5761 |
|
|
if (iqentry_v[tail1]==`INV) begin
|
5762 |
|
|
canq2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2 && SUP_VECTOR;
|
5763 |
|
|
vqueued2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2;
|
5764 |
|
|
end
|
5765 |
|
|
if (hirq) begin
|
5766 |
|
|
if (IsVector(fetchbuf1_instr)) begin
|
5767 |
|
|
queued1 <= TRUE;
|
5768 |
|
|
if (vqe1 < vl-2)
|
5769 |
|
|
queued2 <= iqentry_v[tail1]==`INV;
|
5770 |
|
|
end
|
5771 |
|
|
end
|
5772 |
|
|
end
|
5773 |
|
|
else
|
5774 |
|
|
queuedNop <= TRUE;
|
5775 |
|
|
end
|
5776 |
|
|
//else no instructions available to queue
|
5777 |
|
|
end
|
5778 |
|
|
else begin
|
5779 |
|
|
// One available
|
5780 |
|
|
if (fetchbuf0_v && fetchbuf0_thrd != branchmiss_thrd) begin
|
5781 |
|
|
if (fetchbuf0_instr[`INSTRUCTION_OP]!=`NOP) begin
|
5782 |
|
|
if (iqentry_v[tail0]==`INV) begin
|
5783 |
|
|
canq1 <= !IsVex(fetchbuf0_instr) || rf_vra0 || !SUP_VECTOR;
|
5784 |
|
|
queued1 <= (
|
5785 |
|
|
((!IsVex(fetchbuf0_instr) || rf_vra0) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
|
5786 |
|
|
end
|
5787 |
|
|
if (iqentry_v[tail1]==`INV) begin
|
5788 |
|
|
canq2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && SUP_VECTOR;
|
5789 |
|
|
vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
|
5790 |
|
|
end
|
5791 |
|
|
end
|
5792 |
|
|
else
|
5793 |
|
|
queuedNop <= TRUE;
|
5794 |
|
|
end
|
5795 |
|
|
else if (fetchbuf1_v && fetchbuf1_thrd != branchmiss_thrd) begin
|
5796 |
|
|
if (fetchbuf1_instr[`INSTRUCTION_OP]!=`NOP) begin
|
5797 |
|
|
if (iqentry_v[tail0]==`INV) begin
|
5798 |
|
|
canq1 <= !IsVex(fetchbuf1_instr) || rf_vra1 || !SUP_VECTOR;
|
5799 |
|
|
queued1 <= (
|
5800 |
|
|
((!IsVex(fetchbuf1_instr) || rf_vra1) && (!IsVector(fetchbuf1_instr))) || !SUP_VECTOR);
|
5801 |
|
|
end
|
5802 |
|
|
if (iqentry_v[tail1]==`INV) begin
|
5803 |
|
|
canq2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2 && SUP_VECTOR;
|
5804 |
|
|
vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
|
5805 |
|
|
end
|
5806 |
|
|
end
|
5807 |
|
|
else
|
5808 |
|
|
queuedNop <= TRUE;
|
5809 |
|
|
end
|
5810 |
|
|
else
|
5811 |
|
|
queuedNop <= TRUE;
|
5812 |
|
|
end
|
5813 |
|
|
end
|
5814 |
|
|
|
5815 |
|
|
//
|
5816 |
|
|
// Branchmiss seems to be sticky sometimes during simulation. For instance branch miss
|
5817 |
|
|
// and cache miss at same time. The branchmiss should clear before the core continues
|
5818 |
|
|
// so the positive edge is detected to avoid incrementing the sequnce number too many
|
5819 |
|
|
// times.
|
5820 |
|
|
wire pebm;
|
5821 |
|
|
edge_det uedbm (.rst(rst), .clk(clk), .ce(1'b1), .i(branchmiss), .pe(pebm), .ne(), .ee() );
|
5822 |
|
|
|
5823 |
|
|
reg [5:0] ld_time;
|
5824 |
|
|
reg [63:0] wc_time_dat;
|
5825 |
|
|
reg [63:0] wc_times;
|
5826 |
|
|
always @(posedge tm_clk_i)
|
5827 |
|
|
begin
|
5828 |
|
|
if (|ld_time)
|
5829 |
|
|
wc_time <= wc_time_dat;
|
5830 |
|
|
else begin
|
5831 |
|
|
wc_time[31:0] <= wc_time[31:0] + 32'd1;
|
5832 |
|
|
if (wc_time[31:0] >= TM_CLKFREQ-1) begin
|
5833 |
|
|
wc_time[31:0] <= 32'd0;
|
5834 |
|
|
wc_time[63:32] <= wc_time[63:32] + 32'd1;
|
5835 |
|
|
end
|
5836 |
|
|
end
|
5837 |
|
|
end
|
5838 |
|
|
|
5839 |
|
|
|
5840 |
|
|
// Monster clock domain.
|
5841 |
|
|
// Like to move some of this to clocking under different always blocks in order
|
5842 |
|
|
// to help out the toolset's synthesis, but it ain't gonna be easy.
|
5843 |
|
|
// Simulation doesn't like it if things are under separate always blocks.
|
5844 |
|
|
// Synthesis doesn't like it if things are under the same always block.
|
5845 |
|
|
|
5846 |
49 |
robfinch |
//always @(posedge clk)
|
5847 |
|
|
//begin
|
5848 |
|
|
// branchmiss <= excmiss|fcu_branchmiss;
|
5849 |
|
|
// misspc <= excmiss ? excmisspc : fcu_misspc;
|
5850 |
|
|
// missid <= excmiss ? (|iqentry_exc[head0] ? head0 : head1) : fcu_sourceid;
|
5851 |
|
|
// branchmiss_thrd <= excmiss ? excthrd : fcu_thrd;
|
5852 |
|
|
//end
|
5853 |
48 |
robfinch |
|
5854 |
|
|
always @(posedge clk)
|
5855 |
|
|
if (rst) begin
|
5856 |
|
|
`ifdef SUPPORT_SMT
|
5857 |
|
|
mstatus[0] <= 64'h0007; // select register set #0 for thread 0
|
5858 |
|
|
mstatus[1] <= 64'h8007; // select register set #2 for thread 1
|
5859 |
|
|
`else
|
5860 |
|
|
mstatus <= 64'h0007; // select register set #0 for thread 0
|
5861 |
|
|
`endif
|
5862 |
|
|
for (n = 0; n < QENTRIES; n = n + 1) begin
|
5863 |
51 |
robfinch |
iqentry_v[n] <= `INV;
|
5864 |
|
|
iqentry_iv[n] <= `INV;
|
5865 |
|
|
iqentry_is[n] <= 3'b00;
|
5866 |
|
|
iqentry_done[n] <= FALSE;
|
5867 |
|
|
iqentry_cmt[n] <= FALSE;
|
5868 |
|
|
iqentry_out[n] <= FALSE;
|
5869 |
|
|
iqentry_agen[n] <= FALSE;
|
5870 |
|
|
iqentry_sn[n] <= 32'd0;
|
5871 |
|
|
iqentry_pt[n] <= FALSE;
|
5872 |
|
|
iqentry_bt[n] <= FALSE;
|
5873 |
|
|
iqentry_br[n] <= FALSE;
|
5874 |
|
|
iqentry_aq[n] <= FALSE;
|
5875 |
|
|
iqentry_rl[n] <= FALSE;
|
5876 |
|
|
iqentry_alu0[n] <= FALSE;
|
5877 |
|
|
iqentry_alu[n] <= FALSE;
|
5878 |
|
|
iqentry_alu0_issue[n] <= FALSE;
|
5879 |
|
|
iqentry_alu1_issue[n] <= FALSE;
|
5880 |
|
|
iqentry_fpu[n] <= FALSE;
|
5881 |
|
|
iqentry_fpu1_issue[n] <= FALSE;
|
5882 |
|
|
iqentry_fpu2_issue[n] <= FALSE;
|
5883 |
|
|
iqentry_fsync[n] <= FALSE;
|
5884 |
|
|
iqentry_fc[n] <= FALSE;
|
5885 |
|
|
iqentry_fcu_issue[n] <= FALSE;
|
5886 |
|
|
iqentry_jmp[n] <= FALSE;
|
5887 |
|
|
iqentry_jal[n] <= FALSE;
|
5888 |
|
|
iqentry_ret[n] <= FALSE;
|
5889 |
|
|
iqentry_brk[n] <= FALSE;
|
5890 |
|
|
iqentry_irq[n] <= FALSE;
|
5891 |
|
|
iqentry_rti[n] <= FALSE;
|
5892 |
|
|
iqentry_ldcmp[n] <= FALSE;
|
5893 |
|
|
iqentry_load[n] <= FALSE;
|
5894 |
|
|
iqentry_rtop[n] <= FALSE;
|
5895 |
|
|
iqentry_sei[n] <= FALSE;
|
5896 |
|
|
iqentry_shft48[n] <= FALSE;
|
5897 |
|
|
iqentry_sync[n] <= FALSE;
|
5898 |
|
|
iqentry_ven[n] <= 6'd0;
|
5899 |
|
|
iqentry_vl[n] <= 8'd0;
|
5900 |
|
|
iqentry_we[n] <= 8'h00;
|
5901 |
|
|
iqentry_rfw[n] <= FALSE;
|
5902 |
|
|
iqentry_rmw[n] <= FALSE;
|
5903 |
|
|
iqentry_pc[n] <= RSTPC;
|
5904 |
48 |
robfinch |
iqentry_instr[n] <= `NOP_INSN;
|
5905 |
|
|
iqentry_insln[n] <= 4'd4;
|
5906 |
|
|
iqentry_preload[n] <= FALSE;
|
5907 |
|
|
iqentry_mem[n] <= FALSE;
|
5908 |
|
|
iqentry_memndx[n] <= FALSE;
|
5909 |
51 |
robfinch |
iqentry_memissue[n] <= FALSE;
|
5910 |
|
|
iqentry_mem_islot[n] <= 3'd0;
|
5911 |
|
|
iqentry_memdb[n] <= FALSE;
|
5912 |
|
|
iqentry_memsb[n] <= FALSE;
|
5913 |
|
|
iqentry_tgt[n] <= 6'd0;
|
5914 |
|
|
iqentry_imm[n] <= 1'b0;
|
5915 |
|
|
iqentry_a0[n] <= 64'd0;
|
5916 |
|
|
iqentry_a1[n] <= 64'd0;
|
5917 |
|
|
iqentry_a2[n] <= 64'd0;
|
5918 |
|
|
iqentry_a3[n] <= 64'd0;
|
5919 |
|
|
iqentry_a1_v[n] <= `INV;
|
5920 |
|
|
iqentry_a2_v[n] <= `INV;
|
5921 |
|
|
iqentry_a3_v[n] <= `INV;
|
5922 |
|
|
iqentry_a1_s[n] <= 5'd0;
|
5923 |
|
|
iqentry_a2_s[n] <= 5'd0;
|
5924 |
|
|
iqentry_a3_s[n] <= 5'd0;
|
5925 |
|
|
iqentry_canex[n] <= FALSE;
|
5926 |
48 |
robfinch |
end
|
5927 |
49 |
robfinch |
bwhich <= 2'b00;
|
5928 |
48 |
robfinch |
dram0 <= `DRAMSLOT_AVAIL;
|
5929 |
|
|
dram1 <= `DRAMSLOT_AVAIL;
|
5930 |
|
|
dram2 <= `DRAMSLOT_AVAIL;
|
5931 |
|
|
dram0_instr <= `NOP_INSN;
|
5932 |
|
|
dram1_instr <= `NOP_INSN;
|
5933 |
|
|
dram2_instr <= `NOP_INSN;
|
5934 |
|
|
dram0_addr <= 32'h0;
|
5935 |
|
|
dram1_addr <= 32'h0;
|
5936 |
|
|
dram2_addr <= 32'h0;
|
5937 |
|
|
L1_adr <= RSTPC;
|
5938 |
|
|
invic <= FALSE;
|
5939 |
|
|
tail0 <= 3'd0;
|
5940 |
|
|
tail1 <= 3'd1;
|
5941 |
|
|
head0 <= 0;
|
5942 |
|
|
head1 <= 1;
|
5943 |
|
|
head2 <= 2;
|
5944 |
|
|
head3 <= 3;
|
5945 |
|
|
head4 <= 4;
|
5946 |
|
|
head5 <= 5;
|
5947 |
|
|
head6 <= 6;
|
5948 |
|
|
head7 <= 7;
|
5949 |
|
|
panic = `PANIC_NONE;
|
5950 |
|
|
alu0_dataready <= 0;
|
5951 |
|
|
alu1_dataready <= 0;
|
5952 |
|
|
alu0_sourceid <= 5'd0;
|
5953 |
|
|
alu1_sourceid <= 5'd0;
|
5954 |
|
|
`ifdef SIM
|
5955 |
|
|
alu0_pc <= RSTPC;
|
5956 |
|
|
alu0_instr <= `NOP_INSN;
|
5957 |
|
|
alu0_argA <= 64'h0;
|
5958 |
|
|
alu0_argB <= 64'h0;
|
5959 |
|
|
alu0_argC <= 64'h0;
|
5960 |
|
|
alu0_argI <= 64'h0;
|
5961 |
|
|
alu0_bt <= 1'b0;
|
5962 |
|
|
alu0_mem <= 1'b0;
|
5963 |
|
|
alu0_shft48 <= 1'b0;
|
5964 |
|
|
alu0_thrd <= 1'b0;
|
5965 |
|
|
alu0_tgt <= 6'h00;
|
5966 |
|
|
alu0_ven <= 6'd0;
|
5967 |
|
|
alu1_pc <= RSTPC;
|
5968 |
|
|
alu1_instr <= `NOP_INSN;
|
5969 |
|
|
alu1_argA <= 64'h0;
|
5970 |
|
|
alu1_argB <= 64'h0;
|
5971 |
|
|
alu1_argC <= 64'h0;
|
5972 |
|
|
alu1_argI <= 64'h0;
|
5973 |
|
|
alu1_bt <= 1'b0;
|
5974 |
|
|
alu1_mem <= 1'b0;
|
5975 |
|
|
alu1_shft48 <= 1'b0;
|
5976 |
|
|
alu1_thrd <= 1'b0;
|
5977 |
|
|
alu1_tgt <= 6'h00;
|
5978 |
|
|
alu1_ven <= 6'd0;
|
5979 |
|
|
`endif
|
5980 |
|
|
fcu_dataready <= 0;
|
5981 |
|
|
fcu_instr <= `NOP_INSN;
|
5982 |
|
|
dramA_v <= 0;
|
5983 |
|
|
dramB_v <= 0;
|
5984 |
|
|
dramC_v <= 0;
|
5985 |
|
|
I <= 0;
|
5986 |
|
|
icstate <= IDLE;
|
5987 |
|
|
bstate <= BIDLE;
|
5988 |
|
|
tick <= 64'd0;
|
5989 |
|
|
bte_o <= 2'b00;
|
5990 |
|
|
cti_o <= 3'b000;
|
5991 |
|
|
cyc_o <= `LOW;
|
5992 |
|
|
stb_o <= `LOW;
|
5993 |
|
|
we_o <= `LOW;
|
5994 |
|
|
sel_o <= 8'h00;
|
5995 |
|
|
sr_o <= `LOW;
|
5996 |
|
|
cr_o <= `LOW;
|
5997 |
|
|
adr_o <= RSTPC;
|
5998 |
|
|
icl_o <= `LOW; // instruction cache load
|
5999 |
|
|
cr0 <= 64'd0;
|
6000 |
|
|
cr0[13:8] <= 6'd0; // select register set #0
|
6001 |
|
|
cr0[30] <= TRUE; // enable data caching
|
6002 |
|
|
cr0[32] <= TRUE; // enable branch predictor
|
6003 |
|
|
cr0[16] <= 1'b0; // disable SMT
|
6004 |
|
|
cr0[17] <= 1'b0; // sequence number reset = 1
|
6005 |
|
|
pcr <= 32'd0;
|
6006 |
|
|
pcr2 <= 64'd0;
|
6007 |
|
|
for (n = 0; n < PREGS; n = n + 1)
|
6008 |
|
|
rf_v[n] <= `VAL;
|
6009 |
|
|
tgtq <= FALSE;
|
6010 |
51 |
robfinch |
fp_rm <= 3'd0; // round nearest even - default rounding mode
|
6011 |
|
|
fpu_csr[37:32] <= 5'd31; // register set #31
|
6012 |
48 |
robfinch |
waitctr <= 64'd0;
|
6013 |
|
|
for (n = 0; n < 16; n = n + 1)
|
6014 |
|
|
badaddr[n] <= 64'd0;
|
6015 |
|
|
sbl <= 32'h0;
|
6016 |
|
|
sbu <= 32'hFFFFFFFF;
|
6017 |
|
|
// Vector
|
6018 |
|
|
vqe0 <= 6'd0;
|
6019 |
|
|
vqet0 <= 6'd0;
|
6020 |
|
|
vqe1 <= 6'd0;
|
6021 |
|
|
vqet1 <= 6'd0;
|
6022 |
|
|
vl <= 7'd62;
|
6023 |
|
|
for (n = 0; n < 8; n = n + 1)
|
6024 |
|
|
vm[n] <= 64'h7FFFFFFFFFFFFFFF;
|
6025 |
|
|
nop_fetchbuf <= 4'h0;
|
6026 |
|
|
seq_num <= 5'd0;
|
6027 |
|
|
seq_num1 <= 5'd0;
|
6028 |
|
|
fcu_done <= `TRUE;
|
6029 |
|
|
sema <= 64'h0;
|
6030 |
|
|
tvec[0] <= RSTPC;
|
6031 |
49 |
robfinch |
pmr <= 64'hFFFFFFFFFFFFFFFF;
|
6032 |
|
|
pmr[0] <= `ID1_AVAIL;
|
6033 |
|
|
pmr[1] <= `ID2_AVAIL;
|
6034 |
|
|
pmr[2] <= `ID3_AVAIL;
|
6035 |
|
|
pmr[8] <= `ALU0_AVAIL;
|
6036 |
|
|
pmr[9] <= `ALU1_AVAIL;
|
6037 |
|
|
pmr[16] <= `FPU1_AVAIL;
|
6038 |
|
|
pmr[17] <= `FPU2_AVAIL;
|
6039 |
|
|
pmr[24] <= `MEM1_AVAIL;
|
6040 |
|
|
pmr[25] <= `MEM2_AVAIL;
|
6041 |
|
|
pmr[26] <= `MEM3_AVAIL;
|
6042 |
|
|
pmr[32] <= `FCU_AVAIL;
|
6043 |
|
|
for (n = 0; n < `WB_DEPTH; n = n + 1) begin
|
6044 |
|
|
wb_v[n] <= 1'b0;
|
6045 |
|
|
wb_rmw[n] <= 1'b0;
|
6046 |
|
|
wb_id[n] <= {QENTRIES{1'b0}};
|
6047 |
|
|
end
|
6048 |
|
|
wb_en <= `TRUE;
|
6049 |
|
|
wbo_id <= {QENTRIES{1'b0}};
|
6050 |
|
|
`ifdef SIM
|
6051 |
|
|
wb_merges <= 32'd0;
|
6052 |
|
|
`endif
|
6053 |
48 |
robfinch |
end
|
6054 |
|
|
else begin
|
6055 |
49 |
robfinch |
if (|fb_panic)
|
6056 |
|
|
panic <= fb_panic;
|
6057 |
|
|
begin
|
6058 |
|
|
branchmiss <= excmiss|fcu_branchmiss;
|
6059 |
51 |
robfinch |
misspc <= excmiss ? excmisspc : fcu_misspc;
|
6060 |
|
|
missid <= excmiss ? (|iqentry_exc[head0] ? head0 : head1) : fcu_sourceid;
|
6061 |
49 |
robfinch |
branchmiss_thrd <= excmiss ? excthrd : fcu_thrd;
|
6062 |
|
|
end
|
6063 |
48 |
robfinch |
// The following signals only pulse
|
6064 |
|
|
|
6065 |
|
|
// Instruction decode output should only pulse once for a queue entry. We
|
6066 |
|
|
// want the decode to be invalidated after a clock cycle so that it isn't
|
6067 |
|
|
// inadvertently used to update the queue at a later point.
|
6068 |
|
|
id1_vi <= `INV;
|
6069 |
49 |
robfinch |
if (`NUM_IDU > 1)
|
6070 |
|
|
id2_vi <= `INV;
|
6071 |
|
|
if (`NUM_IDU > 2)
|
6072 |
|
|
id3_vi <= `INV;
|
6073 |
|
|
if (iqentry_v[nid] && iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]])
|
6074 |
|
|
fcu_dataready <= `INV;
|
6075 |
48 |
robfinch |
ld_time <= {ld_time[4:0],1'b0};
|
6076 |
|
|
wc_times <= wc_time;
|
6077 |
|
|
rf_vra0 <= regIsValid[Ra0s];
|
6078 |
|
|
rf_vra1 <= regIsValid[Ra1s];
|
6079 |
|
|
if (vqe0 >= vl) begin
|
6080 |
|
|
vqe0 <= 6'd0;
|
6081 |
|
|
vqet0 <= 6'h0;
|
6082 |
|
|
end
|
6083 |
|
|
if (vqe1 >= vl) begin
|
6084 |
|
|
vqe1 <= 6'd0;
|
6085 |
|
|
vqet1 <= 6'h0;
|
6086 |
|
|
end
|
6087 |
|
|
// Turn off vector chaining indicator when chained instructions are done.
|
6088 |
|
|
if ((vqe0 >= vl || vqe0==6'd0) && (vqe1 >= vl || vqe1==6'd0))
|
6089 |
|
|
`ifdef SUPPORT_SMT
|
6090 |
|
|
mstatus[0][32] <= 1'b0;
|
6091 |
|
|
`else
|
6092 |
|
|
mstatus[32] <= 1'b0;
|
6093 |
|
|
`endif
|
6094 |
|
|
|
6095 |
|
|
nop_fetchbuf <= 4'h0;
|
6096 |
|
|
excmiss <= FALSE;
|
6097 |
|
|
invic <= FALSE;
|
6098 |
|
|
tick <= tick + 64'd1;
|
6099 |
|
|
alu0_ld <= FALSE;
|
6100 |
|
|
alu1_ld <= FALSE;
|
6101 |
49 |
robfinch |
fpu1_ld <= FALSE;
|
6102 |
|
|
fpu2_ld <= FALSE;
|
6103 |
48 |
robfinch |
fcu_ld <= FALSE;
|
6104 |
|
|
dramA_v <= FALSE;
|
6105 |
|
|
dramB_v <= FALSE;
|
6106 |
|
|
dramC_v <= FALSE;
|
6107 |
|
|
cr0[17] <= 1'b0;
|
6108 |
|
|
if (waitctr != 64'd0)
|
6109 |
|
|
waitctr <= waitctr - 64'd1;
|
6110 |
|
|
|
6111 |
|
|
|
6112 |
50 |
robfinch |
if (iqentry_fc[fcu_id[`QBITS]] && iqentry_v[fcu_id[`QBITS]] && !iqentry_done[fcu_id[`QBITS]] && iqentry_out[fcu_id[`QBITS]])
|
6113 |
48 |
robfinch |
fcu_timeout <= fcu_timeout + 8'd1;
|
6114 |
|
|
|
6115 |
|
|
if (branchmiss) begin
|
6116 |
|
|
for (n = 1; n < PREGS; n = n + 1)
|
6117 |
|
|
if (~livetarget[n]) begin
|
6118 |
|
|
if (branchmiss_thrd) begin
|
6119 |
|
|
if (n >= 128)
|
6120 |
|
|
rf_v[n] <= `VAL;
|
6121 |
|
|
end
|
6122 |
|
|
else begin
|
6123 |
|
|
if (n < 128)
|
6124 |
|
|
rf_v[n] <= `VAL;
|
6125 |
|
|
end
|
6126 |
|
|
end
|
6127 |
|
|
|
6128 |
|
|
if (|iqentry_0_latestID) if (iqentry_thrd[0]==branchmiss_thrd) rf_source[ {iqentry_tgt[0][7:0]} ] <= { 1'b0, iqentry_mem[0], 3'd0 };
|
6129 |
|
|
if (|iqentry_1_latestID) if (iqentry_thrd[1]==branchmiss_thrd) rf_source[ {iqentry_tgt[1][7:0]} ] <= { 1'b0, iqentry_mem[1], 3'd1 };
|
6130 |
|
|
if (|iqentry_2_latestID) if (iqentry_thrd[2]==branchmiss_thrd) rf_source[ {iqentry_tgt[2][7:0]} ] <= { 1'b0, iqentry_mem[2], 3'd2 };
|
6131 |
|
|
if (|iqentry_3_latestID) if (iqentry_thrd[3]==branchmiss_thrd) rf_source[ {iqentry_tgt[3][7:0]} ] <= { 1'b0, iqentry_mem[3], 3'd3 };
|
6132 |
|
|
if (|iqentry_4_latestID) if (iqentry_thrd[4]==branchmiss_thrd) rf_source[ {iqentry_tgt[4][7:0]} ] <= { 1'b0, iqentry_mem[4], 3'd4 };
|
6133 |
|
|
if (|iqentry_5_latestID) if (iqentry_thrd[5]==branchmiss_thrd) rf_source[ {iqentry_tgt[5][7:0]} ] <= { 1'b0, iqentry_mem[5], 3'd5 };
|
6134 |
|
|
if (|iqentry_6_latestID) if (iqentry_thrd[6]==branchmiss_thrd) rf_source[ {iqentry_tgt[6][7:0]} ] <= { 1'b0, iqentry_mem[6], 3'd6 };
|
6135 |
|
|
if (|iqentry_7_latestID) if (iqentry_thrd[7]==branchmiss_thrd) rf_source[ {iqentry_tgt[7][7:0]} ] <= { 1'b0, iqentry_mem[7], 3'd7 };
|
6136 |
|
|
|
6137 |
|
|
end
|
6138 |
|
|
|
6139 |
|
|
// The source for the register file data might have changed since it was
|
6140 |
|
|
// placed on the commit bus. So it's needed to check that the source is
|
6141 |
|
|
// still as expected to validate the register.
|
6142 |
|
|
if (commit0_v) begin
|
6143 |
|
|
if (!rf_v[ {commit0_tgt[7:0]} ])
|
6144 |
|
|
// rf_v[ {commit0_tgt[7:0]} ] <= rf_source[ commit0_tgt[7:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]);
|
6145 |
|
|
rf_v[ {commit0_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}];//rf_source[ commit0_tgt[4:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]);
|
6146 |
|
|
if (commit0_tgt[5:0] != 6'd0) $display("r%d <- %h v[%d]<-%d", commit0_tgt, commit0_bus, regIsValid[commit0_tgt[5:0]],
|
6147 |
|
|
rf_source[ {commit0_tgt[7:0]} ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]));
|
6148 |
|
|
if (commit0_tgt[5:0]==6'd30 && commit0_bus==64'd0)
|
6149 |
|
|
$display("FP <= 0");
|
6150 |
|
|
end
|
6151 |
49 |
robfinch |
if (commit1_v && `NUM_CMT > 1) begin
|
6152 |
48 |
robfinch |
if (!rf_v[ {commit1_tgt[7:0]} ]) begin
|
6153 |
|
|
if ({commit1_tgt[7:0]}=={commit0_tgt[7:0]})
|
6154 |
|
|
rf_v[ {commit1_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit1_tgt[7:0]}];
|
6155 |
|
|
/*
|
6156 |
|
|
(rf_source[ commit0_tgt[4:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ])) ||
|
6157 |
|
|
(rf_source[ commit1_tgt[4:0] ] == commit1_id || (branchmiss && iqentry_source[ commit1_id[`QBITS] ]));
|
6158 |
|
|
*/
|
6159 |
|
|
else
|
6160 |
|
|
rf_v[ {commit1_tgt[7:0]} ] <= regIsValid[{commit1_tgt[7:0]}];//rf_source[ commit1_tgt[4:0] ] == commit1_id || (branchmiss && iqentry_source[ commit1_id[`QBITS] ]);
|
6161 |
|
|
end
|
6162 |
|
|
if (commit1_tgt[5:0] != 6'd0) $display("r%d <- %h v[%d]<-%d", commit1_tgt, commit1_bus, regIsValid[commit1_tgt[5:0]],
|
6163 |
|
|
rf_source[ {commit1_tgt[7:0]} ] == commit1_id || (branchmiss && iqentry_source[ commit1_id[`QBITS] ]));
|
6164 |
|
|
if (commit1_tgt[5:0]==6'd30 && commit1_bus==64'd0)
|
6165 |
|
|
$display("FP <= 0");
|
6166 |
|
|
end
|
6167 |
|
|
rf_v[0] <= 1;
|
6168 |
|
|
|
6169 |
49 |
robfinch |
//
|
6170 |
|
|
// ENQUEUE
|
6171 |
|
|
//
|
6172 |
|
|
// place up to two instructions from the fetch buffer into slots in the IQ.
|
6173 |
|
|
// note: they are placed in-order, and they are expected to be executed
|
6174 |
|
|
// 0, 1, or 2 of the fetch buffers may have valid data
|
6175 |
|
|
// 0, 1, or 2 slots in the instruction queue may be available.
|
6176 |
|
|
// if we notice that one of the instructions in the fetch buffer is a predicted branch,
|
6177 |
|
|
// (set branchback/backpc and delete any instructions after it in fetchbuf)
|
6178 |
|
|
//
|
6179 |
48 |
robfinch |
|
6180 |
|
|
// enqueue fetchbuf0 and fetchbuf1, but only if there is room,
|
6181 |
|
|
// and ignore fetchbuf1 if fetchbuf0 has a backwards branch in it.
|
6182 |
|
|
//
|
6183 |
|
|
// also, do some instruction-decode ... set the operand_valid bits in the IQ
|
6184 |
|
|
// appropriately so that the DATAINCOMING stage does not have to look at the opcode
|
6185 |
|
|
//
|
6186 |
|
|
if (!branchmiss) // don't bother doing anything if there's been a branch miss
|
6187 |
|
|
|
6188 |
|
|
case ({fetchbuf0_v, fetchbuf1_v})
|
6189 |
|
|
|
6190 |
|
|
2'b00: ; // do nothing
|
6191 |
|
|
|
6192 |
|
|
2'b01:
|
6193 |
|
|
if (canq1) begin
|
6194 |
|
|
if (IsVector(fetchbuf1_instr) && SUP_VECTOR) begin
|
6195 |
|
|
vqe1 <= vqe1 + 4'd1;
|
6196 |
|
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
6197 |
|
|
if (vm[fetchbuf1_instr[25:23]][vqe1])
|
6198 |
|
|
vqet1 <= vqet1 + 4'd1;
|
6199 |
|
|
end
|
6200 |
|
|
else
|
6201 |
|
|
vqet1 <= vqet1 + 4'd1;
|
6202 |
|
|
if (vqe1 >= vl-2)
|
6203 |
|
|
nop_fetchbuf <= fetchbuf ? 4'b0100 : 4'b0001;
|
6204 |
|
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, vqe1);
|
6205 |
|
|
if (fetchbuf1_thrd)
|
6206 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6207 |
|
|
else
|
6208 |
|
|
seq_num <= seq_num + 5'd1;
|
6209 |
|
|
tgtq <= FALSE;
|
6210 |
|
|
if (fetchbuf1_rfw) begin
|
6211 |
|
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
6212 |
|
|
rf_v [Rt1s] <= `INV;
|
6213 |
|
|
end
|
6214 |
|
|
if (canq2 && vqe1 < vl-2) begin
|
6215 |
|
|
vqe1 <= vqe1 + 4'd2;
|
6216 |
|
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
6217 |
|
|
if (vm[fetchbuf1_instr[25:23]][vqe1+6'd1])
|
6218 |
|
|
vqet1 <= vqet1 + 4'd2;
|
6219 |
|
|
end
|
6220 |
|
|
else
|
6221 |
|
|
vqet1 <= vqet1 + 4'd2;
|
6222 |
|
|
enque1(tail1, fetchbuf1_thrd ? seq_num1 + 5'd1 : seq_num + 5'd1, vqe1 + 6'd1);
|
6223 |
|
|
if (fetchbuf1_thrd)
|
6224 |
|
|
seq_num1 <= seq_num1 + 5'd2;
|
6225 |
|
|
else
|
6226 |
|
|
seq_num <= seq_num + 5'd2;
|
6227 |
|
|
tgtq <= FALSE;
|
6228 |
|
|
if (fetchbuf1_rfw) begin
|
6229 |
|
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail1 }; // top bit indicates ALU/MEM bus
|
6230 |
|
|
rf_v [Rt1s] <= `INV;
|
6231 |
|
|
end
|
6232 |
|
|
end
|
6233 |
|
|
end
|
6234 |
|
|
else begin
|
6235 |
|
|
enque1(tail0, fetchbuf1_thrd ? seq_num1 : seq_num, 6'd0);
|
6236 |
|
|
if (fetchbuf1_thrd)
|
6237 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6238 |
|
|
else
|
6239 |
|
|
seq_num <= seq_num + 5'd1;
|
6240 |
|
|
tgtq <= FALSE;
|
6241 |
|
|
if (fetchbuf1_rfw) begin
|
6242 |
|
|
rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_memld, tail0 }; // top bit indicates ALU/MEM bus
|
6243 |
|
|
rf_v [Rt1s] <= `INV;
|
6244 |
|
|
end
|
6245 |
|
|
end
|
6246 |
|
|
end
|
6247 |
|
|
|
6248 |
|
|
2'b10:
|
6249 |
|
|
if (canq1) begin
|
6250 |
|
|
// $display("queued1: %d", queued1);
|
6251 |
|
|
// if (!IsBranch(fetchbuf0_instr)) panic <= `PANIC_FETCHBUFBEQ;
|
6252 |
|
|
// if (!predict_taken0) panic <= `PANIC_FETCHBUFBEQ;
|
6253 |
|
|
//
|
6254 |
|
|
// this should only happen when the first instruction is a BEQ-backwards and the IQ
|
6255 |
|
|
// happened to be full on the previous cycle (thus we deleted fetchbuf1 but did not
|
6256 |
|
|
// enqueue fetchbuf0) ... probably no need to check for LW -- sanity check, just in case
|
6257 |
|
|
//
|
6258 |
|
|
if (IsVector(fetchbuf0_instr) && SUP_VECTOR) begin
|
6259 |
|
|
vqe0 <= vqe0 + 4'd1;
|
6260 |
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
6261 |
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0])
|
6262 |
|
|
vqet0 <= vqet0 + 4'd1;
|
6263 |
|
|
end
|
6264 |
|
|
else
|
6265 |
|
|
vqet0 <= vqet0 + 4'd1;
|
6266 |
|
|
if (vqe0 >= vl-2)
|
6267 |
|
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
6268 |
|
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, vqe0);
|
6269 |
|
|
if (fetchbuf0_thrd)
|
6270 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6271 |
|
|
else
|
6272 |
|
|
seq_num <= seq_num + 5'd1;
|
6273 |
|
|
tgtq <= FALSE;
|
6274 |
|
|
if (fetchbuf0_rfw) begin
|
6275 |
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail0 }; // top bit indicates ALU/MEM bus
|
6276 |
|
|
rf_v[Rt0s] <= `INV;
|
6277 |
|
|
end
|
6278 |
|
|
if (canq2) begin
|
6279 |
|
|
if (vqe0 < vl-2) begin
|
6280 |
|
|
vqe0 <= vqe0 + 4'd2;
|
6281 |
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
6282 |
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0+6'd1])
|
6283 |
|
|
vqet0 <= vqet0 + 4'd2;
|
6284 |
|
|
end
|
6285 |
|
|
else
|
6286 |
|
|
vqet0 <= vqet0 + 4'd2;
|
6287 |
|
|
enque0(tail1, fetchbuf0_thrd ? seq_num1 + 5'd1 : seq_num+5'd1, vqe0 + 6'd1);
|
6288 |
|
|
if (fetchbuf0_thrd)
|
6289 |
|
|
seq_num1 <= seq_num1 + 5'd2;
|
6290 |
|
|
else
|
6291 |
|
|
seq_num <= seq_num + 5'd2;
|
6292 |
|
|
tgtq <= FALSE;
|
6293 |
|
|
if (fetchbuf0_rfw) begin
|
6294 |
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail1 }; // top bit indicates ALU/MEM bus
|
6295 |
|
|
rf_v[Rt0s] <= `INV;
|
6296 |
|
|
end
|
6297 |
|
|
end
|
6298 |
|
|
end
|
6299 |
|
|
end
|
6300 |
|
|
else begin
|
6301 |
|
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, 6'd0);
|
6302 |
|
|
if (fetchbuf0_thrd)
|
6303 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6304 |
|
|
else
|
6305 |
|
|
seq_num <= seq_num + 5'd1;
|
6306 |
|
|
tgtq <= FALSE;
|
6307 |
|
|
if (fetchbuf0_rfw) begin
|
6308 |
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail0 }; // top bit indicates ALU/MEM bus
|
6309 |
|
|
rf_v[Rt0s] <= `INV;
|
6310 |
|
|
end
|
6311 |
|
|
end
|
6312 |
|
|
end
|
6313 |
|
|
|
6314 |
|
|
2'b11:
|
6315 |
|
|
if (canq1) begin
|
6316 |
|
|
//
|
6317 |
|
|
// if the first instruction is a predicted branch, enqueue it & stomp on all following instructions
|
6318 |
|
|
// but only if the following instruction is in the same thread. Otherwise we want to queue two.
|
6319 |
|
|
//
|
6320 |
|
|
if (take_branch0 && fetchbuf1_thrd==fetchbuf0_thrd) begin
|
6321 |
|
|
tgtq <= FALSE;
|
6322 |
|
|
enque0(tail0,fetchbuf0_thrd ? seq_num1 : seq_num,6'd0);
|
6323 |
|
|
if (fetchbuf0_thrd)
|
6324 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6325 |
|
|
else
|
6326 |
|
|
seq_num <= seq_num + 5'd1;
|
6327 |
|
|
if (fetchbuf0_rfw) begin
|
6328 |
|
|
rf_source[ Rt0s ] <= {1'b0,fetchbuf0_memld, tail0};
|
6329 |
|
|
rf_v [ Rt0s ] <= `INV;
|
6330 |
|
|
end
|
6331 |
|
|
end
|
6332 |
|
|
|
6333 |
|
|
else begin // fetchbuf0 doesn't contain a predicted branch
|
6334 |
|
|
//
|
6335 |
|
|
// so -- we can enqueue 1 or 2 instructions, depending on space in the IQ
|
6336 |
|
|
// update the rf_v and rf_source bits separately (at end)
|
6337 |
|
|
// the problem is that if we do have two instructions,
|
6338 |
|
|
// they may interact with each other, so we have to be
|
6339 |
|
|
// careful about where things point.
|
6340 |
|
|
//
|
6341 |
|
|
// enqueue the first instruction ...
|
6342 |
|
|
//
|
6343 |
|
|
if (IsVector(fetchbuf0_instr) && SUP_VECTOR) begin
|
6344 |
|
|
vqe0 <= vqe0 + 4'd1;
|
6345 |
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
6346 |
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0])
|
6347 |
|
|
vqet0 <= vqet0 + 4'd1;
|
6348 |
|
|
end
|
6349 |
|
|
else
|
6350 |
|
|
vqet0 <= vqet0 + 4'd1;
|
6351 |
|
|
if (vqe0 >= vl-2)
|
6352 |
|
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
6353 |
|
|
end
|
6354 |
|
|
tgtq <= FALSE;
|
6355 |
|
|
if (vqe0 < vl || !IsVector(fetchbuf0_instr)) begin
|
6356 |
|
|
enque0(tail0, fetchbuf0_thrd ? seq_num1 : seq_num, vqe0);
|
6357 |
|
|
if (fetchbuf0_thrd)
|
6358 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6359 |
|
|
else
|
6360 |
|
|
seq_num <= seq_num + 5'd1;
|
6361 |
|
|
//
|
6362 |
|
|
// if there is room for a second instruction, enqueue it
|
6363 |
|
|
//
|
6364 |
|
|
if (canq2) begin
|
6365 |
|
|
if (vechain && IsVector(fetchbuf1_instr)
|
6366 |
|
|
&& Ra1s != Rt0s // And there is no dependency
|
6367 |
|
|
&& Rb1s != Rt0s
|
6368 |
|
|
&& Rc1s != Rt0s
|
6369 |
|
|
) begin
|
6370 |
|
|
`ifdef SUPPORT_SMT
|
6371 |
|
|
mstatus[0][32] <= 1'b1;
|
6372 |
|
|
`else
|
6373 |
|
|
mstatus[32] <= 1'b1;
|
6374 |
|
|
`endif
|
6375 |
|
|
vqe1 <= vqe1 + 4'd1;
|
6376 |
|
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
6377 |
|
|
if (vm[fetchbuf1_instr[25:23]][vqe1])
|
6378 |
|
|
vqet1 <= vqet1 + 4'd1;
|
6379 |
|
|
end
|
6380 |
|
|
else
|
6381 |
|
|
vqet1 <= vqet1 + 4'd1;
|
6382 |
|
|
if (vqe1 >= vl-2)
|
6383 |
|
|
nop_fetchbuf <= fetchbuf ? 4'b0100 : 4'b0001;
|
6384 |
|
|
enque1(tail1,
|
6385 |
|
|
fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b1 ? seq_num1 + 5'd1 :
|
6386 |
|
|
fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b0 ? seq_num + 5'd1 :
|
6387 |
|
|
fetchbuf1_thrd ? seq_num1 + 5'd1: seq_num + 5'd1, 6'd0);
|
6388 |
|
|
if (fetchbuf1_thrd==fetchbuf0_thrd) begin
|
6389 |
|
|
if (fetchbuf1_thrd)
|
6390 |
|
|
seq_num1 <= seq_num1 + 5'd2;
|
6391 |
|
|
else
|
6392 |
|
|
seq_num <= seq_num + 5'd2;
|
6393 |
|
|
end
|
6394 |
|
|
else begin
|
6395 |
|
|
if (fetchbuf1_thrd)
|
6396 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6397 |
|
|
else
|
6398 |
|
|
seq_num <= seq_num + 5'd1;
|
6399 |
|
|
end
|
6400 |
|
|
|
6401 |
|
|
// SOURCE 1 ...
|
6402 |
|
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
6403 |
|
|
if (~fetchbuf0_rfw) begin
|
6404 |
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
6405 |
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
6406 |
|
|
end
|
6407 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6408 |
|
|
else if (Ra1 == Rt0) begin
|
6409 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6410 |
|
|
iqentry_a1_v [tail1] <= `INV;
|
6411 |
|
|
iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
6412 |
|
|
end
|
6413 |
|
|
// if no overlap, get info from rf_v and rf_source
|
6414 |
|
|
else begin
|
6415 |
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
6416 |
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
6417 |
|
|
end
|
6418 |
|
|
|
6419 |
|
|
// SOURCE 2 ...
|
6420 |
|
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
6421 |
|
|
if (~fetchbuf0_rfw) begin
|
6422 |
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
6423 |
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
6424 |
|
|
end
|
6425 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6426 |
|
|
else if (Rb1s == Rt0s) begin
|
6427 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6428 |
|
|
iqentry_a2_v [tail1] <= `INV;
|
6429 |
|
|
iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
6430 |
|
|
end
|
6431 |
|
|
// if no overlap, get info from rf_v and rf_source
|
6432 |
|
|
else begin
|
6433 |
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
6434 |
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
6435 |
|
|
end
|
6436 |
|
|
|
6437 |
|
|
// SOURCE 3 ...
|
6438 |
|
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
6439 |
|
|
if (~fetchbuf0_rfw) begin
|
6440 |
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
6441 |
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
6442 |
|
|
end
|
6443 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6444 |
|
|
else if (Rc1 == Rt0) begin
|
6445 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6446 |
|
|
iqentry_a3_v [tail1] <= `INV;
|
6447 |
|
|
iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
6448 |
|
|
end
|
6449 |
|
|
// if no overlap, get info from rf_v and rf_source
|
6450 |
|
|
else begin
|
6451 |
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
6452 |
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
6453 |
|
|
end
|
6454 |
|
|
|
6455 |
|
|
// if the two instructions enqueued target the same register,
|
6456 |
|
|
// make sure only the second writes to rf_v and rf_source.
|
6457 |
|
|
// first is allowed to update rf_v and rf_source only if the
|
6458 |
|
|
// second has no target
|
6459 |
|
|
//
|
6460 |
|
|
if (fetchbuf0_rfw) begin
|
6461 |
|
|
rf_source[ Rt0s ] <= { 1'b0,fetchbuf0_memld, tail0 };
|
6462 |
|
|
rf_v [ Rt0s] <= `INV;
|
6463 |
|
|
end
|
6464 |
|
|
if (fetchbuf1_rfw) begin
|
6465 |
|
|
rf_source[ Rt1s ] <= { 1'b0,fetchbuf1_memld, tail1 };
|
6466 |
|
|
rf_v [ Rt1s ] <= `INV;
|
6467 |
|
|
end
|
6468 |
|
|
end
|
6469 |
|
|
// If there was a vector instruction in fetchbuf0, we really
|
6470 |
|
|
// want to queue the next vector element, not the next
|
6471 |
|
|
// instruction waiting in fetchbuf1.
|
6472 |
|
|
else if (IsVector(fetchbuf0_instr) && SUP_VECTOR && vqe0 < vl-1) begin
|
6473 |
|
|
vqe0 <= vqe0 + 4'd2;
|
6474 |
|
|
if (IsVCmprss(fetchbuf0_instr)) begin
|
6475 |
|
|
if (vm[fetchbuf0_instr[25:23]][vqe0+6'd1])
|
6476 |
|
|
vqet0 <= vqet0 + 4'd2;
|
6477 |
|
|
end
|
6478 |
|
|
else
|
6479 |
|
|
vqet0 <= vqet0 + 4'd2;
|
6480 |
|
|
if (vqe0 >= vl-3)
|
6481 |
|
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
6482 |
|
|
if (vqe0 < vl-1) begin
|
6483 |
|
|
enque0(tail1, fetchbuf0_thrd ? seq_num1 + 5'd1 : seq_num + 5'd1, vqe0 + 6'd1);
|
6484 |
|
|
if (fetchbuf0_thrd)
|
6485 |
|
|
seq_num1 <= seq_num1 + 5'd2;
|
6486 |
|
|
else
|
6487 |
|
|
seq_num <= seq_num + 5'd2;
|
6488 |
|
|
|
6489 |
|
|
// SOURCE 1 ...
|
6490 |
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra0s];
|
6491 |
|
|
iqentry_a1_s [tail1] <= rf_source [Ra0s];
|
6492 |
|
|
|
6493 |
|
|
// SOURCE 2 ...
|
6494 |
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb0s];
|
6495 |
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb0s ];
|
6496 |
|
|
|
6497 |
|
|
// SOURCE 3 ...
|
6498 |
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc0s];
|
6499 |
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc0s ];
|
6500 |
|
|
|
6501 |
|
|
// if the two instructions enqueued target the same register,
|
6502 |
|
|
// make sure only the second writes to rf_v and rf_source.
|
6503 |
|
|
// first is allowed to update rf_v and rf_source only if the
|
6504 |
|
|
// second has no target (BEQ or SW)
|
6505 |
|
|
//
|
6506 |
|
|
if (fetchbuf0_rfw) begin
|
6507 |
|
|
rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_memld, tail1 };
|
6508 |
|
|
rf_v [ Rt0s ] <= `INV;
|
6509 |
|
|
end
|
6510 |
|
|
end
|
6511 |
|
|
end
|
6512 |
|
|
else if (IsVector(fetchbuf1_instr) && SUP_VECTOR) begin
|
6513 |
|
|
vqe1 <= 6'd1;
|
6514 |
|
|
if (IsVCmprss(fetchbuf1_instr)) begin
|
6515 |
|
|
if (vm[fetchbuf1_instr[25:23]][IsVector(fetchbuf0_instr)? 6'd0:vqe1+6'd1])
|
6516 |
|
|
vqet1 <= 6'd1;
|
6517 |
|
|
else
|
6518 |
|
|
vqet1 <= 6'd0;
|
6519 |
|
|
end
|
6520 |
|
|
else
|
6521 |
|
|
vqet1 <= 6'd1;
|
6522 |
|
|
if (IsVector(fetchbuf0_instr) && SUP_VECTOR)
|
6523 |
|
|
nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
|
6524 |
|
|
enque1(tail1,
|
6525 |
|
|
fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b1 ? seq_num1 + 5'd1 :
|
6526 |
|
|
fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b0 ? seq_num + 5'd1 :
|
6527 |
|
|
fetchbuf1_thrd ? seq_num1 + 5'd1: seq_num + 5'd1, 6'd0);
|
6528 |
|
|
if (fetchbuf1_thrd==fetchbuf0_thrd) begin
|
6529 |
|
|
if (fetchbuf1_thrd)
|
6530 |
|
|
seq_num1 <= seq_num1 + 5'd2;
|
6531 |
|
|
else
|
6532 |
|
|
seq_num <= seq_num + 5'd2;
|
6533 |
|
|
end
|
6534 |
|
|
else begin
|
6535 |
|
|
if (fetchbuf1_thrd)
|
6536 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6537 |
|
|
else
|
6538 |
|
|
seq_num <= seq_num + 5'd1;
|
6539 |
|
|
end
|
6540 |
|
|
|
6541 |
|
|
// SOURCE 1 ...
|
6542 |
|
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
6543 |
|
|
if (~fetchbuf0_rfw) begin
|
6544 |
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
6545 |
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
6546 |
|
|
end
|
6547 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6548 |
|
|
else if (Ra1 == Rt0) begin
|
6549 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6550 |
|
|
iqentry_a1_v [tail1] <= `INV;
|
6551 |
|
|
iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
6552 |
|
|
end
|
6553 |
|
|
// if no overlap, get info from rf_v and rf_source
|
6554 |
|
|
else begin
|
6555 |
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
6556 |
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
6557 |
|
|
end
|
6558 |
|
|
|
6559 |
|
|
// SOURCE 2 ...
|
6560 |
|
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
6561 |
|
|
if (~fetchbuf0_rfw) begin
|
6562 |
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
6563 |
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
6564 |
|
|
end
|
6565 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6566 |
|
|
else if (Rb1s == Rt0s) begin
|
6567 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6568 |
|
|
iqentry_a2_v [tail1] <= `INV;
|
6569 |
|
|
iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
6570 |
|
|
end
|
6571 |
|
|
// if no overlap, get info from rf_v and rf_source
|
6572 |
|
|
else begin
|
6573 |
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
6574 |
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
6575 |
|
|
end
|
6576 |
|
|
|
6577 |
|
|
// SOURCE 3 ...
|
6578 |
|
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
6579 |
|
|
if (~fetchbuf0_rfw) begin
|
6580 |
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
6581 |
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
6582 |
|
|
end
|
6583 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6584 |
|
|
else if (Rc1 == Rt0) begin
|
6585 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6586 |
|
|
iqentry_a3_v [tail1] <= `INV;
|
6587 |
|
|
iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_mem &IsLoad(fetchbuf0_instr), tail0 };
|
6588 |
|
|
end
|
6589 |
|
|
// if no overlap, get info from rf_v and rf_source
|
6590 |
|
|
else begin
|
6591 |
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
6592 |
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
6593 |
|
|
end
|
6594 |
|
|
|
6595 |
|
|
// if the two instructions enqueued target the same register,
|
6596 |
|
|
// make sure only the second writes to rf_v and rf_source.
|
6597 |
|
|
// first is allowed to update rf_v and rf_source only if the
|
6598 |
|
|
// second has no target
|
6599 |
|
|
//
|
6600 |
|
|
if (fetchbuf0_rfw) begin
|
6601 |
|
|
rf_source[ Rt0s ] <= { 1'b0,fetchbuf0_memld, tail0 };
|
6602 |
|
|
rf_v [ Rt0s] <= `INV;
|
6603 |
|
|
end
|
6604 |
|
|
if (fetchbuf1_rfw) begin
|
6605 |
|
|
rf_source[ Rt1s ] <= { 1'b0,fetchbuf1_memld, tail1 };
|
6606 |
|
|
rf_v [ Rt1s ] <= `INV;
|
6607 |
|
|
end
|
6608 |
|
|
end
|
6609 |
|
|
else begin
|
6610 |
|
|
// enque1(tail1, seq_num + 5'd1, 6'd0);
|
6611 |
|
|
enque1(tail1,
|
6612 |
|
|
fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b1 ? seq_num1 + 5'd1 :
|
6613 |
|
|
fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b0 ? seq_num + 5'd1 :
|
6614 |
|
|
fetchbuf1_thrd ? seq_num1: seq_num, 6'd0);
|
6615 |
|
|
if (fetchbuf1_thrd==fetchbuf0_thrd) begin
|
6616 |
|
|
if (fetchbuf1_thrd)
|
6617 |
|
|
seq_num1 <= seq_num1 + 5'd2;
|
6618 |
|
|
else
|
6619 |
|
|
seq_num <= seq_num + 5'd2;
|
6620 |
|
|
end
|
6621 |
|
|
else begin
|
6622 |
|
|
seq_num1 <= seq_num1 + 5'd1;
|
6623 |
|
|
seq_num <= seq_num + 5'd1;
|
6624 |
|
|
end
|
6625 |
|
|
|
6626 |
|
|
// SOURCE 1 ...
|
6627 |
|
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
6628 |
|
|
if (~fetchbuf0_rfw) begin
|
6629 |
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
6630 |
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
6631 |
|
|
end
|
6632 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6633 |
|
|
else if (Ra1s == Rt0s) begin
|
6634 |
|
|
iqentry_a1_v [tail1] <= `INV;
|
6635 |
|
|
iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
6636 |
|
|
end
|
6637 |
|
|
// if no overlap, get info from regIsValid and rf_source
|
6638 |
|
|
else begin
|
6639 |
|
|
iqentry_a1_v [tail1] <= regIsValid[Ra1s];
|
6640 |
|
|
iqentry_a1_s [tail1] <= rf_source [Ra1s];
|
6641 |
|
|
end
|
6642 |
|
|
|
6643 |
|
|
// SOURCE 2 ...
|
6644 |
|
|
// if the argument is an immediate or not needed, we're done
|
6645 |
|
|
$display("Rb1s=%h, Rt0s=%h", Rb1s, Rt0s);
|
6646 |
|
|
$display("instr=%h", fetchbuf1_instr);
|
6647 |
|
|
// if previous instruction writes nothing to RF, then get info from regIsValid and rf_source
|
6648 |
|
|
if (~fetchbuf0_rfw) begin
|
6649 |
|
|
$display("fetchbuf0_rfw=0");
|
6650 |
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
6651 |
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
6652 |
|
|
end
|
6653 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6654 |
|
|
else if (Rb1s == Rt0s) begin
|
6655 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6656 |
|
|
iqentry_a2_v [tail1] <= `INV;
|
6657 |
|
|
iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
6658 |
|
|
end
|
6659 |
|
|
// if no overlap, get info from regIsValid and rf_source
|
6660 |
|
|
else begin
|
6661 |
|
|
$display("No overlap");
|
6662 |
|
|
iqentry_a2_v [tail1] <= regIsValid[Rb1s];
|
6663 |
|
|
iqentry_a2_s [tail1] <= rf_source[ Rb1s ];
|
6664 |
|
|
end
|
6665 |
|
|
|
6666 |
|
|
// SOURCE 3 ...
|
6667 |
|
|
// if previous instruction writes nothing to RF, then get info from regIsValid and rf_source
|
6668 |
|
|
if (~fetchbuf0_rfw) begin
|
6669 |
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
6670 |
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
6671 |
|
|
end
|
6672 |
|
|
// otherwise, previous instruction does write to RF ... see if overlap
|
6673 |
|
|
else if (Rc1s == Rt0s) begin
|
6674 |
|
|
// if the previous instruction is a LW, then grab result from memq, not the iq
|
6675 |
|
|
iqentry_a3_v [tail1] <= `INV;
|
6676 |
|
|
iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_memld, tail0 };
|
6677 |
|
|
end
|
6678 |
|
|
// if no overlap, get info from regIsValid and rf_source
|
6679 |
|
|
else begin
|
6680 |
|
|
iqentry_a3_v [tail1] <= regIsValid[Rc1s];
|
6681 |
|
|
iqentry_a3_s [tail1] <= rf_source[ Rc1s ];
|
6682 |
|
|
end
|
6683 |
|
|
|
6684 |
|
|
// if the two instructions enqueued target the same register,
|
6685 |
|
|
// make sure only the second writes to regIsValid and rf_source.
|
6686 |
|
|
// first is allowed to update regIsValid and rf_source only if the
|
6687 |
|
|
// second has no target (BEQ or SW)
|
6688 |
|
|
//
|
6689 |
|
|
if (fetchbuf0_rfw) begin
|
6690 |
|
|
rf_source[ Rt0s ] <= { 1'b0,fetchbuf0_memld, tail0 };
|
6691 |
|
|
rf_v [ Rt0s] <= `INV;
|
6692 |
|
|
$display("r%dx (%d) Invalidated", Rt0s, Rt0s[4:0]);
|
6693 |
|
|
end
|
6694 |
|
|
else
|
6695 |
|
|
$display("No rfw");
|
6696 |
|
|
if (fetchbuf1_rfw) begin
|
6697 |
|
|
rf_source[ Rt1s ] <= { 1'b0,fetchbuf1_memld, tail1 };
|
6698 |
|
|
$display("r%dx (%d) Invalidated", Rt1s, Rt1s[4:0]);
|
6699 |
|
|
rf_v [ Rt1s ] <= `INV;
|
6700 |
|
|
end
|
6701 |
|
|
else
|
6702 |
|
|
$display("No rfw");
|
6703 |
|
|
end
|
6704 |
|
|
|
6705 |
|
|
end // ends the "if IQ[tail1] is available" clause
|
6706 |
|
|
else begin // only first instruction was enqueued
|
6707 |
|
|
if (fetchbuf0_rfw) begin
|
6708 |
|
|
$display("r%dx (%d) Invalidated 1", Rt0s, Rt0s[4:0]);
|
6709 |
|
|
rf_source[ Rt0s ] <= {1'b0,fetchbuf0_memld, tail0};
|
6710 |
|
|
rf_v [ Rt0s ] <= `INV;
|
6711 |
|
|
end
|
6712 |
|
|
end
|
6713 |
|
|
end
|
6714 |
|
|
|
6715 |
|
|
end // ends the "else fetchbuf0 doesn't have a backwards branch" clause
|
6716 |
|
|
end
|
6717 |
|
|
endcase
|
6718 |
|
|
if (pebm) begin
|
6719 |
|
|
if (branchmiss_thrd==1'b0)
|
6720 |
|
|
seq_num <= seq_num + 5'd3;
|
6721 |
|
|
else
|
6722 |
|
|
seq_num1 <= seq_num1 + 5'd3;
|
6723 |
|
|
end
|
6724 |
|
|
|
6725 |
|
|
//
|
6726 |
|
|
// DATAINCOMING
|
6727 |
|
|
//
|
6728 |
|
|
// wait for operand/s to appear on alu busses and puts them into
|
6729 |
|
|
// the iqentry_a1 and iqentry_a2 slots (if appropriate)
|
6730 |
|
|
// as well as the appropriate iqentry_res slots (and setting valid bits)
|
6731 |
|
|
//
|
6732 |
|
|
// put results into the appropriate instruction entries
|
6733 |
|
|
//
|
6734 |
|
|
// This chunk of code has to be before the enqueue stage so that the agen bit
|
6735 |
|
|
// can be reset to zero by enqueue.
|
6736 |
|
|
// put results into the appropriate instruction entries
|
6737 |
|
|
//
|
6738 |
|
|
if (IsMul(alu0_instr)|IsDivmod(alu0_instr)|alu0_shft48) begin
|
6739 |
|
|
if (alu0_done) begin
|
6740 |
|
|
alu0_dataready <= `TRUE;
|
6741 |
|
|
end
|
6742 |
|
|
end
|
6743 |
|
|
|
6744 |
|
|
if (alu0_v) begin
|
6745 |
|
|
iqentry_tgt [ alu0_id[`QBITS] ] <= alu0_tgt;
|
6746 |
|
|
iqentry_res [ alu0_id[`QBITS] ] <= alu0_bus;
|
6747 |
|
|
iqentry_exc [ alu0_id[`QBITS] ] <= alu0_exc;
|
6748 |
|
|
iqentry_done[ alu0_id[`QBITS] ] <= !iqentry_mem[ alu0_id[`QBITS] ] && alu0_done;
|
6749 |
|
|
iqentry_cmt[ alu0_id[`QBITS] ] <= !iqentry_mem[ alu0_id[`QBITS] ] && alu0_done;
|
6750 |
|
|
iqentry_out [ alu0_id[`QBITS] ] <= `INV;
|
6751 |
|
|
iqentry_agen[ alu0_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET
|
6752 |
|
|
alu0_dataready <= FALSE;
|
6753 |
|
|
end
|
6754 |
|
|
|
6755 |
49 |
robfinch |
if (alu1_v && `NUM_ALU > 1) begin
|
6756 |
48 |
robfinch |
iqentry_tgt [ alu1_id[`QBITS] ] <= alu1_tgt;
|
6757 |
|
|
iqentry_res [ alu1_id[`QBITS] ] <= alu1_bus;
|
6758 |
|
|
iqentry_exc [ alu1_id[`QBITS] ] <= alu1_exc;
|
6759 |
|
|
iqentry_done[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done;
|
6760 |
|
|
iqentry_cmt[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done;
|
6761 |
|
|
iqentry_out [ alu1_id[`QBITS] ] <= `INV;
|
6762 |
|
|
iqentry_agen[ alu1_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET
|
6763 |
|
|
alu1_dataready <= FALSE;
|
6764 |
|
|
end
|
6765 |
|
|
|
6766 |
49 |
robfinch |
if (fpu1_v) begin
|
6767 |
51 |
robfinch |
iqentry_res [ fpu1_id[`QBITS] ] <= fpu1_bus;
|
6768 |
|
|
iqentry_a0 [ fpu1_id[`QBITS] ] <= fpu1_status;
|
6769 |
|
|
iqentry_exc [ fpu1_id[`QBITS] ] <= fpu1_exc;
|
6770 |
49 |
robfinch |
iqentry_done[ fpu1_id[`QBITS] ] <= fpu1_done;
|
6771 |
51 |
robfinch |
iqentry_cmt [ fpu1_id[`QBITS] ] <= fpu1_done;
|
6772 |
|
|
iqentry_out [ fpu1_id[`QBITS] ] <= `INV;
|
6773 |
49 |
robfinch |
fpu1_dataready <= FALSE;
|
6774 |
48 |
robfinch |
end
|
6775 |
|
|
|
6776 |
49 |
robfinch |
if (fpu2_v && `NUM_FPU > 1) begin
|
6777 |
51 |
robfinch |
iqentry_res [ fpu2_id[`QBITS] ] <= fpu2_bus;
|
6778 |
|
|
iqentry_a0 [ fpu2_id[`QBITS] ] <= fpu2_status;
|
6779 |
|
|
iqentry_exc [ fpu2_id[`QBITS] ] <= fpu2_exc;
|
6780 |
49 |
robfinch |
iqentry_done[ fpu2_id[`QBITS] ] <= fpu2_done;
|
6781 |
51 |
robfinch |
iqentry_cmt [ fpu2_id[`QBITS] ] <= fpu2_done;
|
6782 |
|
|
iqentry_out [ fpu2_id[`QBITS] ] <= `INV;
|
6783 |
49 |
robfinch |
//iqentry_agen[ fpu_id[`QBITS] ] <= `VAL; // RET
|
6784 |
|
|
fpu2_dataready <= FALSE;
|
6785 |
|
|
end
|
6786 |
|
|
|
6787 |
51 |
robfinch |
if (fcu_wr & ~fcu_done) begin
|
6788 |
|
|
fcu_done <= `TRUE;
|
6789 |
|
|
if (fcu_ld)
|
6790 |
|
|
waitctr <= fcu_argA;
|
6791 |
|
|
iqentry_res [ fcu_id[`QBITS] ] <= fcu_bus;
|
6792 |
|
|
iqentry_exc [ fcu_id[`QBITS] ] <= fcu_exc;
|
6793 |
|
|
if (IsWait(fcu_instr)) begin
|
6794 |
|
|
iqentry_done [ fcu_id[`QBITS] ] <= (waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]];
|
6795 |
|
|
iqentry_cmt [ fcu_id[`QBITS] ] <= (waitctr==64'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]];
|
6796 |
|
|
end
|
6797 |
|
|
else begin
|
6798 |
|
|
iqentry_done[ fcu_id[`QBITS] ] <= `TRUE;
|
6799 |
|
|
iqentry_cmt[ fcu_id[`QBITS] ] <= `TRUE;
|
6800 |
|
|
end
|
6801 |
|
|
// Only safe place to propagate the miss pc is a0.
|
6802 |
|
|
iqentry_a0[ fcu_id[`QBITS] ] <= fcu_misspc;
|
6803 |
|
|
// Update branch taken indicator.
|
6804 |
|
|
if (fcu_jal || fcu_ret || fcu_brk || fcu_rti) begin
|
6805 |
|
|
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
|
6806 |
|
|
end
|
6807 |
|
|
// Branch target is only updated for branch-to-register
|
6808 |
|
|
// else if (fcu_branch) begin
|
6809 |
|
|
// iqentry_bt[ fcu_id[`QBITS] ] <= fcu_takb;
|
6810 |
|
|
// end
|
6811 |
|
|
iqentry_out [ fcu_id[`QBITS] ] <= `INV;
|
6812 |
|
|
//iqentry_agen[ fcu_id[`QBITS] ] <= `VAL;//!IsRet(fcu_instr);
|
6813 |
|
|
fcu_dataready <= `VAL;
|
6814 |
48 |
robfinch |
//fcu_dataready <= fcu_branchmiss || !iqentry_agen[ fcu_id[`QBITS] ] || !(iqentry_mem[ fcu_id[`QBITS] ] && IsLoad(iqentry_instr[fcu_id[`QBITS]]));
|
6815 |
|
|
//fcu_instr[`INSTRUCTION_OP] <= fcu_branchmiss|| (!IsMem(fcu_instr) && !IsWait(fcu_instr))? `NOP : fcu_instr[`INSTRUCTION_OP]; // to clear branchmiss
|
6816 |
51 |
robfinch |
end
|
6817 |
|
|
// Clear a branch miss when target instruction is fetched.
|
6818 |
|
|
if (fcu_branchmiss) begin
|
6819 |
|
|
if ((fetchbuf0_v && fetchbuf0_pc==misspc) ||
|
6820 |
|
|
(fetchbuf1_v && fetchbuf1_pc==misspc))
|
6821 |
|
|
fcu_clearbm <= `TRUE;
|
6822 |
|
|
end
|
6823 |
|
|
|
6824 |
|
|
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ]) begin
|
6825 |
|
|
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus;
|
6826 |
|
|
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc;
|
6827 |
|
|
iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
|
6828 |
|
|
iqentry_out [ dramA_id[`QBITS] ] <= `INV;
|
6829 |
|
|
iqentry_cmt [ dramA_id[`QBITS] ] <= `VAL;
|
6830 |
|
|
iqentry_aq [ dramA_id[`QBITS] ] <= `INV;
|
6831 |
|
|
end
|
6832 |
|
|
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ]) begin
|
6833 |
|
|
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus;
|
6834 |
|
|
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc;
|
6835 |
|
|
iqentry_done[ dramB_id[`QBITS] ] <= `VAL;
|
6836 |
|
|
iqentry_out [ dramB_id[`QBITS] ] <= `INV;
|
6837 |
|
|
iqentry_cmt [ dramB_id[`QBITS] ] <= `VAL;
|
6838 |
|
|
iqentry_aq [ dramB_id[`QBITS] ] <= `INV;
|
6839 |
|
|
end
|
6840 |
|
|
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ]) begin
|
6841 |
|
|
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus;
|
6842 |
|
|
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc;
|
6843 |
|
|
iqentry_done[ dramC_id[`QBITS] ] <= `VAL;
|
6844 |
|
|
iqentry_out [ dramC_id[`QBITS] ] <= `INV;
|
6845 |
|
|
iqentry_cmt [ dramC_id[`QBITS] ] <= `VAL;
|
6846 |
|
|
iqentry_aq [ dramC_id[`QBITS] ] <= `INV;
|
6847 |
48 |
robfinch |
// if (iqentry_lptr[dram2_id[`QBITS]])
|
6848 |
|
|
// wbrcd[pcr[5:0]] <= 1'b1;
|
6849 |
51 |
robfinch |
end
|
6850 |
48 |
robfinch |
|
6851 |
|
|
//
|
6852 |
|
|
// set the IQ entry == DONE as soon as the SW is let loose to the memory system
|
6853 |
|
|
//
|
6854 |
50 |
robfinch |
if (mem1_available && dram0 == `DRAMSLOT_BUSY && dram0_store) begin
|
6855 |
48 |
robfinch |
if ((alu0_v && (dram0_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram0_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
6856 |
|
|
iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
|
6857 |
|
|
iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
6858 |
|
|
end
|
6859 |
50 |
robfinch |
if (mem2_available && `NUM_MEM > 1 && dram1 == `DRAMSLOT_BUSY && dram1_store) begin
|
6860 |
48 |
robfinch |
if ((alu0_v && (dram1_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram1_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
6861 |
|
|
iqentry_done[ dram1_id[`QBITS] ] <= `VAL;
|
6862 |
|
|
iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
6863 |
|
|
end
|
6864 |
50 |
robfinch |
if (mem3_available && `NUM_MEM > 2 && dram2 == `DRAMSLOT_BUSY && dram2_store) begin
|
6865 |
48 |
robfinch |
if ((alu0_v && (dram2_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram2_id[`QBITS] == alu1_id[`QBITS]))) panic <= `PANIC_MEMORYRACE;
|
6866 |
|
|
iqentry_done[ dram2_id[`QBITS] ] <= `VAL;
|
6867 |
|
|
iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
6868 |
|
|
end
|
6869 |
|
|
|
6870 |
|
|
//
|
6871 |
|
|
// see if anybody else wants the results ... look at lots of buses:
|
6872 |
|
|
// - fpu_bus
|
6873 |
|
|
// - alu0_bus
|
6874 |
|
|
// - alu1_bus
|
6875 |
|
|
// - fcu_bus
|
6876 |
|
|
// - dram_bus
|
6877 |
|
|
// - commit0_bus
|
6878 |
|
|
// - commit1_bus
|
6879 |
|
|
//
|
6880 |
|
|
|
6881 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
6882 |
|
|
begin
|
6883 |
49 |
robfinch |
if (`NUM_FPU > 0)
|
6884 |
|
|
setargs(n,{1'b0,fpu1_id},fpu1_v,fpu1_bus);
|
6885 |
|
|
if (`NUM_FPU > 1)
|
6886 |
|
|
setargs(n,{1'b0,fpu2_id},fpu2_v,fpu2_bus);
|
6887 |
|
|
|
6888 |
48 |
robfinch |
setargs(n,{1'b0,alu0_id},alu0_v,alu0_bus);
|
6889 |
49 |
robfinch |
if (`NUM_ALU > 1)
|
6890 |
|
|
setargs(n,{1'b0,alu1_id},alu1_v,alu1_bus);
|
6891 |
|
|
|
6892 |
48 |
robfinch |
setargs(n,{1'b0,fcu_id},fcu_wr,fcu_bus);
|
6893 |
49 |
robfinch |
|
6894 |
48 |
robfinch |
setargs(n,{1'b0,dramA_id},dramA_v,dramA_bus);
|
6895 |
49 |
robfinch |
if (`NUM_MEM > 1)
|
6896 |
|
|
setargs(n,{1'b0,dramB_id},dramB_v,dramB_bus);
|
6897 |
|
|
if (`NUM_MEM > 2)
|
6898 |
|
|
setargs(n,{1'b0,dramC_id},dramC_v,dramC_bus);
|
6899 |
|
|
|
6900 |
48 |
robfinch |
setargs(n,commit0_id,commit0_v,commit0_bus);
|
6901 |
49 |
robfinch |
if (`NUM_CMT > 1)
|
6902 |
|
|
setargs(n,commit1_id,commit1_v,commit1_bus);
|
6903 |
48 |
robfinch |
|
6904 |
|
|
setinsn(n[`QBITS],id1_ido,id1_available&id1_vo,id1_bus);
|
6905 |
49 |
robfinch |
if (`NUM_IDU > 1)
|
6906 |
|
|
setinsn(n[`QBITS],id2_ido,id2_available&id2_vo,id2_bus);
|
6907 |
|
|
if (`NUM_IDU > 2)
|
6908 |
|
|
setinsn(n[`QBITS],id3_ido,id3_available&id3_vo,id3_bus);
|
6909 |
48 |
robfinch |
end
|
6910 |
|
|
|
6911 |
|
|
//
|
6912 |
|
|
// ISSUE
|
6913 |
|
|
//
|
6914 |
|
|
// determines what instructions are ready to go, then places them
|
6915 |
|
|
// in the various ALU queues.
|
6916 |
|
|
// also invalidates instructions following a branch-miss BEQ or any JALR (STOMP logic)
|
6917 |
|
|
//
|
6918 |
|
|
|
6919 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
6920 |
|
|
if (id1_available) begin
|
6921 |
|
|
if (iqentry_id1issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
6922 |
|
|
id1_vi <= `VAL;
|
6923 |
|
|
id1_id <= n[4:0];
|
6924 |
|
|
id1_instr <= iqentry_rtop[n] ? (
|
6925 |
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
6926 |
49 |
robfinch |
`ifdef FU_BYPASS
|
6927 |
48 |
robfinch |
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
6928 |
|
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
6929 |
49 |
robfinch |
`endif
|
6930 |
48 |
robfinch |
: `NOP_INSN)
|
6931 |
|
|
: iqentry_instr[n];
|
6932 |
|
|
id1_ven <= iqentry_ven[n];
|
6933 |
|
|
id1_vl <= iqentry_vl[n];
|
6934 |
|
|
id1_thrd <= iqentry_thrd[n];
|
6935 |
|
|
id1_Rt <= iqentry_tgt[n][4:0];
|
6936 |
|
|
id1_pt <= iqentry_pt[n];
|
6937 |
|
|
end
|
6938 |
|
|
end
|
6939 |
49 |
robfinch |
if (`NUM_IDU > 1) begin
|
6940 |
48 |
robfinch |
for (n = 0; n < QENTRIES; n = n + 1)
|
6941 |
49 |
robfinch |
if (id2_available) begin
|
6942 |
|
|
if (iqentry_id2issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
6943 |
|
|
id2_vi <= `VAL;
|
6944 |
|
|
id2_id <= n[4:0];
|
6945 |
|
|
id2_instr <= iqentry_rtop[n] ? (
|
6946 |
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
6947 |
|
|
`ifdef FU_BYPASS
|
6948 |
|
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
6949 |
|
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
6950 |
|
|
`endif
|
6951 |
|
|
: `NOP_INSN)
|
6952 |
|
|
: iqentry_instr[n];
|
6953 |
|
|
id2_ven <= iqentry_ven[n];
|
6954 |
|
|
id2_vl <= iqentry_vl[n];
|
6955 |
|
|
id2_thrd <= iqentry_thrd[n];
|
6956 |
|
|
id2_Rt <= iqentry_tgt[n][4:0];
|
6957 |
|
|
id2_pt <= iqentry_pt[n];
|
6958 |
|
|
end
|
6959 |
48 |
robfinch |
end
|
6960 |
|
|
end
|
6961 |
49 |
robfinch |
if (`NUM_IDU > 2) begin
|
6962 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
6963 |
|
|
if (id3_available) begin
|
6964 |
|
|
if (iqentry_id3issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
6965 |
|
|
id3_vi <= `VAL;
|
6966 |
|
|
id3_id <= n[4:0];
|
6967 |
|
|
id3_instr <= iqentry_rtop[n] ? (
|
6968 |
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
6969 |
|
|
`ifdef FU_BYPASS
|
6970 |
|
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
6971 |
|
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
6972 |
|
|
`endif
|
6973 |
|
|
: `NOP_INSN)
|
6974 |
|
|
: iqentry_instr[n];
|
6975 |
|
|
id3_ven <= iqentry_ven[n];
|
6976 |
|
|
id3_vl <= iqentry_vl[n];
|
6977 |
|
|
id3_thrd <= iqentry_thrd[n];
|
6978 |
|
|
id3_Rt <= iqentry_tgt[n][4:0];
|
6979 |
|
|
id3_pt <= iqentry_pt[n];
|
6980 |
|
|
end
|
6981 |
|
|
end
|
6982 |
|
|
end
|
6983 |
48 |
robfinch |
|
6984 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
6985 |
|
|
if (iqentry_alu0_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
6986 |
|
|
if (alu0_available & alu0_done) begin
|
6987 |
|
|
alu0_sourceid <= n[3:0];
|
6988 |
|
|
alu0_instr <= iqentry_rtop[n] ? (
|
6989 |
49 |
robfinch |
`ifdef FU_BYPASS
|
6990 |
48 |
robfinch |
iqentry_a3_v[n] ? iqentry_a3[n]
|
6991 |
49 |
robfinch |
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
6992 |
|
|
: (iqentry_a3_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
6993 |
|
|
: alu1_bus)
|
6994 |
|
|
`else
|
6995 |
|
|
iqentry_a3[n])
|
6996 |
|
|
`endif
|
6997 |
48 |
robfinch |
: iqentry_instr[n];
|
6998 |
|
|
alu0_bt <= iqentry_bt[n];
|
6999 |
|
|
alu0_mem <= iqentry_mem[n];
|
7000 |
|
|
alu0_shft48 <= iqentry_shft48[n];
|
7001 |
|
|
alu0_pc <= iqentry_pc[n];
|
7002 |
49 |
robfinch |
alu0_argA <=
|
7003 |
|
|
`ifdef FU_BYPASS
|
7004 |
|
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
7005 |
|
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
7006 |
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7007 |
|
|
: alu1_bus;
|
7008 |
|
|
`else
|
7009 |
|
|
iqentry_a1[n];
|
7010 |
|
|
`endif
|
7011 |
48 |
robfinch |
alu0_argB <= iqentry_imm[n]
|
7012 |
|
|
? iqentry_a0[n]
|
7013 |
49 |
robfinch |
`ifdef FU_BYPASS
|
7014 |
48 |
robfinch |
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
7015 |
49 |
robfinch |
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
7016 |
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7017 |
|
|
: alu1_bus);
|
7018 |
|
|
`else
|
7019 |
|
|
: iqentry_a2[n];
|
7020 |
|
|
`endif
|
7021 |
|
|
alu0_argC <=
|
7022 |
|
|
`ifdef FU_BYPASS
|
7023 |
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
7024 |
48 |
robfinch |
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
7025 |
49 |
robfinch |
`else
|
7026 |
|
|
iqentry_a3[n];
|
7027 |
|
|
`endif
|
7028 |
48 |
robfinch |
alu0_argI <= iqentry_a0[n];
|
7029 |
|
|
alu0_tgt <= IsVeins(iqentry_instr[n]) ?
|
7030 |
49 |
robfinch |
{6'h0,1'b1,iqentry_tgt[n][4:0]} | ((
|
7031 |
|
|
iqentry_a2_v[n] ? iqentry_a2[n][5:0]
|
7032 |
48 |
robfinch |
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus[5:0]
|
7033 |
|
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus[5:0]
|
7034 |
|
|
: {4{16'h0000}})) << 6 :
|
7035 |
|
|
iqentry_tgt[n];
|
7036 |
|
|
alu0_ven <= iqentry_ven[n];
|
7037 |
|
|
alu0_thrd <= iqentry_thrd[n];
|
7038 |
|
|
alu0_dataready <= IsSingleCycle(iqentry_instr[n]);
|
7039 |
|
|
alu0_ld <= TRUE;
|
7040 |
|
|
iqentry_out[n] <= `VAL;
|
7041 |
|
|
// if it is a memory operation, this is the address-generation step ... collect result into arg1
|
7042 |
|
|
if (iqentry_mem[n]) begin
|
7043 |
|
|
iqentry_a1_v[n] <= `INV;
|
7044 |
|
|
iqentry_a1_s[n] <= n[3:0];
|
7045 |
|
|
end
|
7046 |
|
|
end
|
7047 |
|
|
end
|
7048 |
49 |
robfinch |
if (`NUM_ALU > 1) begin
|
7049 |
48 |
robfinch |
for (n = 0; n < QENTRIES; n = n + 1)
|
7050 |
|
|
if (iqentry_alu1_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
7051 |
|
|
if (alu1_available && alu1_done) begin
|
7052 |
|
|
if (iqentry_alu0[n])
|
7053 |
|
|
panic <= `PANIC_ALU0ONLY;
|
7054 |
|
|
alu1_sourceid <= n[3:0];
|
7055 |
|
|
alu1_instr <= iqentry_instr[n];
|
7056 |
|
|
alu1_bt <= iqentry_bt[n];
|
7057 |
|
|
alu1_mem <= iqentry_mem[n];
|
7058 |
|
|
alu1_shft48 <= iqentry_shft48[n];
|
7059 |
|
|
alu1_pc <= iqentry_pc[n];
|
7060 |
49 |
robfinch |
alu1_argA <=
|
7061 |
|
|
`ifdef FU_BYPASS
|
7062 |
|
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
7063 |
|
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
7064 |
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7065 |
|
|
: alu1_bus;
|
7066 |
|
|
`else
|
7067 |
|
|
iqentry_a1[n];
|
7068 |
|
|
`endif
|
7069 |
48 |
robfinch |
alu1_argB <= iqentry_imm[n]
|
7070 |
|
|
? iqentry_a0[n]
|
7071 |
49 |
robfinch |
`ifdef FU_BYPASS
|
7072 |
48 |
robfinch |
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
7073 |
49 |
robfinch |
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
7074 |
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7075 |
|
|
: alu1_bus);
|
7076 |
|
|
`else
|
7077 |
|
|
: iqentry_a2[n];
|
7078 |
|
|
`endif
|
7079 |
|
|
alu1_argC <=
|
7080 |
|
|
`ifdef FU_BYPASS
|
7081 |
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
7082 |
48 |
robfinch |
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
7083 |
49 |
robfinch |
`else
|
7084 |
|
|
iqentry_a3[n];
|
7085 |
|
|
`endif
|
7086 |
48 |
robfinch |
alu1_argI <= iqentry_a0[n];
|
7087 |
|
|
alu1_tgt <= IsVeins(iqentry_instr[n]) ?
|
7088 |
|
|
{6'h0,1'b1,iqentry_tgt[n][4:0]} | ((iqentry_a2_v[n] ? iqentry_a2[n][5:0]
|
7089 |
|
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus[5:0]
|
7090 |
|
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus[5:0]
|
7091 |
|
|
: {4{16'h0000}})) << 6 :
|
7092 |
|
|
iqentry_tgt[n];
|
7093 |
|
|
alu1_ven <= iqentry_ven[n];
|
7094 |
|
|
alu1_dataready <= IsSingleCycle(iqentry_instr[n]);
|
7095 |
|
|
alu1_ld <= TRUE;
|
7096 |
|
|
iqentry_out[n] <= `VAL;
|
7097 |
|
|
// if it is a memory operation, this is the address-generation step ... collect result into arg1
|
7098 |
|
|
if (iqentry_mem[n]) begin
|
7099 |
|
|
iqentry_a1_v[n] <= `INV;
|
7100 |
|
|
iqentry_a1_s[n] <= n[3:0];
|
7101 |
|
|
end
|
7102 |
|
|
end
|
7103 |
|
|
end
|
7104 |
49 |
robfinch |
end
|
7105 |
48 |
robfinch |
|
7106 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
7107 |
49 |
robfinch |
if (iqentry_fpu1_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
7108 |
|
|
if (fpu1_available & fpu1_done) begin
|
7109 |
|
|
fpu1_sourceid <= n[3:0];
|
7110 |
|
|
fpu1_instr <= iqentry_instr[n];
|
7111 |
|
|
fpu1_pc <= iqentry_pc[n];
|
7112 |
|
|
fpu1_argA <=
|
7113 |
|
|
`ifdef FU_BYPASS
|
7114 |
|
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
7115 |
|
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
7116 |
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7117 |
|
|
: alu1_bus;
|
7118 |
|
|
`else
|
7119 |
|
|
iqentry_a1[n];
|
7120 |
|
|
`endif
|
7121 |
|
|
fpu1_argB <=
|
7122 |
|
|
`ifdef FU_BYPASS
|
7123 |
|
|
(iqentry_a2_v[n] ? iqentry_a2[n]
|
7124 |
|
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
7125 |
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7126 |
|
|
: alu1_bus);
|
7127 |
|
|
`else
|
7128 |
|
|
iqentry_a2[n];
|
7129 |
|
|
`endif
|
7130 |
|
|
fpu1_argC <=
|
7131 |
|
|
`ifdef FU_BYPASS
|
7132 |
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
7133 |
48 |
robfinch |
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
7134 |
49 |
robfinch |
`else
|
7135 |
|
|
iqentry_a3[n];
|
7136 |
|
|
`endif
|
7137 |
|
|
fpu1_argI <= iqentry_a0[n];
|
7138 |
|
|
fpu1_dataready <= `VAL;
|
7139 |
|
|
fpu1_ld <= TRUE;
|
7140 |
48 |
robfinch |
iqentry_out[n] <= `VAL;
|
7141 |
|
|
end
|
7142 |
|
|
end
|
7143 |
|
|
|
7144 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
7145 |
49 |
robfinch |
if (`NUM_FPU > 1 && iqentry_fpu2_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
7146 |
|
|
if (fpu2_available & fpu2_done) begin
|
7147 |
|
|
fpu2_sourceid <= n[3:0];
|
7148 |
|
|
fpu2_instr <= iqentry_instr[n];
|
7149 |
|
|
fpu2_pc <= iqentry_pc[n];
|
7150 |
|
|
fpu2_argA <=
|
7151 |
|
|
`ifdef FU_BYPASS
|
7152 |
|
|
iqentry_a1_v[n] ? iqentry_a1[n]
|
7153 |
|
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
7154 |
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7155 |
|
|
: alu1_bus;
|
7156 |
|
|
`else
|
7157 |
|
|
iqentry_a1[n];
|
7158 |
|
|
`endif
|
7159 |
|
|
fpu2_argB <=
|
7160 |
|
|
`ifdef FU_BYPASS
|
7161 |
|
|
(iqentry_a2_v[n] ? iqentry_a2[n]
|
7162 |
|
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
7163 |
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7164 |
|
|
: alu1_bus);
|
7165 |
|
|
`else
|
7166 |
|
|
iqentry_a2[n];
|
7167 |
|
|
`endif
|
7168 |
|
|
fpu2_argC <=
|
7169 |
|
|
`ifdef FU_BYPASS
|
7170 |
|
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
7171 |
|
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
7172 |
|
|
`else
|
7173 |
|
|
iqentry_a3[n];
|
7174 |
|
|
`endif
|
7175 |
|
|
fpu2_argI <= iqentry_a0[n];
|
7176 |
|
|
fpu2_dataready <= `VAL;
|
7177 |
|
|
fpu2_ld <= TRUE;
|
7178 |
|
|
iqentry_out[n] <= `VAL;
|
7179 |
|
|
end
|
7180 |
|
|
end
|
7181 |
|
|
|
7182 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
7183 |
48 |
robfinch |
if (iqentry_fcu_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
|
7184 |
|
|
if (fcu_done) begin
|
7185 |
|
|
fcu_sourceid <= n[3:0];
|
7186 |
|
|
fcu_instr <= iqentry_instr[n];
|
7187 |
|
|
fcu_insln <= iqentry_insln[n];
|
7188 |
|
|
fcu_pc <= iqentry_pc[n];
|
7189 |
|
|
fcu_nextpc <= iqentry_pc[n] + iqentry_insln[n];
|
7190 |
|
|
fcu_brdisp <= {{52{iqentry_instr[n][31]}},iqentry_instr[n][31:21],1'b0};
|
7191 |
51 |
robfinch |
fcu_branch <= iqentry_br[n];
|
7192 |
|
|
fcu_call <= IsCall(iqentry_instr[n])|iqentry_jal[n];
|
7193 |
|
|
fcu_jal <= iqentry_jal[n];
|
7194 |
|
|
fcu_ret <= iqentry_ret[n];
|
7195 |
|
|
fcu_brk <= iqentry_brk[n];
|
7196 |
|
|
fcu_rti <= iqentry_rti[n];
|
7197 |
48 |
robfinch |
fcu_bt <= iqentry_bt[n];
|
7198 |
|
|
fcu_pc <= iqentry_pc[n];
|
7199 |
|
|
fcu_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
7200 |
49 |
robfinch |
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
7201 |
|
|
: (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7202 |
|
|
: alu1_bus;
|
7203 |
48 |
robfinch |
`ifdef SUPPORT_SMT
|
7204 |
51 |
robfinch |
fcu_argB <= iqentry_rti[n] ? epc0[iqentry_thrd[n]]
|
7205 |
48 |
robfinch |
`else
|
7206 |
51 |
robfinch |
fcu_argB <= iqentry_rti[n] ? epc0
|
7207 |
48 |
robfinch |
`endif
|
7208 |
|
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
7209 |
49 |
robfinch |
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
7210 |
|
|
: (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? fpu1_bus
|
7211 |
|
|
: alu1_bus);
|
7212 |
48 |
robfinch |
waitctr <= iqentry_imm[n]
|
7213 |
|
|
? iqentry_a0[n]
|
7214 |
|
|
: (iqentry_a2_v[n] ? iqentry_a2[n]
|
7215 |
|
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus : alu1_bus);
|
7216 |
|
|
fcu_argC <= iqentry_a3_v[n] ? iqentry_a3[n]
|
7217 |
|
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus : alu1_bus;
|
7218 |
|
|
fcu_argI <= iqentry_a0[n];
|
7219 |
|
|
fcu_thrd <= iqentry_thrd[n];
|
7220 |
|
|
fcu_dataready <= `VAL;
|
7221 |
|
|
fcu_clearbm <= `FALSE;
|
7222 |
|
|
fcu_ld <= TRUE;
|
7223 |
|
|
fcu_timeout <= 8'h00;
|
7224 |
|
|
iqentry_out[n] <= `VAL;
|
7225 |
|
|
fcu_done <= `FALSE;
|
7226 |
|
|
end
|
7227 |
|
|
end
|
7228 |
|
|
//
|
7229 |
|
|
// MEMORY
|
7230 |
|
|
//
|
7231 |
|
|
// update the memory queues and put data out on bus if appropriate
|
7232 |
|
|
//
|
7233 |
|
|
|
7234 |
|
|
//
|
7235 |
|
|
// dram0, dram1, dram2 are the "state machines" that keep track
|
7236 |
|
|
// of three pipelined DRAM requests. if any has the value "00",
|
7237 |
|
|
// then it can accept a request (which bumps it up to the value "01"
|
7238 |
|
|
// at the end of the cycle). once it hits the value "11" the request
|
7239 |
|
|
// is finished and the dram_bus takes the value. if it is a store, the
|
7240 |
|
|
// dram_bus value is not used, but the dram_v value along with the
|
7241 |
|
|
// dram_id value signals the waiting memq entry that the store is
|
7242 |
|
|
// completed and the instruction can commit.
|
7243 |
|
|
//
|
7244 |
|
|
|
7245 |
|
|
// if (dram0 != `DRAMSLOT_AVAIL) dram0 <= dram0 + 2'd1;
|
7246 |
|
|
// if (dram1 != `DRAMSLOT_AVAIL) dram1 <= dram1 + 2'd1;
|
7247 |
|
|
// if (dram2 != `DRAMSLOT_AVAIL) dram2 <= dram2 + 2'd1;
|
7248 |
|
|
|
7249 |
|
|
//
|
7250 |
|
|
// grab requests that have finished and put them on the dram_bus
|
7251 |
49 |
robfinch |
if (mem1_available && dram0 == `DRAMREQ_READY) begin
|
7252 |
48 |
robfinch |
dram0 <= `DRAMSLOT_AVAIL;
|
7253 |
|
|
dramA_v <= dram0_load;
|
7254 |
|
|
dramA_id <= dram0_id;
|
7255 |
|
|
dramA_exc <= dram0_exc;
|
7256 |
|
|
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0);
|
7257 |
50 |
robfinch |
if (dram0_store) $display("m[%h] <- %h", dram0_addr, dram0_data);
|
7258 |
48 |
robfinch |
end
|
7259 |
|
|
// else
|
7260 |
|
|
// dramA_v <= `INV;
|
7261 |
49 |
robfinch |
if (mem2_available && dram1 == `DRAMREQ_READY && `NUM_MEM > 1) begin
|
7262 |
48 |
robfinch |
dram1 <= `DRAMSLOT_AVAIL;
|
7263 |
|
|
dramB_v <= dram1_load;
|
7264 |
|
|
dramB_id <= dram1_id;
|
7265 |
|
|
dramB_exc <= dram1_exc;
|
7266 |
|
|
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1);
|
7267 |
50 |
robfinch |
if (dram1_store) $display("m[%h] <- %h", dram1_addr, dram1_data);
|
7268 |
48 |
robfinch |
end
|
7269 |
|
|
// else
|
7270 |
|
|
// dramB_v <= `INV;
|
7271 |
49 |
robfinch |
if (mem3_available && dram2 == `DRAMREQ_READY && `NUM_MEM > 2) begin
|
7272 |
48 |
robfinch |
dram2 <= `DRAMSLOT_AVAIL;
|
7273 |
|
|
dramC_v <= dram2_load;
|
7274 |
|
|
dramC_id <= dram2_id;
|
7275 |
|
|
dramC_exc <= dram2_exc;
|
7276 |
|
|
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2);
|
7277 |
50 |
robfinch |
if (dram2_store) $display("m[%h] <- %h", dram2_addr, dram2_data);
|
7278 |
48 |
robfinch |
end
|
7279 |
|
|
// else
|
7280 |
|
|
// dramC_v <= `INV;
|
7281 |
|
|
|
7282 |
|
|
//
|
7283 |
|
|
// determine if the instructions ready to issue can, in fact, issue.
|
7284 |
|
|
// "ready" means that the instruction has valid operands but has not gone yet
|
7285 |
|
|
iqentry_memissue <= memissue;
|
7286 |
|
|
missue_count <= issue_count;
|
7287 |
|
|
|
7288 |
|
|
|
7289 |
|
|
//
|
7290 |
|
|
// take requests that are ready and put them into DRAM slots
|
7291 |
|
|
|
7292 |
|
|
if (dram0 == `DRAMSLOT_AVAIL) dram0_exc <= `FLT_NONE;
|
7293 |
|
|
if (dram1 == `DRAMSLOT_AVAIL) dram1_exc <= `FLT_NONE;
|
7294 |
|
|
if (dram2 == `DRAMSLOT_AVAIL) dram2_exc <= `FLT_NONE;
|
7295 |
|
|
|
7296 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
7297 |
|
|
if (iqentry_v[n] && iqentry_stomp[n]) begin
|
7298 |
|
|
iqentry_v[n] <= `INV;
|
7299 |
|
|
iqentry_iv[n] <= `INV;
|
7300 |
|
|
if (dram0_id[`QBITS] == n[`QBITS]) dram0 <= `DRAMSLOT_AVAIL;
|
7301 |
|
|
if (dram1_id[`QBITS] == n[`QBITS]) dram1 <= `DRAMSLOT_AVAIL;
|
7302 |
|
|
if (dram2_id[`QBITS] == n[`QBITS]) dram2 <= `DRAMSLOT_AVAIL;
|
7303 |
|
|
end
|
7304 |
|
|
|
7305 |
|
|
last_issue = 8;
|
7306 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
7307 |
49 |
robfinch |
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n] && ~iqentry_done[n]) begin
|
7308 |
|
|
if (mem1_available && dram0 == `DRAMSLOT_AVAIL) begin
|
7309 |
48 |
robfinch |
dramA_v <= `INV;
|
7310 |
|
|
dram0 <= `DRAMSLOT_BUSY;
|
7311 |
|
|
dram0_id <= { 1'b1, n[`QBITS] };
|
7312 |
|
|
dram0_instr <= iqentry_instr[n];
|
7313 |
|
|
dram0_rmw <= iqentry_rmw[n];
|
7314 |
|
|
dram0_preload <= iqentry_preload[n];
|
7315 |
|
|
dram0_tgt <= iqentry_tgt[n];
|
7316 |
|
|
dram0_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
7317 |
|
|
dram0_addr <= iqentry_a1[n];
|
7318 |
|
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
7319 |
|
|
// dram0_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
7320 |
|
|
// else
|
7321 |
50 |
robfinch |
dram0_unc <= iqentry_a1[n][39:20]==20'hFFFFD || !dce || iqentry_loadv[n];
|
7322 |
|
|
dram0_memsize <= iqentry_memsz[n];
|
7323 |
48 |
robfinch |
dram0_load <= iqentry_load[n];
|
7324 |
50 |
robfinch |
dram0_store <= iqentry_store[n];
|
7325 |
48 |
robfinch |
dram0_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
7326 |
|
|
// Once the memory op is issued reset the a1_v flag.
|
7327 |
|
|
// This will cause the a1 bus to look for new data from memory (a1_s is pointed to a memory bus)
|
7328 |
|
|
// This is used for the load and compare instructions.
|
7329 |
|
|
iqentry_a1_v[n] <= `INV;
|
7330 |
|
|
last_issue = n;
|
7331 |
|
|
end
|
7332 |
|
|
end
|
7333 |
|
|
if (last_issue < 8)
|
7334 |
|
|
iqentry_out[last_issue] <= `VAL;
|
7335 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
7336 |
49 |
robfinch |
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n] && ~iqentry_done[n]) begin
|
7337 |
|
|
if (mem2_available && n < last_issue && `NUM_MEM > 1) begin
|
7338 |
48 |
robfinch |
if (dram1 == `DRAMSLOT_AVAIL) begin
|
7339 |
|
|
dramB_v <= `INV;
|
7340 |
|
|
dram1 <= `DRAMSLOT_BUSY;
|
7341 |
|
|
dram1_id <= { 1'b1, n[`QBITS] };
|
7342 |
|
|
dram1_instr <= iqentry_instr[n];
|
7343 |
|
|
dram1_rmw <= iqentry_rmw[n];
|
7344 |
|
|
dram1_preload <= iqentry_preload[n];
|
7345 |
|
|
dram1_tgt <= iqentry_tgt[n];
|
7346 |
|
|
dram1_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
7347 |
|
|
dram1_addr <= iqentry_a1[n];
|
7348 |
|
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
7349 |
|
|
// dram1_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
7350 |
|
|
// else
|
7351 |
50 |
robfinch |
dram1_unc <= iqentry_a1[n][39:20]==20'hFFFFD || !dce || iqentry_loadv[n];
|
7352 |
|
|
dram1_memsize <= iqentry_memsz[n];
|
7353 |
48 |
robfinch |
dram1_load <= iqentry_load[n];
|
7354 |
50 |
robfinch |
dram1_store <= iqentry_store[n];
|
7355 |
48 |
robfinch |
dram1_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
7356 |
|
|
iqentry_a1_v[n] <= `INV;
|
7357 |
|
|
last_issue = n;
|
7358 |
|
|
end
|
7359 |
|
|
end
|
7360 |
|
|
end
|
7361 |
|
|
if (last_issue < 8)
|
7362 |
|
|
iqentry_out[last_issue] <= `VAL;
|
7363 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
7364 |
49 |
robfinch |
if (~iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && ~iqentry_out[n] && ~iqentry_done[n]) begin
|
7365 |
|
|
if (mem3_available && n < last_issue && `NUM_MEM > 2) begin
|
7366 |
48 |
robfinch |
if (dram2 == `DRAMSLOT_AVAIL) begin
|
7367 |
|
|
dramC_v <= `INV;
|
7368 |
|
|
dram2 <= `DRAMSLOT_BUSY;
|
7369 |
|
|
dram2_id <= { 1'b1, n[`QBITS] };
|
7370 |
|
|
dram2_instr <= iqentry_instr[n];
|
7371 |
|
|
dram2_rmw <= iqentry_rmw[n];
|
7372 |
|
|
dram2_preload <= iqentry_preload[n];
|
7373 |
|
|
dram2_tgt <= iqentry_tgt[n];
|
7374 |
|
|
dram2_data <= iqentry_memndx[n] ? iqentry_a3[n] : iqentry_a2[n];
|
7375 |
|
|
dram2_addr <= iqentry_a1[n];
|
7376 |
|
|
// if (ol[iqentry_thrd[n]]==`OL_USER)
|
7377 |
|
|
// dram2_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
|
7378 |
|
|
// else
|
7379 |
50 |
robfinch |
dram2_unc <= iqentry_a1[n][39:20]==20'hFFFFD || !dce || iqentry_loadv[n];
|
7380 |
|
|
dram2_memsize <= iqentry_memsz[n];
|
7381 |
48 |
robfinch |
dram2_load <= iqentry_load[n];
|
7382 |
50 |
robfinch |
dram2_store <= iqentry_store[n];
|
7383 |
48 |
robfinch |
dram2_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
|
7384 |
|
|
iqentry_a1_v[n] <= `INV;
|
7385 |
|
|
end
|
7386 |
|
|
end
|
7387 |
|
|
end
|
7388 |
|
|
if (last_issue < 8)
|
7389 |
|
|
iqentry_out[last_issue] <= `VAL;
|
7390 |
|
|
|
7391 |
51 |
robfinch |
for (n = 0; n < QENTRIES; n = n + 1)
|
7392 |
|
|
begin
|
7393 |
|
|
if (!iqentry_v[n])
|
7394 |
|
|
iqentry_done[n] <= FALSE;
|
7395 |
|
|
end
|
7396 |
48 |
robfinch |
|
7397 |
|
|
|
7398 |
|
|
|
7399 |
49 |
robfinch |
//
|
7400 |
|
|
// COMMIT PHASE (dequeue only ... not register-file update)
|
7401 |
|
|
//
|
7402 |
|
|
// look at head0 and head1 and let 'em write to the register file if they are ready
|
7403 |
|
|
//
|
7404 |
48 |
robfinch |
// always @(posedge clk) begin: commit_phase
|
7405 |
|
|
|
7406 |
49 |
robfinch |
oddball_commit(commit0_v, head0);
|
7407 |
|
|
if (`NUM_CMT > 1)
|
7408 |
|
|
oddball_commit(commit1_v, head1);
|
7409 |
50 |
robfinch |
//if (`NUM_CMT > 2)
|
7410 |
|
|
// oddball_commit(commit2_v, head2);
|
7411 |
48 |
robfinch |
|
7412 |
|
|
// Fetch and queue are limited to two instructions per cycle, so we might as
|
7413 |
|
|
// well limit retiring to two instructions max to conserve logic.
|
7414 |
|
|
//
|
7415 |
|
|
if (~|panic)
|
7416 |
49 |
robfinch |
casez ({ iqentry_v[head0],
|
7417 |
|
|
iqentry_cmt[head0],
|
7418 |
|
|
iqentry_v[head1],
|
7419 |
|
|
iqentry_cmt[head1],
|
7420 |
|
|
iqentry_v[head2],
|
7421 |
|
|
iqentry_cmt[head2]})
|
7422 |
48 |
robfinch |
|
7423 |
|
|
// retire 3
|
7424 |
49 |
robfinch |
6'b0?_0?_0?:
|
7425 |
|
|
if (head0 != tail0 && head1 != tail0 && head2 != tail0) begin
|
7426 |
|
|
head_inc(3);
|
7427 |
|
|
end
|
7428 |
|
|
else if (head0 != tail0 && head1 != tail0) begin
|
7429 |
48 |
robfinch |
head_inc(2);
|
7430 |
|
|
end
|
7431 |
|
|
else if (head0 != tail0) begin
|
7432 |
|
|
head_inc(1);
|
7433 |
|
|
end
|
7434 |
49 |
robfinch |
6'b0?_0?_10: ;
|
7435 |
|
|
6'b0?_0?_11:
|
7436 |
|
|
if (`NUM_CMT > 2 || iqentry_tgt[head2][4:0]==5'd0) begin
|
7437 |
|
|
iqentry_v[head2] <= `INV;
|
7438 |
|
|
head_inc(3);
|
7439 |
|
|
end
|
7440 |
|
|
else begin
|
7441 |
|
|
head_inc(2);
|
7442 |
|
|
end
|
7443 |
48 |
robfinch |
|
7444 |
|
|
// retire 1 (wait for regfile for head1)
|
7445 |
49 |
robfinch |
6'b0?_10_??:
|
7446 |
|
|
head_inc(1);
|
7447 |
48 |
robfinch |
|
7448 |
|
|
// retire 2
|
7449 |
49 |
robfinch |
6'b0?_11_0?,
|
7450 |
|
|
6'b0?_11_10:
|
7451 |
|
|
if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
7452 |
|
|
iqentry_v[head1] <= `INV;
|
7453 |
|
|
head_inc(2);
|
7454 |
48 |
robfinch |
end
|
7455 |
49 |
robfinch |
else begin
|
7456 |
|
|
head_inc(1);
|
7457 |
|
|
end
|
7458 |
|
|
6'b0?_11_11:
|
7459 |
50 |
robfinch |
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2] == 12'd0 && !iqentry_oddball[head2] && ~|iqentry_exc[head2])) begin
|
7460 |
49 |
robfinch |
iqentry_v[head1] <= `INV;
|
7461 |
|
|
iqentry_v[head2] <= `INV;
|
7462 |
|
|
head_inc(3);
|
7463 |
|
|
end
|
7464 |
|
|
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
7465 |
|
|
iqentry_v[head1] <= `INV;
|
7466 |
|
|
head_inc(2);
|
7467 |
|
|
end
|
7468 |
|
|
else
|
7469 |
|
|
head_inc(1);
|
7470 |
|
|
6'b10_??_??: ;
|
7471 |
|
|
6'b11_0?_0?:
|
7472 |
|
|
if (head1 != tail0 && head2 != tail0) begin
|
7473 |
48 |
robfinch |
iqentry_v[head0] <= `INV;
|
7474 |
49 |
robfinch |
head_inc(3);
|
7475 |
|
|
end
|
7476 |
|
|
else if (head1 != tail0) begin
|
7477 |
|
|
iqentry_v[head0] <= `INV;
|
7478 |
48 |
robfinch |
head_inc(2);
|
7479 |
49 |
robfinch |
end
|
7480 |
|
|
else begin
|
7481 |
48 |
robfinch |
iqentry_v[head0] <= `INV;
|
7482 |
|
|
head_inc(1);
|
7483 |
49 |
robfinch |
end
|
7484 |
|
|
6'b11_0?_10:
|
7485 |
|
|
if (head1 != tail0) begin
|
7486 |
|
|
iqentry_v[head0] <= `INV;
|
7487 |
|
|
head_inc(2);
|
7488 |
|
|
end
|
7489 |
|
|
else begin
|
7490 |
|
|
iqentry_v[head0] <= `INV;
|
7491 |
|
|
head_inc(1);
|
7492 |
|
|
end
|
7493 |
|
|
6'b11_0?_11:
|
7494 |
|
|
if (head1 != tail0) begin
|
7495 |
50 |
robfinch |
if (`NUM_CMT > 2 || (iqentry_tgt[head2]==12'd0 && !iqentry_oddball[head2] && ~|iqentry_exc[head2])) begin
|
7496 |
49 |
robfinch |
iqentry_v[head0] <= `INV;
|
7497 |
|
|
iqentry_v[head2] <= `INV;
|
7498 |
|
|
head_inc(3);
|
7499 |
|
|
end
|
7500 |
|
|
else begin
|
7501 |
|
|
iqentry_v[head0] <= `INV;
|
7502 |
|
|
head_inc(2);
|
7503 |
|
|
end
|
7504 |
|
|
end
|
7505 |
|
|
else begin
|
7506 |
|
|
iqentry_v[head0] <= `INV;
|
7507 |
|
|
head_inc(1);
|
7508 |
|
|
end
|
7509 |
|
|
6'b11_10_??:
|
7510 |
|
|
begin
|
7511 |
|
|
iqentry_v[head0] <= `INV;
|
7512 |
|
|
head_inc(1);
|
7513 |
|
|
end
|
7514 |
|
|
6'b11_11_0?:
|
7515 |
|
|
if (`NUM_CMT > 1 && head2 != tail0) begin
|
7516 |
|
|
iqentry_v[head0] <= `INV;
|
7517 |
|
|
iqentry_v[head1] <= `INV;
|
7518 |
|
|
head_inc(3);
|
7519 |
|
|
end
|
7520 |
|
|
else if (iqentry_tgt[head1]== 12'd0 && head2 != tail0) begin
|
7521 |
|
|
iqentry_v[head0] <= `INV;
|
7522 |
|
|
iqentry_v[head1] <= `INV;
|
7523 |
|
|
head_inc(3);
|
7524 |
|
|
end
|
7525 |
|
|
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
7526 |
|
|
iqentry_v[head0] <= `INV;
|
7527 |
|
|
iqentry_v[head1] <= `INV;
|
7528 |
|
|
head_inc(2);
|
7529 |
|
|
end
|
7530 |
|
|
else begin
|
7531 |
|
|
iqentry_v[head0] <= `INV;
|
7532 |
|
|
head_inc(1);
|
7533 |
|
|
end
|
7534 |
|
|
6'b11_11_10:
|
7535 |
|
|
if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
7536 |
|
|
iqentry_v[head0] <= `INV;
|
7537 |
|
|
iqentry_v[head1] <= `INV;
|
7538 |
|
|
head_inc(2);
|
7539 |
|
|
end
|
7540 |
|
|
else begin
|
7541 |
|
|
iqentry_v[head0] <= `INV;
|
7542 |
|
|
head_inc(1);
|
7543 |
|
|
end
|
7544 |
|
|
6'b11_11_11:
|
7545 |
50 |
robfinch |
if (`NUM_CMT > 2 || (`NUM_CMT > 1 && iqentry_tgt[head2]==12'd0 && !iqentry_oddball[head2] && ~|iqentry_exc[head2])) begin
|
7546 |
49 |
robfinch |
iqentry_v[head0] <= `INV;
|
7547 |
|
|
iqentry_v[head1] <= `INV;
|
7548 |
|
|
iqentry_v[head2] <= `INV;
|
7549 |
|
|
head_inc(3);
|
7550 |
48 |
robfinch |
end
|
7551 |
49 |
robfinch |
else if (`NUM_CMT > 1 || iqentry_tgt[head1]==12'd0) begin
|
7552 |
48 |
robfinch |
iqentry_v[head0] <= `INV;
|
7553 |
49 |
robfinch |
iqentry_v[head1] <= `INV;
|
7554 |
|
|
head_inc(2);
|
7555 |
|
|
end
|
7556 |
|
|
else begin
|
7557 |
|
|
iqentry_v[head0] <= `INV;
|
7558 |
48 |
robfinch |
head_inc(1);
|
7559 |
|
|
end
|
7560 |
49 |
robfinch |
endcase
|
7561 |
48 |
robfinch |
|
7562 |
|
|
|
7563 |
|
|
rf_source[0] <= 0;
|
7564 |
|
|
L1_wr0 <= FALSE;
|
7565 |
|
|
L1_wr1 <= FALSE;
|
7566 |
|
|
L1_invline <= FALSE;
|
7567 |
|
|
icnxt <= FALSE;
|
7568 |
|
|
L2_nxt <= FALSE;
|
7569 |
|
|
// Instruction cache state machine.
|
7570 |
|
|
// On a miss first see if the instruction is in the L2 cache. No need to go to
|
7571 |
|
|
// the BIU on an L1 miss.
|
7572 |
|
|
// If not the machine will wait until the BIU loads the L2 cache.
|
7573 |
|
|
|
7574 |
|
|
// Capture the previous ic state, used to determine how long to wait in
|
7575 |
|
|
// icstate #4.
|
7576 |
|
|
picstate <= icstate;
|
7577 |
|
|
case(icstate)
|
7578 |
|
|
IDLE:
|
7579 |
|
|
// If the bus unit is busy doing an update involving L1_adr or L2_adr
|
7580 |
|
|
// we have to wait.
|
7581 |
|
|
if (bstate != B7 && bstate != B9) begin
|
7582 |
|
|
if (!ihit0) begin
|
7583 |
|
|
L1_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
7584 |
|
|
L2_adr <= {pcr[5:0],pc0[31:3],3'h0};
|
7585 |
|
|
L1_invline <= TRUE;
|
7586 |
49 |
robfinch |
icwhich <= 2'b00;
|
7587 |
48 |
robfinch |
iccnt <= 3'b00;
|
7588 |
|
|
icstate <= IC2;
|
7589 |
|
|
end
|
7590 |
49 |
robfinch |
else if (!ihit1 && `WAYS > 1) begin
|
7591 |
48 |
robfinch |
`ifdef SUPPORT_SMT
|
7592 |
|
|
L1_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
7593 |
|
|
L2_adr <= {pcr[5:0],pc1[31:3],3'h0};
|
7594 |
|
|
`else
|
7595 |
|
|
L1_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
7596 |
|
|
L2_adr <= {pcr[5:0],pc0plus6[31:3],3'h0};
|
7597 |
|
|
`endif
|
7598 |
|
|
L1_invline <= TRUE;
|
7599 |
49 |
robfinch |
icwhich <= 2'b01;
|
7600 |
48 |
robfinch |
iccnt <= 3'b00;
|
7601 |
|
|
icstate <= IC2;
|
7602 |
|
|
end
|
7603 |
49 |
robfinch |
else if (!ihit2 && `WAYS > 2) begin
|
7604 |
|
|
`ifdef SUPPORT_SMT
|
7605 |
|
|
L1_adr <= {pcr[5:0],pc2[31:3],3'h0};
|
7606 |
|
|
L2_adr <= {pcr[5:0],pc2[31:3],3'h0};
|
7607 |
|
|
`else
|
7608 |
|
|
L1_adr <= {pcr[5:0],pc0plus12[31:3],3'h0};
|
7609 |
|
|
L2_adr <= {pcr[5:0],pc0plus12[31:3],3'h0};
|
7610 |
|
|
`endif
|
7611 |
|
|
L1_invline <= TRUE;
|
7612 |
|
|
icwhich <= 2'b10;
|
7613 |
|
|
iccnt <= 3'b00;
|
7614 |
|
|
icstate <= IC2;
|
7615 |
|
|
end
|
7616 |
48 |
robfinch |
end
|
7617 |
|
|
IC2: icstate <= IC3;
|
7618 |
|
|
IC3: icstate <= IC3a;
|
7619 |
|
|
IC3a: icstate <= IC4;
|
7620 |
|
|
// If data was in the L2 cache already there's no need to wait on the
|
7621 |
|
|
// BIU to retrieve data. It can be determined if the hit signal was
|
7622 |
|
|
// already active when this state was entered in which case waiting
|
7623 |
|
|
// will do no good.
|
7624 |
|
|
// The IC machine will stall in this state until the BIU has loaded the
|
7625 |
|
|
// L2 cache.
|
7626 |
|
|
IC4:
|
7627 |
49 |
robfinch |
if (ihitL2 && picstate==IC3a) begin
|
7628 |
|
|
L1_en <= 9'h1FF;
|
7629 |
48 |
robfinch |
L1_wr0 <= TRUE;
|
7630 |
49 |
robfinch |
L1_wr1 <= TRUE && `WAYS > 1;
|
7631 |
|
|
L1_wr2 <= TRUE && `WAYS > 2;
|
7632 |
48 |
robfinch |
L1_adr <= L2_adr;
|
7633 |
|
|
L2_rdat <= L2_dato;
|
7634 |
|
|
icstate <= IC5;
|
7635 |
|
|
end
|
7636 |
|
|
else if (bstate!=B9)
|
7637 |
|
|
;
|
7638 |
|
|
else begin
|
7639 |
49 |
robfinch |
L1_en <= 9'h1FF;
|
7640 |
48 |
robfinch |
L1_wr0 <= TRUE;
|
7641 |
49 |
robfinch |
L1_wr1 <= TRUE && `WAYS > 1;
|
7642 |
|
|
L1_wr2 <= TRUE && `WAYS > 2;
|
7643 |
48 |
robfinch |
L1_adr <= L2_adr;
|
7644 |
|
|
L2_rdat <= L2_dato;
|
7645 |
|
|
icstate <= IC5;
|
7646 |
|
|
end
|
7647 |
|
|
IC5:
|
7648 |
|
|
begin
|
7649 |
49 |
robfinch |
L1_en <= 9'h000;
|
7650 |
48 |
robfinch |
L1_wr0 <= FALSE;
|
7651 |
|
|
L1_wr1 <= FALSE;
|
7652 |
49 |
robfinch |
L1_wr2 <= FALSE;
|
7653 |
48 |
robfinch |
icstate <= IC6;
|
7654 |
|
|
end
|
7655 |
|
|
IC6: icstate <= IC7;
|
7656 |
|
|
IC7: icstate <= IC8;
|
7657 |
|
|
IC8: begin
|
7658 |
|
|
icstate <= IDLE;
|
7659 |
|
|
icnxt <= TRUE;
|
7660 |
|
|
end
|
7661 |
|
|
default: icstate <= IDLE;
|
7662 |
|
|
endcase
|
7663 |
|
|
|
7664 |
49 |
robfinch |
if (mem1_available && dram0_load)
|
7665 |
48 |
robfinch |
case(dram0)
|
7666 |
|
|
`DRAMSLOT_AVAIL: ;
|
7667 |
|
|
`DRAMSLOT_BUSY: dram0 <= dram0 + !dram0_unc;
|
7668 |
|
|
3'd2: dram0 <= dram0 + 3'd1;
|
7669 |
|
|
3'd3: dram0 <= dram0 + 3'd1;
|
7670 |
|
|
3'd4: if (dhit0) dram0 <= `DRAMREQ_READY; else dram0 <= `DRAMSLOT_REQBUS;
|
7671 |
|
|
`DRAMSLOT_REQBUS: ;
|
7672 |
|
|
`DRAMSLOT_HASBUS: ;
|
7673 |
|
|
`DRAMREQ_READY: ;
|
7674 |
|
|
endcase
|
7675 |
|
|
|
7676 |
49 |
robfinch |
if (mem2_available && dram1_load && `NUM_MEM > 1)
|
7677 |
48 |
robfinch |
case(dram1)
|
7678 |
|
|
`DRAMSLOT_AVAIL: ;
|
7679 |
|
|
`DRAMSLOT_BUSY: dram1 <= dram1 + !dram1_unc;
|
7680 |
|
|
3'd2: dram1 <= dram1 + 3'd1;
|
7681 |
|
|
3'd3: dram1 <= dram1 + 3'd1;
|
7682 |
|
|
3'd4: if (dhit1) dram1 <= `DRAMREQ_READY; else dram1 <= `DRAMSLOT_REQBUS;
|
7683 |
|
|
`DRAMSLOT_REQBUS: ;
|
7684 |
|
|
`DRAMSLOT_HASBUS: ;
|
7685 |
|
|
`DRAMREQ_READY: ;
|
7686 |
|
|
endcase
|
7687 |
|
|
|
7688 |
49 |
robfinch |
if (mem3_available && dram2_load && `NUM_MEM > 2)
|
7689 |
48 |
robfinch |
case(dram2)
|
7690 |
|
|
`DRAMSLOT_AVAIL: ;
|
7691 |
|
|
`DRAMSLOT_BUSY: dram2 <= dram2 + !dram2_unc;
|
7692 |
|
|
3'd2: dram2 <= dram2 + 3'd1;
|
7693 |
|
|
3'd3: dram2 <= dram2 + 3'd1;
|
7694 |
|
|
3'd4: if (dhit2) dram2 <= `DRAMREQ_READY; else dram2 <= `DRAMSLOT_REQBUS;
|
7695 |
|
|
`DRAMSLOT_REQBUS: ;
|
7696 |
|
|
`DRAMSLOT_HASBUS: ;
|
7697 |
|
|
`DRAMREQ_READY: ;
|
7698 |
|
|
endcase
|
7699 |
|
|
|
7700 |
|
|
// Bus Interface Unit (BIU)
|
7701 |
|
|
// Interfaces to the external bus which is WISHBONE compatible.
|
7702 |
|
|
// Stores take precedence over other operations.
|
7703 |
|
|
// Next data cache read misses are serviced.
|
7704 |
|
|
// Uncached data reads are serviced.
|
7705 |
|
|
// Finally L2 instruction cache misses are serviced.
|
7706 |
|
|
|
7707 |
|
|
case(bstate)
|
7708 |
|
|
BIDLE:
|
7709 |
49 |
robfinch |
begin
|
7710 |
|
|
isCAS <= FALSE;
|
7711 |
|
|
isAMO <= FALSE;
|
7712 |
|
|
isInc <= FALSE;
|
7713 |
|
|
isSpt <= FALSE;
|
7714 |
|
|
isRMW <= FALSE;
|
7715 |
|
|
rdvq <= 1'b0;
|
7716 |
|
|
errq <= 1'b0;
|
7717 |
|
|
exvq <= 1'b0;
|
7718 |
|
|
bwhich <= 2'b00;
|
7719 |
|
|
preload <= FALSE;
|
7720 |
|
|
`ifdef HAS_WB
|
7721 |
|
|
if (wb_v[0] & wb_en) begin
|
7722 |
|
|
cyc_o <= `HIGH;
|
7723 |
|
|
stb_o <= `HIGH;
|
7724 |
|
|
we_o <= `HIGH;
|
7725 |
|
|
sel_o <= wb_sel[0];
|
7726 |
|
|
adr_o <= wb_addr[0];
|
7727 |
|
|
dat_o <= wb_data[0];
|
7728 |
|
|
ol_o <= wb_ol[0];
|
7729 |
|
|
wbo_id <= wb_id[0];
|
7730 |
|
|
bstate <= wb_rmw[0] ? B12 : B1;
|
7731 |
|
|
end
|
7732 |
|
|
begin
|
7733 |
|
|
for (j = 1; j < `WB_DEPTH; j = j + 1) begin
|
7734 |
|
|
wb_v[j-1] <= wb_v[j];
|
7735 |
|
|
wb_id[j-1] <= wb_id[j];
|
7736 |
|
|
wb_rmw[j-1] <= wb_rmw[j];
|
7737 |
|
|
wb_sel[j-1] <= wb_sel[j];
|
7738 |
|
|
wb_addr[j-1] <= wb_addr[j];
|
7739 |
|
|
wb_data[j-1] <= wb_data[j];
|
7740 |
|
|
wb_ol[j-1] <= wb_ol[j];
|
7741 |
|
|
end
|
7742 |
|
|
wb_v[`WB_DEPTH-1] <= `INV;
|
7743 |
|
|
wb_rmw[`WB_DEPTH-1] <= `FALSE;
|
7744 |
|
|
end
|
7745 |
|
|
|
7746 |
|
|
// if (|wb_v)
|
7747 |
|
|
// ;
|
7748 |
|
|
// else
|
7749 |
|
|
`endif
|
7750 |
|
|
if (~|wb_v && mem1_available && dram0==`DRAMSLOT_BUSY && dram0_rmw) begin
|
7751 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7752 |
|
|
if (dbg_smatch0|dbg_lmatch0) begin
|
7753 |
|
|
dramA_v <= `TRUE;
|
7754 |
|
|
dramA_id <= dram0_id;
|
7755 |
|
|
dramA_exc <= `FLT_DBG;
|
7756 |
|
|
dramA_bus <= 64'h0;
|
7757 |
|
|
dram0 <= `DRAMSLOT_AVAIL;
|
7758 |
|
|
end
|
7759 |
|
|
else
|
7760 |
|
|
`endif
|
7761 |
|
|
begin
|
7762 |
|
|
isRMW <= dram0_rmw;
|
7763 |
|
|
isCAS <= IsCAS(dram0_instr);
|
7764 |
|
|
isAMO <= IsAMO(dram0_instr);
|
7765 |
|
|
isInc <= IsInc(dram0_instr);
|
7766 |
|
|
casid <= dram0_id;
|
7767 |
|
|
bwhich <= 2'b00;
|
7768 |
49 |
robfinch |
dram0 <= `DRAMSLOT_HASBUS;
|
7769 |
48 |
robfinch |
cyc_o <= `HIGH;
|
7770 |
|
|
stb_o <= `HIGH;
|
7771 |
|
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
7772 |
|
|
adr_o <= dram0_addr;
|
7773 |
|
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
7774 |
|
|
ol_o <= dram0_ol;
|
7775 |
|
|
bstate <= B12;
|
7776 |
|
|
end
|
7777 |
|
|
end
|
7778 |
49 |
robfinch |
else if (~|wb_v && mem2_available && dram1==`DRAMSLOT_BUSY && dram1_rmw && `NUM_MEM > 1) begin
|
7779 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7780 |
|
|
if (dbg_smatch1|dbg_lmatch1) begin
|
7781 |
|
|
dramB_v <= `TRUE;
|
7782 |
|
|
dramB_id <= dram1_id;
|
7783 |
|
|
dramB_exc <= `FLT_DBG;
|
7784 |
|
|
dramB_bus <= 64'h0;
|
7785 |
|
|
dram1 <= `DRAMSLOT_AVAIL;
|
7786 |
|
|
end
|
7787 |
|
|
else
|
7788 |
|
|
`endif
|
7789 |
|
|
begin
|
7790 |
|
|
isRMW <= dram1_rmw;
|
7791 |
|
|
isCAS <= IsCAS(dram1_instr);
|
7792 |
|
|
isAMO <= IsAMO(dram1_instr);
|
7793 |
|
|
isInc <= IsInc(dram1_instr);
|
7794 |
|
|
casid <= dram1_id;
|
7795 |
|
|
bwhich <= 2'b01;
|
7796 |
49 |
robfinch |
dram1 <= `DRAMSLOT_HASBUS;
|
7797 |
48 |
robfinch |
cyc_o <= `HIGH;
|
7798 |
|
|
stb_o <= `HIGH;
|
7799 |
|
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
7800 |
|
|
adr_o <= dram1_addr;
|
7801 |
|
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
7802 |
|
|
ol_o <= dram1_ol;
|
7803 |
|
|
bstate <= B12;
|
7804 |
|
|
end
|
7805 |
|
|
end
|
7806 |
49 |
robfinch |
else if (~|wb_v && mem3_available && dram2==`DRAMSLOT_BUSY && dram2_rmw && `NUM_MEM > 2) begin
|
7807 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7808 |
|
|
if (dbg_smatch2|dbg_lmatch2) begin
|
7809 |
|
|
dramC_v <= `TRUE;
|
7810 |
|
|
dramC_id <= dram2_id;
|
7811 |
|
|
dramC_exc <= `FLT_DBG;
|
7812 |
|
|
dramC_bus <= 64'h0;
|
7813 |
|
|
dram2 <= `DRAMSLOT_AVAIL;
|
7814 |
|
|
end
|
7815 |
|
|
else
|
7816 |
|
|
`endif
|
7817 |
|
|
begin
|
7818 |
|
|
isRMW <= dram2_rmw;
|
7819 |
|
|
isCAS <= IsCAS(dram2_instr);
|
7820 |
|
|
isAMO <= IsAMO(dram2_instr);
|
7821 |
|
|
isInc <= IsInc(dram2_instr);
|
7822 |
|
|
casid <= dram2_id;
|
7823 |
|
|
bwhich <= 2'b10;
|
7824 |
49 |
robfinch |
dram2 <= `DRAMSLOT_HASBUS;
|
7825 |
48 |
robfinch |
cyc_o <= `HIGH;
|
7826 |
|
|
stb_o <= `HIGH;
|
7827 |
|
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
7828 |
|
|
adr_o <= dram2_addr;
|
7829 |
|
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
7830 |
|
|
ol_o <= dram2_ol;
|
7831 |
|
|
bstate <= B12;
|
7832 |
|
|
end
|
7833 |
|
|
end
|
7834 |
50 |
robfinch |
else if (mem1_available && dram0==`DRAMSLOT_BUSY && dram0_store) begin
|
7835 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7836 |
|
|
if (dbg_smatch0) begin
|
7837 |
|
|
dramA_v <= `TRUE;
|
7838 |
|
|
dramA_id <= dram0_id;
|
7839 |
|
|
dramA_exc <= `FLT_DBG;
|
7840 |
|
|
dramA_bus <= 64'h0;
|
7841 |
|
|
dram0 <= `DRAMSLOT_AVAIL;
|
7842 |
|
|
end
|
7843 |
|
|
else
|
7844 |
|
|
`endif
|
7845 |
|
|
begin
|
7846 |
49 |
robfinch |
bwhich <= 2'b00;
|
7847 |
|
|
`ifndef HAS_WB
|
7848 |
|
|
dram0 <= `DRAMSLOT_HASBUS;
|
7849 |
|
|
dram0_instr[`INSTRUCTION_OP] <= `NOP;
|
7850 |
|
|
cyc_o <= `HIGH;
|
7851 |
|
|
stb_o <= `HIGH;
|
7852 |
48 |
robfinch |
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
7853 |
|
|
adr_o <= dram0_addr;
|
7854 |
|
|
dat_o <= fnDato(dram0_instr,dram0_data);
|
7855 |
|
|
ol_o <= dram0_ol;
|
7856 |
|
|
bstate <= B1;
|
7857 |
49 |
robfinch |
`else
|
7858 |
|
|
if (wbptr<`WB_DEPTH-1) begin
|
7859 |
|
|
dram0 <= `DRAMREQ_READY;
|
7860 |
|
|
dram0_instr[`INSTRUCTION_OP] <= `NOP;
|
7861 |
|
|
wb_update(
|
7862 |
|
|
dram0_id,
|
7863 |
|
|
`FALSE,
|
7864 |
|
|
fnSelect(dram0_instr,dram0_addr),
|
7865 |
|
|
dram0_ol,
|
7866 |
|
|
dram0_addr,
|
7867 |
|
|
fnDato(dram0_instr,dram0_data)
|
7868 |
|
|
);
|
7869 |
|
|
iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
|
7870 |
|
|
iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
7871 |
|
|
end
|
7872 |
|
|
`endif
|
7873 |
|
|
// cr_o <= IsSWC(dram0_instr);
|
7874 |
48 |
robfinch |
end
|
7875 |
|
|
end
|
7876 |
50 |
robfinch |
else if (mem2_available && dram1==`DRAMSLOT_BUSY && dram1_store && `NUM_MEM > 1) begin
|
7877 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7878 |
|
|
if (dbg_smatch1) begin
|
7879 |
|
|
dramB_v <= `TRUE;
|
7880 |
|
|
dramB_id <= dram1_id;
|
7881 |
|
|
dramB_exc <= `FLT_DBG;
|
7882 |
|
|
dramB_bus <= 64'h0;
|
7883 |
|
|
dram1 <= `DRAMSLOT_AVAIL;
|
7884 |
|
|
end
|
7885 |
|
|
else
|
7886 |
|
|
`endif
|
7887 |
|
|
begin
|
7888 |
49 |
robfinch |
bwhich <= 2'b01;
|
7889 |
|
|
`ifndef HAS_WB
|
7890 |
48 |
robfinch |
dram1 <= `DRAMSLOT_HASBUS;
|
7891 |
|
|
dram1_instr[`INSTRUCTION_OP] <= `NOP;
|
7892 |
49 |
robfinch |
cyc_o <= `HIGH;
|
7893 |
|
|
stb_o <= `HIGH;
|
7894 |
48 |
robfinch |
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
7895 |
|
|
adr_o <= dram1_addr;
|
7896 |
|
|
dat_o <= fnDato(dram1_instr,dram1_data);
|
7897 |
|
|
ol_o <= dram1_ol;
|
7898 |
|
|
bstate <= B1;
|
7899 |
49 |
robfinch |
`else
|
7900 |
|
|
if (wbptr<`WB_DEPTH-1) begin
|
7901 |
|
|
dram1 <= `DRAMREQ_READY;
|
7902 |
|
|
dram1_instr[`INSTRUCTION_OP] <= `NOP;
|
7903 |
|
|
wb_update(
|
7904 |
|
|
dram1_id,
|
7905 |
|
|
`FALSE,
|
7906 |
|
|
fnSelect(dram1_instr,dram1_addr),
|
7907 |
|
|
dram1_ol,
|
7908 |
|
|
dram1_addr,
|
7909 |
|
|
fnDato(dram1_instr,dram1_data)
|
7910 |
|
|
);
|
7911 |
|
|
iqentry_done[ dram1_id[`QBITS] ] <= `VAL;
|
7912 |
|
|
iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
7913 |
|
|
end
|
7914 |
|
|
`endif
|
7915 |
|
|
// cr_o <= IsSWC(dram0_instr);
|
7916 |
48 |
robfinch |
end
|
7917 |
|
|
end
|
7918 |
50 |
robfinch |
else if (mem3_available && dram2==`DRAMSLOT_BUSY && dram2_store && `NUM_MEM > 2) begin
|
7919 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7920 |
|
|
if (dbg_smatch2) begin
|
7921 |
|
|
dramC_v <= `TRUE;
|
7922 |
|
|
dramC_id <= dram2_id;
|
7923 |
|
|
dramC_exc <= `FLT_DBG;
|
7924 |
|
|
dramC_bus <= 64'h0;
|
7925 |
|
|
dram2 <= `DRAMSLOT_AVAIL;
|
7926 |
|
|
end
|
7927 |
|
|
else
|
7928 |
|
|
`endif
|
7929 |
|
|
begin
|
7930 |
49 |
robfinch |
bwhich <= 2'b10;
|
7931 |
|
|
`ifndef HAS_WB
|
7932 |
48 |
robfinch |
dram2 <= `DRAMSLOT_HASBUS;
|
7933 |
|
|
dram2_instr[`INSTRUCTION_OP] <= `NOP;
|
7934 |
49 |
robfinch |
cyc_o <= `HIGH;
|
7935 |
|
|
stb_o <= `HIGH;
|
7936 |
48 |
robfinch |
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
7937 |
|
|
adr_o <= dram2_addr;
|
7938 |
|
|
dat_o <= fnDato(dram2_instr,dram2_data);
|
7939 |
|
|
ol_o <= dram2_ol;
|
7940 |
|
|
bstate <= B1;
|
7941 |
49 |
robfinch |
`else
|
7942 |
|
|
if (wbptr<`WB_DEPTH-1) begin
|
7943 |
|
|
dram2 <= `DRAMREQ_READY;
|
7944 |
|
|
dram2_instr[`INSTRUCTION_OP] <= `NOP;
|
7945 |
|
|
wb_update(
|
7946 |
|
|
dram2_id,
|
7947 |
|
|
`FALSE,
|
7948 |
|
|
fnSelect(dram2_instr,dram2_addr),
|
7949 |
|
|
dram2_ol,
|
7950 |
|
|
dram2_addr,
|
7951 |
|
|
fnDato(dram2_instr,dram2_data)
|
7952 |
|
|
);
|
7953 |
|
|
iqentry_done[ dram2_id[`QBITS] ] <= `VAL;
|
7954 |
|
|
iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
7955 |
|
|
end
|
7956 |
|
|
`endif
|
7957 |
|
|
// cr_o <= IsSWC(dram0_instr);
|
7958 |
48 |
robfinch |
end
|
7959 |
|
|
end
|
7960 |
|
|
// Check for read misses on the data cache
|
7961 |
51 |
robfinch |
else if (~|wb_v && mem1_available && !dram0_unc && dram0==`DRAMSLOT_REQBUS && dram0_load) begin
|
7962 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7963 |
|
|
if (dbg_lmatch0) begin
|
7964 |
|
|
dramA_v <= `TRUE;
|
7965 |
|
|
dramA_id <= dram0_id;
|
7966 |
|
|
dramA_exc <= `FLT_DBG;
|
7967 |
|
|
dramA_bus <= 64'h0;
|
7968 |
|
|
dram0 <= `DRAMSLOT_AVAIL;
|
7969 |
|
|
end
|
7970 |
|
|
else
|
7971 |
|
|
`endif
|
7972 |
|
|
begin
|
7973 |
|
|
dram0 <= `DRAMSLOT_HASBUS;
|
7974 |
|
|
bwhich <= 2'b00;
|
7975 |
|
|
preload <= dram0_preload;
|
7976 |
|
|
bstate <= B2;
|
7977 |
|
|
end
|
7978 |
|
|
end
|
7979 |
49 |
robfinch |
else if (~|wb_v && mem2_available && !dram1_unc && dram1==`DRAMSLOT_REQBUS && dram1_load && `NUM_MEM > 1) begin
|
7980 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7981 |
|
|
if (dbg_lmatch1) begin
|
7982 |
|
|
dramB_v <= `TRUE;
|
7983 |
|
|
dramB_id <= dram1_id;
|
7984 |
|
|
dramB_exc <= `FLT_DBG;
|
7985 |
|
|
dramB_bus <= 64'h0;
|
7986 |
|
|
dram1 <= `DRAMSLOT_AVAIL;
|
7987 |
|
|
end
|
7988 |
|
|
else
|
7989 |
|
|
`endif
|
7990 |
|
|
begin
|
7991 |
|
|
dram1 <= `DRAMSLOT_HASBUS;
|
7992 |
|
|
bwhich <= 2'b01;
|
7993 |
|
|
preload <= dram1_preload;
|
7994 |
|
|
bstate <= B2;
|
7995 |
|
|
end
|
7996 |
|
|
end
|
7997 |
49 |
robfinch |
else if (~|wb_v && mem3_available && !dram2_unc && dram2==`DRAMSLOT_REQBUS && dram2_load && `NUM_MEM > 2) begin
|
7998 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
7999 |
|
|
if (dbg_lmatch2) begin
|
8000 |
|
|
dramC_v <= `TRUE;
|
8001 |
|
|
dramC_id <= dram2_id;
|
8002 |
|
|
dramC_exc <= `FLT_DBG;
|
8003 |
|
|
dramC_bus <= 64'h0;
|
8004 |
|
|
dram2 <= `DRAMSLOT_AVAIL;
|
8005 |
|
|
end
|
8006 |
|
|
else
|
8007 |
|
|
`endif
|
8008 |
|
|
begin
|
8009 |
|
|
dram2 <= `DRAMSLOT_HASBUS;
|
8010 |
|
|
preload <= dram2_preload;
|
8011 |
|
|
bwhich <= 2'b10;
|
8012 |
|
|
bstate <= B2;
|
8013 |
|
|
end
|
8014 |
|
|
end
|
8015 |
49 |
robfinch |
else if (~|wb_v && mem1_available && dram0_unc && dram0==`DRAMSLOT_BUSY && dram0_load) begin
|
8016 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
8017 |
|
|
if (dbg_lmatch0) begin
|
8018 |
|
|
dramA_v <= `TRUE;
|
8019 |
|
|
dramA_id <= dram0_id;
|
8020 |
|
|
dramA_exc <= `FLT_DBG;
|
8021 |
|
|
dramA_bus <= 64'h0;
|
8022 |
|
|
dram0 <= `DRAMSLOT_AVAIL;
|
8023 |
|
|
end
|
8024 |
|
|
else
|
8025 |
|
|
`endif
|
8026 |
|
|
begin
|
8027 |
|
|
bwhich <= 2'b00;
|
8028 |
|
|
cyc_o <= `HIGH;
|
8029 |
|
|
stb_o <= `HIGH;
|
8030 |
|
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
8031 |
|
|
adr_o <= {dram0_addr[31:3],3'b0};
|
8032 |
|
|
sr_o <= IsLWR(dram0_instr);
|
8033 |
|
|
ol_o <= dram0_ol;
|
8034 |
|
|
bstate <= B12;
|
8035 |
|
|
end
|
8036 |
|
|
end
|
8037 |
49 |
robfinch |
else if (~|wb_v && mem2_available && dram1_unc && dram1==`DRAMSLOT_BUSY && dram1_load && `NUM_MEM > 1) begin
|
8038 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
8039 |
|
|
if (dbg_lmatch1) begin
|
8040 |
|
|
dramB_v <= `TRUE;
|
8041 |
|
|
dramB_id <= dram1_id;
|
8042 |
|
|
dramB_exc <= `FLT_DBG;
|
8043 |
|
|
dramB_bus <= 64'h0;
|
8044 |
|
|
dram1 <= `DRAMSLOT_AVAIL;
|
8045 |
|
|
end
|
8046 |
|
|
else
|
8047 |
|
|
`endif
|
8048 |
|
|
begin
|
8049 |
|
|
bwhich <= 2'b01;
|
8050 |
|
|
cyc_o <= `HIGH;
|
8051 |
|
|
stb_o <= `HIGH;
|
8052 |
|
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
8053 |
|
|
adr_o <= {dram1_addr[31:3],3'b0};
|
8054 |
|
|
sr_o <= IsLWR(dram1_instr);
|
8055 |
|
|
ol_o <= dram1_ol;
|
8056 |
|
|
bstate <= B12;
|
8057 |
|
|
end
|
8058 |
|
|
end
|
8059 |
49 |
robfinch |
else if (~|wb_v && mem3_available && dram2_unc && dram2==`DRAMSLOT_BUSY && dram2_load && `NUM_MEM > 2) begin
|
8060 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
8061 |
|
|
if (dbg_lmatch2) begin
|
8062 |
|
|
dramC_v <= `TRUE;
|
8063 |
|
|
dramC_id <= dram2_id;
|
8064 |
|
|
dramC_exc <= `FLT_DBG;
|
8065 |
|
|
dramC_bus <= 64'h0;
|
8066 |
|
|
dram2 <= 2'd0;
|
8067 |
|
|
end
|
8068 |
|
|
else
|
8069 |
|
|
`endif
|
8070 |
|
|
begin
|
8071 |
|
|
bwhich <= 2'b10;
|
8072 |
|
|
cyc_o <= `HIGH;
|
8073 |
|
|
stb_o <= `HIGH;
|
8074 |
|
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
8075 |
|
|
adr_o <= {dram2_addr[31:3],3'b0};
|
8076 |
|
|
sr_o <= IsLWR(dram2_instr);
|
8077 |
|
|
ol_o <= dram2_ol;
|
8078 |
|
|
bstate <= B12;
|
8079 |
|
|
end
|
8080 |
|
|
end
|
8081 |
|
|
// Check for L2 cache miss
|
8082 |
49 |
robfinch |
else if (~|wb_v && !ihitL2) begin
|
8083 |
48 |
robfinch |
cti_o <= 3'b001;
|
8084 |
49 |
robfinch |
bte_o <= 2'b00;//2'b01; // 4 beat burst wrap
|
8085 |
48 |
robfinch |
cyc_o <= `HIGH;
|
8086 |
|
|
stb_o <= `HIGH;
|
8087 |
|
|
sel_o <= 8'hFF;
|
8088 |
|
|
icl_o <= `HIGH;
|
8089 |
49 |
robfinch |
iccnt <= 3'd0;
|
8090 |
48 |
robfinch |
// adr_o <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
8091 |
|
|
// L2_adr <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
|
8092 |
|
|
adr_o <= {pcr[5:0],L1_adr[31:5],5'h0};
|
8093 |
|
|
ol_o <= ol[0];
|
8094 |
|
|
L2_adr <= {pcr[5:0],L1_adr[31:5],5'h0};
|
8095 |
|
|
L2_xsel <= 1'b0;
|
8096 |
|
|
bstate <= B7;
|
8097 |
|
|
end
|
8098 |
|
|
end
|
8099 |
|
|
// Terminal state for a store operation.
|
8100 |
49 |
robfinch |
// Note that if only a single memory channel is selected, bwhich will be a
|
8101 |
|
|
// constant 0. This should cause the extra code to be removed.
|
8102 |
48 |
robfinch |
B1:
|
8103 |
|
|
if (acki|err_i) begin
|
8104 |
|
|
isStore <= `TRUE;
|
8105 |
|
|
cyc_o <= `LOW;
|
8106 |
|
|
stb_o <= `LOW;
|
8107 |
|
|
we_o <= `LOW;
|
8108 |
|
|
sel_o <= 8'h00;
|
8109 |
|
|
cr_o <= 1'b0;
|
8110 |
|
|
// This isn't a good way of doing things; the state should be propagated
|
8111 |
|
|
// to the commit stage, however since this is a store we know there will
|
8112 |
|
|
// be no change of program flow. So the reservation status bit is set
|
8113 |
|
|
// here. The author wanted to avoid the complexity of propagating the
|
8114 |
|
|
// input signal to the commit stage. It does mean that the SWC
|
8115 |
|
|
// instruction should be surrounded by SYNC's.
|
8116 |
|
|
if (cr_o)
|
8117 |
|
|
sema[0] <= rbi_i;
|
8118 |
49 |
robfinch |
`ifdef HAS_WB
|
8119 |
|
|
for (n = 0; n < QENTRIES; n = n + 1) begin
|
8120 |
|
|
if (wbo_id[n]) begin
|
8121 |
|
|
iqentry_exc[n] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
8122 |
|
|
if (err_i|wrv_i) begin
|
8123 |
|
|
iqentry_a1[n] <= adr_o;
|
8124 |
|
|
wb_v <= 8'h00; // Invalidate write buffer if there is a problem with the store
|
8125 |
|
|
wb_en <= `FALSE; // and disable write buffer
|
8126 |
|
|
end
|
8127 |
|
|
iqentry_cmt[n] <= `VAL;
|
8128 |
|
|
iqentry_aq[n] <= `INV;
|
8129 |
|
|
end
|
8130 |
|
|
end
|
8131 |
|
|
`else
|
8132 |
48 |
robfinch |
case(bwhich)
|
8133 |
49 |
robfinch |
2'd0: if (mem1_available) begin
|
8134 |
48 |
robfinch |
dram0 <= `DRAMREQ_READY;
|
8135 |
|
|
iqentry_exc[dram0_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
8136 |
|
|
if (err_i|wrv_i) iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
8137 |
49 |
robfinch |
iqentry_cmt[ dram0_id[`QBITS] ] <= `VAL;
|
8138 |
|
|
iqentry_aq[ dram0_id[`QBITS] ] <= `INV;
|
8139 |
48 |
robfinch |
//iqentry_out[ dram0_id[`QBITS] ] <= `INV;
|
8140 |
|
|
end
|
8141 |
49 |
robfinch |
2'd1: if (`NUM_MEM > 1) begin
|
8142 |
48 |
robfinch |
dram1 <= `DRAMREQ_READY;
|
8143 |
|
|
iqentry_exc[dram1_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
8144 |
|
|
if (err_i|wrv_i) iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
8145 |
49 |
robfinch |
iqentry_cmt[ dram1_id[`QBITS] ] <= `VAL;
|
8146 |
|
|
iqentry_aq[ dram1_id[`QBITS] ] <= `INV;
|
8147 |
48 |
robfinch |
//iqentry_out[ dram1_id[`QBITS] ] <= `INV;
|
8148 |
|
|
end
|
8149 |
49 |
robfinch |
2'd2: if (`NUM_MEM > 2) begin
|
8150 |
48 |
robfinch |
dram2 <= `DRAMREQ_READY;
|
8151 |
|
|
iqentry_exc[dram2_id[`QBITS]] <= wrv_i|err_i ? `FLT_DWF : `FLT_NONE;
|
8152 |
|
|
if (err_i|wrv_i) iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
8153 |
49 |
robfinch |
iqentry_cmt[ dram2_id[`QBITS] ] <= `VAL;
|
8154 |
|
|
iqentry_aq[ dram2_id[`QBITS] ] <= `INV;
|
8155 |
48 |
robfinch |
//iqentry_out[ dram2_id[`QBITS] ] <= `INV;
|
8156 |
|
|
end
|
8157 |
|
|
default: ;
|
8158 |
|
|
endcase
|
8159 |
49 |
robfinch |
`endif
|
8160 |
48 |
robfinch |
bstate <= B19;
|
8161 |
|
|
end
|
8162 |
|
|
B2:
|
8163 |
|
|
begin
|
8164 |
|
|
dccnt <= 2'd0;
|
8165 |
|
|
case(bwhich)
|
8166 |
|
|
2'd0: begin
|
8167 |
|
|
cti_o <= 3'b001;
|
8168 |
|
|
bte_o <= 2'b01;
|
8169 |
|
|
cyc_o <= `HIGH;
|
8170 |
|
|
stb_o <= `HIGH;
|
8171 |
|
|
sel_o <= fnSelect(dram0_instr,dram0_addr);
|
8172 |
|
|
adr_o <= {dram0_addr[31:5],5'b0};
|
8173 |
|
|
ol_o <= dram0_ol;
|
8174 |
|
|
bstate <= B2d;
|
8175 |
|
|
end
|
8176 |
49 |
robfinch |
2'd1: if (`NUM_MEM > 1) begin
|
8177 |
48 |
robfinch |
cti_o <= 3'b001;
|
8178 |
|
|
bte_o <= 2'b01;
|
8179 |
|
|
cyc_o <= `HIGH;
|
8180 |
|
|
stb_o <= `HIGH;
|
8181 |
|
|
sel_o <= fnSelect(dram1_instr,dram1_addr);
|
8182 |
|
|
adr_o <= {dram1_addr[31:5],5'b0};
|
8183 |
|
|
ol_o <= dram1_ol;
|
8184 |
|
|
bstate <= B2d;
|
8185 |
|
|
end
|
8186 |
49 |
robfinch |
2'd2: if (`NUM_MEM > 2) begin
|
8187 |
48 |
robfinch |
cti_o <= 3'b001;
|
8188 |
|
|
bte_o <= 2'b01;
|
8189 |
|
|
cyc_o <= `HIGH;
|
8190 |
|
|
stb_o <= `HIGH;
|
8191 |
|
|
sel_o <= fnSelect(dram2_instr,dram2_addr);
|
8192 |
|
|
adr_o <= {dram2_addr[31:5],5'b0};
|
8193 |
|
|
ol_o <= dram2_ol;
|
8194 |
|
|
bstate <= B2d;
|
8195 |
|
|
end
|
8196 |
|
|
default: if (~acki) bstate <= BIDLE;
|
8197 |
|
|
endcase
|
8198 |
|
|
end
|
8199 |
|
|
// Data cache load terminal state
|
8200 |
|
|
B2d:
|
8201 |
|
|
if (ack_i|err_i) begin
|
8202 |
|
|
errq <= errq | err_i;
|
8203 |
|
|
rdvq <= rdvq | rdv_i;
|
8204 |
|
|
if (!preload) // A preload instruction ignores any error
|
8205 |
|
|
case(bwhich)
|
8206 |
|
|
2'd0: if (err_i|rdv_i) begin
|
8207 |
|
|
iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
8208 |
|
|
iqentry_exc[dram0_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
8209 |
|
|
end
|
8210 |
49 |
robfinch |
2'd1: if ((err_i|rdv_i) && `NUM_MEM > 1) begin
|
8211 |
48 |
robfinch |
iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
8212 |
|
|
iqentry_exc[dram1_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
8213 |
|
|
end
|
8214 |
49 |
robfinch |
2'd2: if ((err_i|rdv_i) && `NUM_MEM > 2) begin
|
8215 |
48 |
robfinch |
iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
8216 |
|
|
iqentry_exc[dram2_id[`QBITS]] <= err_i ? `FLT_DBE : `FLT_DRF;
|
8217 |
|
|
end
|
8218 |
|
|
default: ;
|
8219 |
|
|
endcase
|
8220 |
|
|
dccnt <= dccnt + 2'd1;
|
8221 |
|
|
adr_o[4:3] <= adr_o[4:3] + 2'd1;
|
8222 |
|
|
bstate <= B2d;
|
8223 |
|
|
if (dccnt==2'd2)
|
8224 |
|
|
cti_o <= 3'b111;
|
8225 |
|
|
if (dccnt==2'd3) begin
|
8226 |
|
|
cti_o <= 3'b000;
|
8227 |
|
|
bte_o <= 2'b00;
|
8228 |
|
|
cyc_o <= `LOW;
|
8229 |
|
|
stb_o <= `LOW;
|
8230 |
|
|
sel_o <= 8'h00;
|
8231 |
|
|
bstate <= B4;
|
8232 |
|
|
end
|
8233 |
|
|
end
|
8234 |
|
|
B3: begin
|
8235 |
|
|
stb_o <= `HIGH;
|
8236 |
|
|
bstate <= B2d;
|
8237 |
|
|
end
|
8238 |
|
|
B4: bstate <= B5;
|
8239 |
|
|
B5: bstate <= B6;
|
8240 |
|
|
B6: begin
|
8241 |
|
|
case(bwhich)
|
8242 |
|
|
2'd0: dram0 <= `DRAMSLOT_BUSY; // causes retest of dhit
|
8243 |
|
|
2'd1: dram1 <= `DRAMSLOT_BUSY;
|
8244 |
|
|
2'd2: dram2 <= `DRAMSLOT_BUSY;
|
8245 |
|
|
default: ;
|
8246 |
|
|
endcase
|
8247 |
|
|
if (~ack_i) bstate <= BIDLE;
|
8248 |
|
|
end
|
8249 |
|
|
|
8250 |
|
|
// Ack state for instruction cache load
|
8251 |
|
|
B7:
|
8252 |
|
|
if (ack_i|err_i) begin
|
8253 |
|
|
errq <= errq | err_i;
|
8254 |
|
|
exvq <= exvq | exv_i;
|
8255 |
49 |
robfinch |
// L1_en <= 9'h3 << {L2_xsel,L2_adr[4:3],1'b0};
|
8256 |
48 |
robfinch |
// L1_wr0 <= `TRUE;
|
8257 |
|
|
// L1_wr1 <= `TRUE;
|
8258 |
|
|
// L1_adr <= L2_adr;
|
8259 |
|
|
if (err_i)
|
8260 |
49 |
robfinch |
L2_rdat <= {9{11'b0,4'd7,1'b0,`FLT_IBE,2'b00,`BRK}};
|
8261 |
48 |
robfinch |
else
|
8262 |
49 |
robfinch |
L2_rdat <= {dat_i[31:0],{4{dat_i}}};
|
8263 |
48 |
robfinch |
iccnt <= iccnt + 3'd1;
|
8264 |
|
|
//stb_o <= `LOW;
|
8265 |
|
|
if (iccnt==3'd3)
|
8266 |
|
|
cti_o <= 3'b111;
|
8267 |
|
|
if (iccnt==3'd4) begin
|
8268 |
|
|
cti_o <= 3'b000;
|
8269 |
|
|
bte_o <= 2'b00; // linear burst
|
8270 |
|
|
cyc_o <= `LOW;
|
8271 |
|
|
stb_o <= `LOW;
|
8272 |
|
|
sel_o <= 8'h00;
|
8273 |
|
|
icl_o <= `LOW;
|
8274 |
|
|
bstate <= B9;
|
8275 |
|
|
end
|
8276 |
|
|
else begin
|
8277 |
|
|
L2_adr[4:3] <= L2_adr[4:3] + 2'd1;
|
8278 |
|
|
if (L2_adr[4:3]==2'b11)
|
8279 |
|
|
L2_xsel <= 1'b1;
|
8280 |
|
|
end
|
8281 |
|
|
end
|
8282 |
|
|
B9:
|
8283 |
|
|
begin
|
8284 |
|
|
L1_wr0 <= `FALSE;
|
8285 |
|
|
L1_wr1 <= `FALSE;
|
8286 |
49 |
robfinch |
L1_wr2 <= `FALSE;
|
8287 |
|
|
L1_en <= 9'h1FF;
|
8288 |
48 |
robfinch |
L2_xsel <= 1'b0;
|
8289 |
|
|
if (~ack_i) begin
|
8290 |
|
|
bstate <= BIDLE;
|
8291 |
|
|
L2_nxt <= TRUE;
|
8292 |
|
|
end
|
8293 |
|
|
end
|
8294 |
|
|
B12:
|
8295 |
|
|
if (ack_i|err_i) begin
|
8296 |
|
|
if (isCAS) begin
|
8297 |
|
|
iqentry_res [ casid[`QBITS] ] <= (dat_i == cas);
|
8298 |
|
|
iqentry_exc [ casid[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
8299 |
|
|
iqentry_done[ casid[`QBITS] ] <= `VAL;
|
8300 |
|
|
iqentry_instr[ casid[`QBITS]] <= `NOP_INSN;
|
8301 |
|
|
iqentry_out [ casid[`QBITS] ] <= `INV;
|
8302 |
|
|
if (err_i | rdv_i) iqentry_a1[casid[`QBITS]] <= adr_o;
|
8303 |
|
|
if (dat_i == cas) begin
|
8304 |
|
|
stb_o <= `LOW;
|
8305 |
|
|
we_o <= `TRUE;
|
8306 |
|
|
bstate <= B15;
|
8307 |
|
|
end
|
8308 |
|
|
else begin
|
8309 |
|
|
cas <= dat_i;
|
8310 |
|
|
cyc_o <= `LOW;
|
8311 |
|
|
stb_o <= `LOW;
|
8312 |
|
|
sel_o <= 8'h00;
|
8313 |
|
|
case(bwhich)
|
8314 |
|
|
2'b00: dram0 <= `DRAMREQ_READY;
|
8315 |
|
|
2'b01: dram1 <= `DRAMREQ_READY;
|
8316 |
|
|
2'b10: dram2 <= `DRAMREQ_READY;
|
8317 |
|
|
default: ;
|
8318 |
|
|
endcase
|
8319 |
|
|
bstate <= B19;
|
8320 |
|
|
end
|
8321 |
|
|
end
|
8322 |
|
|
else if (isRMW) begin
|
8323 |
|
|
rmw_instr <= iqentry_instr[casid[`QBITS]];
|
8324 |
|
|
rmw_argA <= dat_i;
|
8325 |
|
|
if (isSpt) begin
|
8326 |
|
|
rmw_argB <= 64'd1 << iqentry_a1[casid[`QBITS]][63:58];
|
8327 |
|
|
rmw_argC <= iqentry_instr[casid[`QBITS]][5:0]==`R2 ?
|
8328 |
|
|
iqentry_a3[casid[`QBITS]][64] << iqentry_a1[casid[`QBITS]][63:58] :
|
8329 |
|
|
iqentry_a2[casid[`QBITS]][64] << iqentry_a1[casid[`QBITS]][63:58];
|
8330 |
|
|
end
|
8331 |
|
|
else if (isInc) begin
|
8332 |
|
|
rmw_argB <= iqentry_instr[casid[`QBITS]][5:0]==`R2 ? {{59{iqentry_instr[casid[`QBITS]][22]}},iqentry_instr[casid[`QBITS]][22:18]} :
|
8333 |
|
|
{{59{iqentry_instr[casid[`QBITS]][17]}},iqentry_instr[casid[`QBITS]][17:13]};
|
8334 |
|
|
end
|
8335 |
|
|
else begin // isAMO
|
8336 |
|
|
iqentry_res [ casid[`QBITS] ] <= dat_i;
|
8337 |
|
|
rmw_argB <= iqentry_instr[casid[`QBITS]][31] ? {{59{iqentry_instr[casid[`QBITS]][20:16]}},iqentry_instr[casid[`QBITS]][20:16]} : iqentry_a2[casid[`QBITS]];
|
8338 |
|
|
end
|
8339 |
|
|
iqentry_exc [ casid[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
8340 |
|
|
if (err_i | rdv_i) iqentry_a1[casid[`QBITS]] <= adr_o;
|
8341 |
|
|
stb_o <= `LOW;
|
8342 |
|
|
bstate <= B20;
|
8343 |
|
|
end
|
8344 |
|
|
else begin
|
8345 |
|
|
cyc_o <= `LOW;
|
8346 |
|
|
stb_o <= `LOW;
|
8347 |
|
|
sel_o <= 8'h00;
|
8348 |
|
|
sr_o <= `LOW;
|
8349 |
|
|
xdati <= dat_i;
|
8350 |
|
|
case(bwhich)
|
8351 |
|
|
2'b00: begin
|
8352 |
|
|
dram0 <= `DRAMREQ_READY;
|
8353 |
|
|
iqentry_exc [ dram0_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
8354 |
|
|
if (err_i|rdv_i) iqentry_a1[dram0_id[`QBITS]] <= adr_o;
|
8355 |
|
|
end
|
8356 |
49 |
robfinch |
2'b01: if (`NUM_MEM > 1) begin
|
8357 |
48 |
robfinch |
dram1 <= `DRAMREQ_READY;
|
8358 |
|
|
iqentry_exc [ dram1_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
8359 |
|
|
if (err_i|rdv_i) iqentry_a1[dram1_id[`QBITS]] <= adr_o;
|
8360 |
|
|
end
|
8361 |
49 |
robfinch |
2'b10: if (`NUM_MEM > 2) begin
|
8362 |
48 |
robfinch |
dram2 <= `DRAMREQ_READY;
|
8363 |
|
|
iqentry_exc [ dram2_id[`QBITS] ] <= err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
|
8364 |
|
|
if (err_i|rdv_i) iqentry_a1[dram2_id[`QBITS]] <= adr_o;
|
8365 |
|
|
end
|
8366 |
|
|
default: ;
|
8367 |
|
|
endcase
|
8368 |
|
|
bstate <= B19;
|
8369 |
|
|
end
|
8370 |
|
|
end
|
8371 |
|
|
// Three cycles to detemrine if there's a cache hit during a store.
|
8372 |
|
|
B16: begin
|
8373 |
|
|
case(bwhich)
|
8374 |
|
|
2'd0: if (dhit0) begin dram0 <= `DRAMREQ_READY; bstate <= B17; end
|
8375 |
|
|
2'd1: if (dhit1) begin dram1 <= `DRAMREQ_READY; bstate <= B17; end
|
8376 |
|
|
2'd2: if (dhit2) begin dram2 <= `DRAMREQ_READY; bstate <= B17; end
|
8377 |
|
|
default: bstate <= BIDLE;
|
8378 |
|
|
endcase
|
8379 |
|
|
end
|
8380 |
|
|
B17: bstate <= B18;
|
8381 |
|
|
B18: bstate <= B19;
|
8382 |
|
|
B19: if (~acki) begin bstate <= BIDLE; isStore <= `FALSE; end
|
8383 |
|
|
B20:
|
8384 |
|
|
if (~ack_i) begin
|
8385 |
|
|
stb_o <= `HIGH;
|
8386 |
|
|
we_o <= `HIGH;
|
8387 |
|
|
dat_o <= fnDato(rmw_instr,rmw_res);
|
8388 |
|
|
bstate <= B1;
|
8389 |
|
|
end
|
8390 |
|
|
B21:
|
8391 |
|
|
if (~ack_i) begin
|
8392 |
|
|
stb_o <= `HIGH;
|
8393 |
|
|
bstate <= B12;
|
8394 |
|
|
end
|
8395 |
|
|
default: bstate <= BIDLE;
|
8396 |
|
|
endcase
|
8397 |
|
|
|
8398 |
|
|
if (!branchmiss) begin
|
8399 |
|
|
case({fetchbuf0_v, fetchbuf1_v})
|
8400 |
|
|
2'b00: ;
|
8401 |
|
|
2'b01:
|
8402 |
|
|
if (canq1) begin
|
8403 |
|
|
tail0 <= idp1(tail0);
|
8404 |
|
|
tail1 <= idp1(tail1);
|
8405 |
|
|
end
|
8406 |
|
|
2'b10:
|
8407 |
|
|
if (canq1) begin
|
8408 |
|
|
tail0 <= idp1(tail0);
|
8409 |
|
|
tail1 <= idp1(tail1);
|
8410 |
|
|
end
|
8411 |
|
|
2'b11:
|
8412 |
|
|
if (canq1) begin
|
8413 |
|
|
if (IsBranch(fetchbuf0_instr) && predict_taken0 && fetchbuf0_thrd==fetchbuf1_thrd) begin
|
8414 |
|
|
tail0 <= idp1(tail0);
|
8415 |
|
|
tail1 <= idp1(tail1);
|
8416 |
|
|
end
|
8417 |
|
|
else begin
|
8418 |
|
|
if (vqe0 < vl || !IsVector(fetchbuf0_instr)) begin
|
8419 |
|
|
if (canq2) begin
|
8420 |
|
|
tail0 <= idp2(tail0);
|
8421 |
|
|
tail1 <= idp2(tail1);
|
8422 |
|
|
end
|
8423 |
|
|
else begin // queued1 will be true
|
8424 |
|
|
tail0 <= idp1(tail0);
|
8425 |
|
|
tail1 <= idp1(tail1);
|
8426 |
|
|
end
|
8427 |
|
|
end
|
8428 |
|
|
end
|
8429 |
|
|
end
|
8430 |
|
|
endcase
|
8431 |
|
|
end
|
8432 |
|
|
`ifndef SUPPORT_SMT
|
8433 |
|
|
else begin // if branchmiss
|
8434 |
|
|
if (iqentry_stomp[0] & ~iqentry_stomp[7]) begin
|
8435 |
|
|
tail0 <= 3'd0;
|
8436 |
|
|
tail1 <= 3'd1;
|
8437 |
|
|
end
|
8438 |
|
|
else if (iqentry_stomp[1] & ~iqentry_stomp[0]) begin
|
8439 |
|
|
tail0 <= 3'd1;
|
8440 |
|
|
tail1 <= 3'd2;
|
8441 |
|
|
end
|
8442 |
|
|
else if (iqentry_stomp[2] & ~iqentry_stomp[1]) begin
|
8443 |
|
|
tail0 <= 3'd2;
|
8444 |
|
|
tail1 <= 3'd3;
|
8445 |
|
|
end
|
8446 |
|
|
else if (iqentry_stomp[3] & ~iqentry_stomp[2]) begin
|
8447 |
|
|
tail0 <= 3'd3;
|
8448 |
|
|
tail1 <= 3'd4;
|
8449 |
|
|
end
|
8450 |
|
|
else if (iqentry_stomp[4] & ~iqentry_stomp[3]) begin
|
8451 |
|
|
tail0 <= 3'd4;
|
8452 |
|
|
tail1 <= 3'd5;
|
8453 |
|
|
end
|
8454 |
|
|
else if (iqentry_stomp[5] & ~iqentry_stomp[4]) begin
|
8455 |
|
|
tail0 <= 3'd5;
|
8456 |
|
|
tail1 <= 3'd6;
|
8457 |
|
|
end
|
8458 |
|
|
else if (iqentry_stomp[6] & ~iqentry_stomp[5]) begin
|
8459 |
|
|
tail0 <= 3'd6;
|
8460 |
|
|
tail1 <= 3'd7;
|
8461 |
|
|
end
|
8462 |
|
|
else if (iqentry_stomp[7] & ~iqentry_stomp[6]) begin
|
8463 |
|
|
tail0 <= 3'd7;
|
8464 |
|
|
tail1 <= 3'd0;
|
8465 |
|
|
end
|
8466 |
|
|
// otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
|
8467 |
|
|
end
|
8468 |
|
|
`endif
|
8469 |
51 |
robfinch |
|
8470 |
48 |
robfinch |
/*
|
8471 |
|
|
if (pebm)
|
8472 |
|
|
seq_num <= seq_num + 5'd3;
|
8473 |
|
|
else if (queued2)
|
8474 |
|
|
seq_num <= seq_num + 5'd2;
|
8475 |
|
|
else if (queued1)
|
8476 |
|
|
seq_num <= seq_num + 5'd1;
|
8477 |
|
|
*/
|
8478 |
|
|
// #5 rf[0] = 0; rf_v[0] = 1; rf_source[0] = 0;
|
8479 |
51 |
robfinch |
`ifdef SIM
|
8480 |
48 |
robfinch |
$display("\n\n\n\n\n\n\n\n");
|
8481 |
|
|
$display("TIME %0d", $time);
|
8482 |
|
|
$display("%h #", pc0);
|
8483 |
|
|
`ifdef SUPPORT_SMT
|
8484 |
|
|
$display ("Regfile: %d", rgs[0]);
|
8485 |
|
|
for (n=0; n < 32; n=n+4) begin
|
8486 |
|
|
$display("%d: %h %d %o %d: %h %d %o %d: %h %d %o %d: %h %d %o#",
|
8487 |
|
|
n[4:0]+0, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
|
8488 |
|
|
n[4:0]+1, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
|
8489 |
|
|
n[4:0]+2, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
|
8490 |
|
|
n[4:0]+3, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
|
8491 |
|
|
);
|
8492 |
|
|
end
|
8493 |
|
|
$display ("Regfile: %d", rgs[1]);
|
8494 |
|
|
for (n=128; n < 160; n=n+4) begin
|
8495 |
|
|
$display("%d: %h %d %o %d: %h %d %o %d: %h %d %o %d: %h %d %o#",
|
8496 |
|
|
n[4:0]+0, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
|
8497 |
|
|
n[4:0]+1, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
|
8498 |
|
|
n[4:0]+2, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
|
8499 |
|
|
n[4:0]+3, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
|
8500 |
|
|
);
|
8501 |
|
|
end
|
8502 |
|
|
`else
|
8503 |
|
|
$display ("Regfile: %d", rgs);
|
8504 |
|
|
for (n=0; n < 32; n=n+4) begin
|
8505 |
|
|
$display("%d: %h %d %o %d: %h %d %o %d: %h %d %o %d: %h %d %o#",
|
8506 |
|
|
n[4:0]+0, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
|
8507 |
|
|
n[4:0]+1, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
|
8508 |
|
|
n[4:0]+2, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
|
8509 |
|
|
n[4:0]+3, urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
|
8510 |
|
|
);
|
8511 |
|
|
end
|
8512 |
|
|
`endif
|
8513 |
49 |
robfinch |
`ifdef FCU_ENH
|
8514 |
48 |
robfinch |
$display("Call Stack:");
|
8515 |
49 |
robfinch |
for (n = 0; n < 16; n = n + 4)
|
8516 |
48 |
robfinch |
$display("%c%d: %h %c%d: %h %c%d: %h %c%d: %h",
|
8517 |
|
|
ufb1.ursb1.rasp==n+0 ?">" : " ", n[4:0]+0, ufb1.ursb1.ras[n+0],
|
8518 |
|
|
ufb1.ursb1.rasp==n+1 ?">" : " ", n[4:0]+1, ufb1.ursb1.ras[n+1],
|
8519 |
|
|
ufb1.ursb1.rasp==n+2 ?">" : " ", n[4:0]+2, ufb1.ursb1.ras[n+2],
|
8520 |
|
|
ufb1.ursb1.rasp==n+3 ?">" : " ", n[4:0]+3, ufb1.ursb1.ras[n+3]
|
8521 |
|
|
);
|
8522 |
|
|
$display("\n");
|
8523 |
49 |
robfinch |
`endif
|
8524 |
48 |
robfinch |
// $display("Return address stack:");
|
8525 |
|
|
// for (n = 0; n < 16; n = n + 1)
|
8526 |
|
|
// $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
|
8527 |
|
|
$display("TakeBr:%d #", take_branch);//, backpc);
|
8528 |
51 |
robfinch |
$display("Insn%d: %h", 0, insn0);
|
8529 |
|
|
if (`WAYS > 1)
|
8530 |
|
|
$display("Insn%d: %h", 1, insn1);
|
8531 |
48 |
robfinch |
$display("%c%c A: %d %h %h #",
|
8532 |
|
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
|
8533 |
|
|
$display("%c%c B: %d %h %h #",
|
8534 |
|
|
45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
|
8535 |
|
|
$display("%c%c C: %d %h %h #",
|
8536 |
|
|
45, fetchbuf?62:45, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
|
8537 |
|
|
$display("%c%c D: %d %h %h #",
|
8538 |
|
|
45, fetchbuf?62:45, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
|
8539 |
|
|
|
8540 |
|
|
for (i=0; i<QENTRIES; i=i+1)
|
8541 |
|
|
$display("%c%c %d: %c%c%c%c %d %d %c%c %c %c%h %d %o %h %h %h %d %o %h %d %o %h %d %o %d:%h %h %d#",
|
8542 |
|
|
(i[`QBITS]==head0)?"C":".",
|
8543 |
|
|
(i[`QBITS]==tail0)?"Q":".",
|
8544 |
|
|
i[`QBITS],
|
8545 |
|
|
iqentry_v[i] ? "v" : "-",
|
8546 |
|
|
iqentry_iv[i] ? "I" : "-",
|
8547 |
|
|
iqentry_done[i]?"d":"-",
|
8548 |
|
|
iqentry_out[i]?"o":"-",
|
8549 |
|
|
iqentry_bt[i],
|
8550 |
|
|
iqentry_memissue[i],
|
8551 |
|
|
iqentry_agen[i] ? "a": "-",
|
8552 |
|
|
iqentry_alu0_issue[i]?"0":iqentry_alu1_issue[i]?"1":"-",
|
8553 |
|
|
iqentry_stomp[i]?"s":"-",
|
8554 |
|
|
iqentry_fc[i] ? "F" : iqentry_mem[i] ? "M" : (iqentry_alu[i]==1'b1) ? "a" : (iqentry_alu[i]==1'bx) ? "X" : iqentry_fpu[i] ? "f" : "O",
|
8555 |
|
|
iqentry_instr[i], iqentry_tgt[i][4:0],
|
8556 |
|
|
iqentry_exc[i], iqentry_res[i], iqentry_a0[i], iqentry_a1[i], iqentry_a1_v[i],
|
8557 |
|
|
iqentry_a1_s[i],
|
8558 |
|
|
iqentry_a2[i], iqentry_a2_v[i], iqentry_a2_s[i],
|
8559 |
|
|
iqentry_a3[i], iqentry_a3_v[i], iqentry_a3_s[i],
|
8560 |
|
|
iqentry_thrd[i],
|
8561 |
|
|
iqentry_pc[i],
|
8562 |
|
|
iqentry_sn[i], iqentry_ven[i]
|
8563 |
|
|
);
|
8564 |
|
|
$display("DRAM");
|
8565 |
|
|
$display("%d %h %h %c%h %o #",
|
8566 |
|
|
dram0, dram0_addr, dram0_data, (IsFlowCtrl(dram0_instr) ? 98 : (IsMem(dram0_instr)) ? 109 : 97),
|
8567 |
|
|
dram0_instr, dram0_id);
|
8568 |
49 |
robfinch |
if (`NUM_MEM > 1)
|
8569 |
48 |
robfinch |
$display("%d %h %h %c%h %o #",
|
8570 |
|
|
dram1, dram1_addr, dram1_data, (IsFlowCtrl(dram1_instr) ? 98 : (IsMem(dram1_instr)) ? 109 : 97),
|
8571 |
|
|
dram1_instr, dram1_id);
|
8572 |
49 |
robfinch |
if (`NUM_MEM > 2)
|
8573 |
48 |
robfinch |
$display("%d %h %h %c%h %o #",
|
8574 |
|
|
dram2, dram2_addr, dram2_data, (IsFlowCtrl(dram2_instr) ? 98 : (IsMem(dram2_instr)) ? 109 : 97),
|
8575 |
|
|
dram2_instr, dram2_id);
|
8576 |
|
|
$display("%d %h %o %h #", dramA_v, dramA_bus, dramA_id, dramA_exc);
|
8577 |
49 |
robfinch |
if (`NUM_MEM > 1)
|
8578 |
48 |
robfinch |
$display("%d %h %o %h #", dramB_v, dramB_bus, dramB_id, dramB_exc);
|
8579 |
49 |
robfinch |
if (`NUM_MEM > 2)
|
8580 |
48 |
robfinch |
$display("%d %h %o %h #", dramC_v, dramC_bus, dramC_id, dramC_exc);
|
8581 |
|
|
$display("ALU");
|
8582 |
|
|
$display("%d %h %h %h %c%h %d %o %h #",
|
8583 |
|
|
alu0_dataready, alu0_argI, alu0_argA, alu0_argB,
|
8584 |
|
|
(IsFlowCtrl(alu0_instr) ? 98 : IsMem(alu0_instr) ? 109 : 97),
|
8585 |
|
|
alu0_instr, alu0_bt, alu0_sourceid, alu0_pc);
|
8586 |
|
|
$display("%d %h %o 0 #", alu0_v, alu0_bus, alu0_id);
|
8587 |
49 |
robfinch |
if (`NUM_ALU > 1) begin
|
8588 |
|
|
$display("%d %h %h %h %c%h %d %o %h #",
|
8589 |
|
|
alu1_dataready, alu1_argI, alu1_argA, alu1_argB,
|
8590 |
|
|
(IsFlowCtrl(alu1_instr) ? 98 : IsMem(alu1_instr) ? 109 : 97),
|
8591 |
|
|
alu1_instr, alu1_bt, alu1_sourceid, alu1_pc);
|
8592 |
|
|
$display("%d %h %o 0 #", alu1_v, alu1_bus, alu1_id);
|
8593 |
|
|
end
|
8594 |
48 |
robfinch |
$display("FCU");
|
8595 |
|
|
$display("%d %h %h %h %h #", fcu_v, fcu_bus, fcu_argI, fcu_argA, fcu_argB);
|
8596 |
|
|
$display("%c %h %h #", fcu_branchmiss?"m":" ", fcu_sourceid, fcu_misspc);
|
8597 |
|
|
$display("Commit");
|
8598 |
|
|
$display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
|
8599 |
|
|
$display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
|
8600 |
|
|
$display("instructions committed: %d ticks: %d ", I, tick);
|
8601 |
49 |
robfinch |
$display("Write merges: %d", wb_merges);
|
8602 |
51 |
robfinch |
`endif // SIM
|
8603 |
48 |
robfinch |
|
8604 |
|
|
//
|
8605 |
|
|
// $display("\n\n\n\n\n\n\n\n");
|
8606 |
|
|
// $display("TIME %0d", $time);
|
8607 |
|
|
// $display(" pc0=%h", pc0);
|
8608 |
|
|
// $display(" pc1=%h", pc1);
|
8609 |
|
|
// $display(" reg0=%h, v=%d, src=%o", rf[0], rf_v[0], rf_source[0]);
|
8610 |
|
|
// $display(" reg1=%h, v=%d, src=%o", rf[1], rf_v[1], rf_source[1]);
|
8611 |
|
|
// $display(" reg2=%h, v=%d, src=%o", rf[2], rf_v[2], rf_source[2]);
|
8612 |
|
|
// $display(" reg3=%h, v=%d, src=%o", rf[3], rf_v[3], rf_source[3]);
|
8613 |
|
|
// $display(" reg4=%h, v=%d, src=%o", rf[4], rf_v[4], rf_source[4]);
|
8614 |
|
|
// $display(" reg5=%h, v=%d, src=%o", rf[5], rf_v[5], rf_source[5]);
|
8615 |
|
|
// $display(" reg6=%h, v=%d, src=%o", rf[6], rf_v[6], rf_source[6]);
|
8616 |
|
|
// $display(" reg7=%h, v=%d, src=%o", rf[7], rf_v[7], rf_source[7]);
|
8617 |
|
|
|
8618 |
|
|
// $display("Fetch Buffers:");
|
8619 |
|
|
// $display(" %c%c fbA: v=%d instr=%h pc=%h %c%c fbC: v=%d instr=%h pc=%h",
|
8620 |
|
|
// fetchbuf?32:45, fetchbuf?32:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc,
|
8621 |
|
|
// fetchbuf?45:32, fetchbuf?62:32, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
|
8622 |
|
|
// $display(" %c%c fbB: v=%d instr=%h pc=%h %c%c fbD: v=%d instr=%h pc=%h",
|
8623 |
|
|
// fetchbuf?32:45, fetchbuf?32:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc,
|
8624 |
|
|
// fetchbuf?45:32, fetchbuf?62:32, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
|
8625 |
|
|
// $display(" branchback=%d backpc=%h", branchback, backpc);
|
8626 |
|
|
|
8627 |
|
|
// $display("Instruction Queue:");
|
8628 |
|
|
// for (i=0; i<8; i=i+1)
|
8629 |
|
|
// $display(" %c%c%d: v=%d done=%d out=%d agen=%d res=%h op=%d bt=%d tgt=%d a1=%h (v=%d/s=%o) a2=%h (v=%d/s=%o) im=%h pc=%h exc=%h",
|
8630 |
|
|
// (i[`QBITS]==head0)?72:32, (i[`QBITS]==tail0)?84:32, i,
|
8631 |
|
|
// iqentry_v[i], iqentry_done[i], iqentry_out[i], iqentry_agen[i], iqentry_res[i], iqentry_op[i],
|
8632 |
|
|
// iqentry_bt[i], iqentry_tgt[i], iqentry_a1[i], iqentry_a1_v[i], iqentry_a1_s[i], iqentry_a2[i], iqentry_a2_v[i],
|
8633 |
|
|
// iqentry_a2_s[i], iqentry_a0[i], iqentry_pc[i], iqentry_exc[i]);
|
8634 |
|
|
|
8635 |
|
|
// $display("Scheduling Status:");
|
8636 |
|
|
// $display(" iqentry0 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8637 |
|
|
// iqentry_0_issue, iqentry_0_islot, iqentry_stomp[0], iqentry_source[0], iqentry_memready[0], iqentry_memissue[0]);
|
8638 |
|
|
// $display(" iqentry1 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8639 |
|
|
// iqentry_1_issue, iqentry_1_islot, iqentry_stomp[1], iqentry_source[1], iqentry_memready[1], iqentry_memissue[1]);
|
8640 |
|
|
// $display(" iqentry2 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8641 |
|
|
// iqentry_2_issue, iqentry_2_islot, iqentry_stomp[2], iqentry_source[2], iqentry_memready[2], iqentry_memissue[2]);
|
8642 |
|
|
// $display(" iqentry3 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8643 |
|
|
// iqentry_3_issue, iqentry_3_islot, iqentry_stomp[3], iqentry_source[3], iqentry_memready[3], iqentry_memissue[3]);
|
8644 |
|
|
// $display(" iqentry4 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8645 |
|
|
// iqentry_4_issue, iqentry_4_islot, iqentry_stomp[4], iqentry_source[4], iqentry_memready[4], iqentry_memissue[4]);
|
8646 |
|
|
// $display(" iqentry5 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8647 |
|
|
// iqentry_5_issue, iqentry_5_islot, iqentry_stomp[5], iqentry_source[5], iqentry_memready[5], iqentry_memissue[5]);
|
8648 |
|
|
// $display(" iqentry6 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8649 |
|
|
// iqentry_6_issue, iqentry_6_islot, iqentry_stomp[6], iqentry_source[6], iqentry_memready[6], iqentry_memissue[6]);
|
8650 |
|
|
// $display(" iqentry7 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
|
8651 |
|
|
// iqentry_7_issue, iqentry_7_islot, iqentry_stomp[7], iqentry_source[7], iqentry_memready[7], iqentry_memissue[7]);
|
8652 |
|
|
|
8653 |
|
|
// $display("ALU Inputs:");
|
8654 |
|
|
// $display(" 0: avail=%d data=%d id=%o op=%d a1=%h a2=%h im=%h bt=%d",
|
8655 |
|
|
// alu0_available, alu0_dataready, alu0_sourceid, alu0_op, alu0_argA,
|
8656 |
|
|
// alu0_argB, alu0_argI, alu0_bt);
|
8657 |
|
|
// $display(" 1: avail=%d data=%d id=%o op=%d a1=%h a2=%h im=%h bt=%d",
|
8658 |
|
|
// alu1_available, alu1_dataready, alu1_sourceid, alu1_op, alu1_argA,
|
8659 |
|
|
// alu1_argB, alu1_argI, alu1_bt);
|
8660 |
|
|
|
8661 |
|
|
// $display("ALU Outputs:");
|
8662 |
|
|
// $display(" 0: v=%d bus=%h id=%o bmiss=%d misspc=%h missid=%o",
|
8663 |
|
|
// alu0_v, alu0_bus, alu0_id, alu0_branchmiss, alu0_misspc, alu0_sourceid);
|
8664 |
|
|
// $display(" 1: v=%d bus=%h id=%o bmiss=%d misspc=%h missid=%o",
|
8665 |
|
|
// alu1_v, alu1_bus, alu1_id, alu1_branchmiss, alu1_misspc, alu1_sourceid);
|
8666 |
|
|
|
8667 |
|
|
// $display("DRAM Status:");
|
8668 |
|
|
// $display(" OUT: v=%d data=%h tgt=%d id=%o", dram_v, dram_bus, dram_tgt, dram_id);
|
8669 |
|
|
// $display(" dram0: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
|
8670 |
|
|
// dram0, dram0_addr, dram0_data, dram0_op, dram0_tgt, dram0_id);
|
8671 |
|
|
// $display(" dram1: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
|
8672 |
|
|
// dram1, dram1_addr, dram1_data, dram1_op, dram1_tgt, dram1_id);
|
8673 |
|
|
// $display(" dram2: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
|
8674 |
|
|
// dram2, dram2_addr, dram2_data, dram2_op, dram2_tgt, dram2_id);
|
8675 |
|
|
|
8676 |
|
|
// $display("Commit Buses:");
|
8677 |
|
|
// $display(" 0: v=%d id=%o data=%h", commit0_v, commit0_id, commit0_bus);
|
8678 |
|
|
// $display(" 1: v=%d id=%o data=%h", commit1_v, commit1_id, commit1_bus);
|
8679 |
|
|
|
8680 |
|
|
//
|
8681 |
|
|
// $display("Memory Contents:");
|
8682 |
|
|
// for (j=0; j<64; j=j+16)
|
8683 |
|
|
// $display(" %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h",
|
8684 |
|
|
// m[j+0], m[j+1], m[j+2], m[j+3], m[j+4], m[j+5], m[j+6], m[j+7],
|
8685 |
|
|
// m[j+8], m[j+9], m[j+10], m[j+11], m[j+12], m[j+13], m[j+14], m[j+15]);
|
8686 |
|
|
|
8687 |
|
|
$display("");
|
8688 |
|
|
|
8689 |
|
|
if (|panic) begin
|
8690 |
|
|
$display("");
|
8691 |
|
|
$display("-----------------------------------------------------------------");
|
8692 |
|
|
$display("-----------------------------------------------------------------");
|
8693 |
|
|
$display("--------------- PANIC:%s -----------------", message[panic]);
|
8694 |
|
|
$display("-----------------------------------------------------------------");
|
8695 |
|
|
$display("-----------------------------------------------------------------");
|
8696 |
|
|
$display("");
|
8697 |
|
|
$display("instructions committed: %d", I);
|
8698 |
|
|
$display("total execution cycles: %d", $time / 10);
|
8699 |
|
|
$display("");
|
8700 |
|
|
end
|
8701 |
|
|
if (|panic && ~outstanding_stores) begin
|
8702 |
|
|
$finish;
|
8703 |
|
|
end
|
8704 |
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
8705 |
|
|
if (branchmiss) begin
|
8706 |
|
|
if (!setpred[n]) begin
|
8707 |
|
|
iqentry_instr[n][`INSTRUCTION_OP] <= `NOP;
|
8708 |
|
|
iqentry_done[n] <= `VAL;
|
8709 |
|
|
iqentry_cmt[n] <= `VAL;
|
8710 |
|
|
end
|
8711 |
|
|
end
|
8712 |
|
|
|
8713 |
|
|
if (snr) begin
|
8714 |
|
|
seq_num <= 32'd0;
|
8715 |
|
|
seq_num1 <= 32'd0;
|
8716 |
|
|
end
|
8717 |
|
|
end // clock domain
|
8718 |
|
|
/*
|
8719 |
|
|
always @(posedge clk)
|
8720 |
|
|
if (rst) begin
|
8721 |
|
|
tail0 <= 3'd0;
|
8722 |
|
|
tail1 <= 3'd1;
|
8723 |
|
|
end
|
8724 |
|
|
else begin
|
8725 |
|
|
if (!branchmiss) begin
|
8726 |
|
|
case({fetchbuf0_v, fetchbuf1_v})
|
8727 |
|
|
2'b00: ;
|
8728 |
|
|
2'b01:
|
8729 |
|
|
if (canq1) begin
|
8730 |
|
|
tail0 <= idp1(tail0);
|
8731 |
|
|
tail1 <= idp1(tail1);
|
8732 |
|
|
end
|
8733 |
|
|
2'b10:
|
8734 |
|
|
if (canq1) begin
|
8735 |
|
|
tail0 <= idp1(tail0);
|
8736 |
|
|
tail1 <= idp1(tail1);
|
8737 |
|
|
end
|
8738 |
|
|
2'b11:
|
8739 |
|
|
if (canq1) begin
|
8740 |
|
|
if (IsBranch(fetchbuf0_instr) && predict_taken0) begin
|
8741 |
|
|
tail0 <= idp1(tail0);
|
8742 |
|
|
tail1 <= idp1(tail1);
|
8743 |
|
|
end
|
8744 |
|
|
else begin
|
8745 |
|
|
if (vqe < vl || !IsVector(fetchbuf0_instr)) begin
|
8746 |
|
|
if (canq2) begin
|
8747 |
|
|
tail0 <= idp2(tail0);
|
8748 |
|
|
tail1 <= idp2(tail1);
|
8749 |
|
|
end
|
8750 |
|
|
else begin // queued1 will be true
|
8751 |
|
|
tail0 <= idp1(tail0);
|
8752 |
|
|
tail1 <= idp1(tail1);
|
8753 |
|
|
end
|
8754 |
|
|
end
|
8755 |
|
|
end
|
8756 |
|
|
end
|
8757 |
|
|
endcase
|
8758 |
|
|
end
|
8759 |
|
|
else begin // if branchmiss
|
8760 |
|
|
if (iqentry_stomp[0] & ~iqentry_stomp[7]) begin
|
8761 |
|
|
tail0 <= 3'd0;
|
8762 |
|
|
tail1 <= 3'd1;
|
8763 |
|
|
end
|
8764 |
|
|
else if (iqentry_stomp[1] & ~iqentry_stomp[0]) begin
|
8765 |
|
|
tail0 <= 3'd1;
|
8766 |
|
|
tail1 <= 3'd2;
|
8767 |
|
|
end
|
8768 |
|
|
else if (iqentry_stomp[2] & ~iqentry_stomp[1]) begin
|
8769 |
|
|
tail0 <= 3'd2;
|
8770 |
|
|
tail1 <= 3'd3;
|
8771 |
|
|
end
|
8772 |
|
|
else if (iqentry_stomp[3] & ~iqentry_stomp[2]) begin
|
8773 |
|
|
tail0 <= 3'd3;
|
8774 |
|
|
tail1 <= 3'd4;
|
8775 |
|
|
end
|
8776 |
|
|
else if (iqentry_stomp[4] & ~iqentry_stomp[3]) begin
|
8777 |
|
|
tail0 <= 3'd4;
|
8778 |
|
|
tail1 <= 3'd5;
|
8779 |
|
|
end
|
8780 |
|
|
else if (iqentry_stomp[5] & ~iqentry_stomp[4]) begin
|
8781 |
|
|
tail0 <= 3'd5;
|
8782 |
|
|
tail1 <= 3'd6;
|
8783 |
|
|
end
|
8784 |
|
|
else if (iqentry_stomp[6] & ~iqentry_stomp[5]) begin
|
8785 |
|
|
tail0 <= 3'd6;
|
8786 |
|
|
tail1 <= 3'd7;
|
8787 |
|
|
end
|
8788 |
|
|
else if (iqentry_stomp[7] & ~iqentry_stomp[6]) begin
|
8789 |
|
|
tail0 <= 3'd7;
|
8790 |
|
|
tail1 <= 3'd0;
|
8791 |
|
|
end
|
8792 |
|
|
// otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
|
8793 |
|
|
end
|
8794 |
|
|
end
|
8795 |
|
|
*/
|
8796 |
|
|
/*
|
8797 |
|
|
always @(posedge clk)
|
8798 |
|
|
if (rst)
|
8799 |
|
|
seq_num <= 5'd0;
|
8800 |
|
|
else begin
|
8801 |
|
|
if (pebm)
|
8802 |
|
|
seq_num <= seq_num + 5'd3;
|
8803 |
|
|
else if (queued2)
|
8804 |
|
|
seq_num <= seq_num + 5'd2;
|
8805 |
|
|
else if (queued1)
|
8806 |
|
|
seq_num <= seq_num + 5'd1;
|
8807 |
|
|
end
|
8808 |
|
|
*/
|
8809 |
49 |
robfinch |
|
8810 |
51 |
robfinch |
// Update the write buffer.
|
8811 |
49 |
robfinch |
task wb_update;
|
8812 |
|
|
input [`QBITS] id;
|
8813 |
|
|
input rmw;
|
8814 |
|
|
input [7:0] sel;
|
8815 |
|
|
input [1:0] ol;
|
8816 |
|
|
input [`ABITS] addr;
|
8817 |
|
|
input [63:0] data;
|
8818 |
|
|
begin
|
8819 |
|
|
if (wbptr > 0 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3] && wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw) begin
|
8820 |
|
|
wb_sel[wbptr-1] <= wb_sel[wbptr-1] | sel;
|
8821 |
|
|
if (sel[0]) wb_data[wbptr-1][ 7: 0] <= data[ 7: 0];
|
8822 |
|
|
if (sel[1]) wb_data[wbptr-1][15: 8] <= data[15: 8];
|
8823 |
|
|
if (sel[2]) wb_data[wbptr-1][23:16] <= data[23:16];
|
8824 |
|
|
if (sel[3]) wb_data[wbptr-1][31:24] <= data[31:24];
|
8825 |
|
|
if (sel[4]) wb_data[wbptr-1][39:32] <= data[39:32];
|
8826 |
|
|
if (sel[5]) wb_data[wbptr-1][47:40] <= data[47:40];
|
8827 |
|
|
if (sel[6]) wb_data[wbptr-1][55:48] <= data[55:48];
|
8828 |
|
|
if (sel[7]) wb_data[wbptr-1][63:56] <= data[63:56];
|
8829 |
|
|
wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
|
8830 |
|
|
wb_merges <= wb_merges + 32'd1;
|
8831 |
|
|
end
|
8832 |
|
|
else begin
|
8833 |
|
|
wb_v[wbptr] <= wb_en;
|
8834 |
|
|
wb_id[wbptr] <= (16'd1 << id);
|
8835 |
|
|
wb_rmw[wbptr] <= rmw;
|
8836 |
|
|
wb_ol[wbptr] <= ol;
|
8837 |
|
|
wb_sel[wbptr] <= sel;
|
8838 |
|
|
wb_addr[wbptr] <= {addr[AMSB:3],3'b0};
|
8839 |
|
|
wb_data[wbptr] <= data;
|
8840 |
|
|
end
|
8841 |
|
|
end
|
8842 |
|
|
endtask
|
8843 |
48 |
robfinch |
// Increment the head pointers
|
8844 |
|
|
// Also increments the instruction counter
|
8845 |
|
|
// Used when instructions are committed.
|
8846 |
|
|
// Also clear any outstanding state bits that foul things up.
|
8847 |
|
|
//
|
8848 |
|
|
task head_inc;
|
8849 |
|
|
input [`QBITS] amt;
|
8850 |
|
|
begin
|
8851 |
|
|
head0 <= head0 + amt;
|
8852 |
|
|
head1 <= head1 + amt;
|
8853 |
|
|
head2 <= head2 + amt;
|
8854 |
|
|
head3 <= head3 + amt;
|
8855 |
|
|
head4 <= head4 + amt;
|
8856 |
|
|
head5 <= head5 + amt;
|
8857 |
|
|
head6 <= head6 + amt;
|
8858 |
|
|
head7 <= head7 + amt;
|
8859 |
|
|
I <= I + amt;
|
8860 |
49 |
robfinch |
if (amt==3'd3) begin
|
8861 |
|
|
iqentry_agen[head0] <= `INV;
|
8862 |
|
|
iqentry_agen[head1] <= `INV;
|
8863 |
|
|
iqentry_agen[head2] <= `INV;
|
8864 |
|
|
iqentry_mem[head0] <= `FALSE;
|
8865 |
|
|
iqentry_mem[head1] <= `FALSE;
|
8866 |
|
|
iqentry_mem[head2] <= `FALSE;
|
8867 |
|
|
iqentry_iv[head0] <= `INV;
|
8868 |
|
|
iqentry_iv[head1] <= `INV;
|
8869 |
|
|
iqentry_iv[head2] <= `INV;
|
8870 |
|
|
iqentry_alu[head0] <= `FALSE;
|
8871 |
|
|
iqentry_alu[head1] <= `FALSE;
|
8872 |
|
|
iqentry_alu[head2] <= `FALSE;
|
8873 |
|
|
end
|
8874 |
|
|
else if (amt==3'd2) begin
|
8875 |
48 |
robfinch |
iqentry_agen[head0] <= `INV;
|
8876 |
|
|
iqentry_agen[head1] <= `INV;
|
8877 |
49 |
robfinch |
iqentry_mem[head0] <= `FALSE;
|
8878 |
|
|
iqentry_mem[head1] <= `FALSE;
|
8879 |
|
|
iqentry_iv[head0] <= `INV;
|
8880 |
|
|
iqentry_iv[head1] <= `INV;
|
8881 |
|
|
iqentry_alu[head0] <= `FALSE;
|
8882 |
|
|
iqentry_alu[head1] <= `FALSE;
|
8883 |
48 |
robfinch |
end else if (amt==3'd1) begin
|
8884 |
49 |
robfinch |
iqentry_agen[head0] <= `INV;
|
8885 |
|
|
iqentry_mem[head0] <= `FALSE;
|
8886 |
|
|
iqentry_iv[head0] <= `INV;
|
8887 |
|
|
iqentry_alu[head0] <= `FALSE;
|
8888 |
48 |
robfinch |
end
|
8889 |
|
|
end
|
8890 |
|
|
endtask
|
8891 |
|
|
|
8892 |
|
|
task setargs;
|
8893 |
|
|
input [`QBITS] nn;
|
8894 |
|
|
input [4:0] id;
|
8895 |
|
|
input v;
|
8896 |
|
|
input [63:0] bus;
|
8897 |
|
|
begin
|
8898 |
|
|
if (iqentry_a1_v[nn] == `INV && iqentry_a1_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
|
8899 |
|
|
iqentry_a1[nn] <= bus;
|
8900 |
|
|
iqentry_a1_v[nn] <= `VAL;
|
8901 |
|
|
end
|
8902 |
|
|
if (iqentry_a2_v[nn] == `INV && iqentry_a2_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
|
8903 |
|
|
iqentry_a2[nn] <= bus;
|
8904 |
|
|
iqentry_a2_v[nn] <= `VAL;
|
8905 |
|
|
end
|
8906 |
|
|
if (iqentry_a3_v[nn] == `INV && iqentry_a3_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
|
8907 |
|
|
iqentry_a3[nn] <= bus;
|
8908 |
|
|
iqentry_a3_v[nn] <= `VAL;
|
8909 |
|
|
end
|
8910 |
|
|
end
|
8911 |
|
|
endtask
|
8912 |
|
|
|
8913 |
|
|
task setinsn;
|
8914 |
|
|
input [`QBITS] nn;
|
8915 |
|
|
input [4:0] id;
|
8916 |
|
|
input v;
|
8917 |
51 |
robfinch |
input [143:0] bus;
|
8918 |
48 |
robfinch |
begin
|
8919 |
|
|
if (iqentry_iv[nn] == `INV && iqentry_is[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
|
8920 |
|
|
iqentry_iv [nn] <= `VAL;
|
8921 |
|
|
// iqentry_Rt [nn] <= bus[`IB_RT];
|
8922 |
|
|
// iqentry_Rc [nn] <= bus[`IB_RC];
|
8923 |
|
|
// iqentry_Ra [nn] <= bus[`IB_RA];
|
8924 |
|
|
iqentry_a0 [nn] <= bus[`IB_CONST];
|
8925 |
|
|
iqentry_imm [nn] <= bus[`IB_IMM];
|
8926 |
|
|
iqentry_insln[nn] <= bus[`IB_LN];
|
8927 |
51 |
robfinch |
iqentry_jal [nn] <= bus[`IB_JAL];
|
8928 |
|
|
iqentry_ret [nn] <= bus[`IB_RET];
|
8929 |
|
|
iqentry_irq [nn] <= bus[`IB_IRQ];
|
8930 |
|
|
iqentry_brk [nn] <= bus[`IB_BRK];
|
8931 |
|
|
iqentry_rti [nn] <= bus[`IB_RTI];
|
8932 |
48 |
robfinch |
iqentry_bt [nn] <= bus[`IB_BT];
|
8933 |
|
|
iqentry_alu [nn] <= bus[`IB_ALU];
|
8934 |
|
|
iqentry_alu0 [nn] <= bus[`IB_ALU0];
|
8935 |
|
|
iqentry_fpu [nn] <= bus[`IB_FPU];
|
8936 |
|
|
iqentry_fc [nn] <= bus[`IB_FC];
|
8937 |
|
|
iqentry_canex[nn] <= bus[`IB_CANEX];
|
8938 |
50 |
robfinch |
iqentry_loadv[nn] <= bus[`IB_LOADV];
|
8939 |
48 |
robfinch |
iqentry_load [nn] <= bus[`IB_LOAD];
|
8940 |
|
|
iqentry_preload[nn]<= bus[`IB_PRELOAD];
|
8941 |
50 |
robfinch |
iqentry_store[nn] <= bus[`IB_STORE];
|
8942 |
|
|
iqentry_oddball[nn] <= bus[`IB_ODDBALL];
|
8943 |
|
|
iqentry_memsz[nn] <= bus[`IB_MEMSZ];
|
8944 |
48 |
robfinch |
iqentry_mem [nn] <= bus[`IB_MEM];
|
8945 |
|
|
iqentry_memndx[nn] <= bus[`IB_MEMNDX];
|
8946 |
|
|
iqentry_rmw [nn] <= bus[`IB_RMW];
|
8947 |
|
|
iqentry_memdb[nn] <= bus[`IB_MEMDB];
|
8948 |
|
|
iqentry_memsb[nn] <= bus[`IB_MEMSB];
|
8949 |
|
|
iqentry_shft48[nn] <= bus[`IB_SHFT48];
|
8950 |
|
|
iqentry_sei [nn] <= bus[`IB_SEI];
|
8951 |
|
|
iqentry_aq [nn] <= bus[`IB_AQ];
|
8952 |
|
|
iqentry_rl [nn] <= bus[`IB_RL];
|
8953 |
|
|
iqentry_jmp [nn] <= bus[`IB_JMP];
|
8954 |
|
|
iqentry_br [nn] <= bus[`IB_BR];
|
8955 |
|
|
iqentry_sync [nn] <= bus[`IB_SYNC];
|
8956 |
|
|
iqentry_fsync[nn] <= bus[`IB_FSYNC];
|
8957 |
|
|
iqentry_rfw [nn] <= bus[`IB_RFW];
|
8958 |
|
|
iqentry_we [nn] <= bus[`IB_WE];
|
8959 |
|
|
end
|
8960 |
|
|
end
|
8961 |
|
|
endtask
|
8962 |
|
|
|
8963 |
|
|
// Enqueue fetchbuf0 onto the tail of the instruction queue
|
8964 |
|
|
task enque0;
|
8965 |
|
|
input [`QBITS] tail;
|
8966 |
|
|
input [63:0] seqnum;
|
8967 |
|
|
input [5:0] venno;
|
8968 |
|
|
begin
|
8969 |
|
|
iqentry_exc[tail] <= `FLT_NONE;
|
8970 |
|
|
`ifdef SUPPORT_DBG
|
8971 |
|
|
if (dbg_imatchA)
|
8972 |
|
|
iqentry_exc[tail] <= `FLT_DBG;
|
8973 |
|
|
else if (dbg_ctrl[63])
|
8974 |
|
|
iqentry_exc[tail] <= `FLT_SSM;
|
8975 |
|
|
`endif
|
8976 |
|
|
iqentry_sn [tail] <= seqnum;
|
8977 |
|
|
iqentry_v [tail] <= `VAL;
|
8978 |
|
|
iqentry_iv [tail] <= `INV;
|
8979 |
|
|
iqentry_is [tail] <= tail;
|
8980 |
|
|
iqentry_thrd [tail] <= fetchbuf0_thrd;
|
8981 |
|
|
iqentry_done [tail] <= `INV;
|
8982 |
|
|
iqentry_cmt [tail] <= `INV;
|
8983 |
|
|
iqentry_out [tail] <= `INV;
|
8984 |
|
|
iqentry_res [tail] <= `ZERO;
|
8985 |
|
|
iqentry_instr[tail] <= IsVLS(fetchbuf0_instr) ? (vm[fnM2(fetchbuf0_instr)] ? fetchbuf0_instr : `NOP_INSN) : fetchbuf0_instr;
|
8986 |
|
|
iqentry_pt [tail] <= predict_taken0;
|
8987 |
|
|
iqentry_agen [tail] <= `INV;
|
8988 |
|
|
iqentry_state[tail] <= IQS_IDLE;
|
8989 |
|
|
// If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
|
8990 |
|
|
// inherit the previous pc.
|
8991 |
|
|
//if (IsBrk(fetchbuf0_instr) && !fetchbuf0_instr[15] &&
|
8992 |
|
|
// (IsBrk(iqentry_instr[idm1(tail)]) && !iqentry_instr[idm1(tail1)][15] && iqentry_v[idm1(tail)]))
|
8993 |
|
|
// iqentry_pc [tail] <= iqentry_pc[idm1(tail)];
|
8994 |
|
|
//else
|
8995 |
|
|
iqentry_pc [tail] <= fetchbuf0_pc;
|
8996 |
|
|
iqentry_rtop [tail] <= IsRtop(fetchbuf0_instr);
|
8997 |
|
|
iqentry_tgt [tail] <= Rt0;
|
8998 |
|
|
iqentry_Ra [tail] <= Ra0;
|
8999 |
|
|
iqentry_Rb [tail] <= Rb0;
|
9000 |
|
|
iqentry_Rc [tail] <= Rc0;
|
9001 |
|
|
iqentry_vl [tail] <= vl;
|
9002 |
|
|
iqentry_ven [tail] <= venno;
|
9003 |
|
|
iqentry_exc [tail] <= `EXC_NONE;
|
9004 |
|
|
iqentry_a1 [tail] <= rfoa0;
|
9005 |
|
|
iqentry_a1_v [tail] <= Source1Valid(fetchbuf0_instr) | regIsValid[Ra0s];
|
9006 |
|
|
iqentry_a1_s [tail] <= rf_source[Ra0s];
|
9007 |
|
|
iqentry_a2 [tail] <= rfob0;
|
9008 |
|
|
iqentry_a2_v [tail] <= Source2Valid(fetchbuf0_instr) | regIsValid[Rb0s];
|
9009 |
|
|
iqentry_a2_s [tail] <= rf_source[Rb0s];
|
9010 |
|
|
iqentry_a3 [tail] <= rfoc0;
|
9011 |
|
|
iqentry_a3_v [tail] <= Source3Valid(fetchbuf0_instr) | regIsValid[Rc0s];
|
9012 |
|
|
iqentry_a3_s [tail] <= rf_source[Rc0s];
|
9013 |
|
|
end
|
9014 |
|
|
endtask
|
9015 |
|
|
|
9016 |
|
|
// Enque fetchbuf1. Fetchbuf1 might be the second instruction to queue so some
|
9017 |
|
|
// of this code checks to see which tail it is being queued on.
|
9018 |
|
|
task enque1;
|
9019 |
|
|
input [`QBITS] tail;
|
9020 |
|
|
input [63:0] seqnum;
|
9021 |
|
|
input [5:0] venno;
|
9022 |
|
|
begin
|
9023 |
|
|
iqentry_exc[tail] <= `FLT_NONE;
|
9024 |
|
|
`ifdef SUPPORT_DBG
|
9025 |
|
|
if (dbg_imatchB)
|
9026 |
|
|
iqentry_exc[tail] <= `FLT_DBG;
|
9027 |
|
|
else if (dbg_ctrl[63])
|
9028 |
|
|
iqentry_exc[tail] <= `FLT_SSM;
|
9029 |
|
|
`endif
|
9030 |
|
|
iqentry_sn [tail] <= seqnum;
|
9031 |
|
|
iqentry_v [tail] <= `VAL;
|
9032 |
|
|
iqentry_iv [tail] <= `INV;
|
9033 |
|
|
iqentry_is [tail] <= tail;
|
9034 |
|
|
iqentry_thrd [tail] <= fetchbuf1_thrd;
|
9035 |
|
|
iqentry_done [tail] <= `INV;
|
9036 |
|
|
iqentry_cmt [tail] <= `INV;
|
9037 |
|
|
iqentry_out [tail] <= `INV;
|
9038 |
|
|
iqentry_res [tail] <= `ZERO;
|
9039 |
|
|
iqentry_instr[tail] <= IsVLS(fetchbuf1_instr) ? (vm[fnM2(fetchbuf1_instr)] ? fetchbuf1_instr : `NOP_INSN) : fetchbuf1_instr;
|
9040 |
|
|
iqentry_pt [tail] <= predict_taken1;
|
9041 |
|
|
iqentry_agen [tail] <= `INV;
|
9042 |
|
|
iqentry_state[tail] <= IQS_IDLE;
|
9043 |
|
|
// If queing 2nd instruction must read from first
|
9044 |
|
|
if (tail==tail1) begin
|
9045 |
|
|
// If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
|
9046 |
|
|
// inherit the previous pc.
|
9047 |
|
|
// if (IsBrk(fetchbuf1_instr) && !fetchbuf1_instr[15] &&
|
9048 |
|
|
// IsBrk(fetchbuf0_instr) && !fetchbuf0_instr[15])
|
9049 |
|
|
// iqentry_pc [tail] <= fetchbuf0_pc;
|
9050 |
|
|
// else
|
9051 |
|
|
iqentry_pc [tail] <= fetchbuf1_pc;
|
9052 |
|
|
end
|
9053 |
|
|
else begin
|
9054 |
|
|
// If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
|
9055 |
|
|
// inherit the previous pc.
|
9056 |
|
|
// if (IsBrk(fetchbuf1_instr) && !fetchbuf1_instr[15] &&
|
9057 |
|
|
// (IsBrk(iqentry_instr[idp7(tail)]) && !iqentry_instr[idm1(tail)][15] && iqentry_v[idm1(tail)]))
|
9058 |
|
|
// iqentry_pc [tail] <= iqentry_pc[idm1(tail)];
|
9059 |
|
|
// else
|
9060 |
|
|
iqentry_pc [tail] <= fetchbuf1_pc;
|
9061 |
|
|
end
|
9062 |
|
|
iqentry_rtop [tail] <= IsRtop(fetchbuf1_instr);
|
9063 |
|
|
iqentry_tgt [tail] <= Rt1;
|
9064 |
|
|
iqentry_Ra [tail] <= Ra1;
|
9065 |
|
|
iqentry_Rb [tail] <= Rb1;
|
9066 |
|
|
iqentry_Rc [tail] <= Rc1;
|
9067 |
|
|
iqentry_vl [tail] <= vl;
|
9068 |
|
|
iqentry_ven [tail] <= venno;
|
9069 |
|
|
iqentry_exc [tail] <= `EXC_NONE;
|
9070 |
|
|
iqentry_a1 [tail] <= rfoa1;
|
9071 |
|
|
iqentry_a1_v [tail] <= Source1Valid(fetchbuf1_instr) | regIsValid[Ra1s];
|
9072 |
|
|
iqentry_a1_s [tail] <= rf_source[Ra1s];
|
9073 |
|
|
iqentry_a2 [tail] <= rfob1;
|
9074 |
|
|
iqentry_a2_v [tail] <= Source2Valid(fetchbuf1_instr) | regIsValid[Rb1s];
|
9075 |
|
|
iqentry_a2_s [tail] <= rf_source[Rb1s];
|
9076 |
|
|
iqentry_a3 [tail] <= rfoc1;
|
9077 |
|
|
iqentry_a3_v [tail] <= Source3Valid(fetchbuf1_instr) | regIsValid[Rc1s];
|
9078 |
|
|
iqentry_a3_s [tail] <= rf_source[Rc1s];
|
9079 |
|
|
end
|
9080 |
|
|
endtask
|
9081 |
|
|
|
9082 |
|
|
// This task takes care of commits for things other than the register file.
|
9083 |
|
|
task oddball_commit;
|
9084 |
|
|
input v;
|
9085 |
|
|
input [`QBITS] head;
|
9086 |
|
|
reg thread;
|
9087 |
|
|
begin
|
9088 |
|
|
thread = iqentry_thrd[head];
|
9089 |
|
|
if (v) begin
|
9090 |
|
|
if (|iqentry_exc[head]) begin
|
9091 |
|
|
excmiss <= TRUE;
|
9092 |
|
|
`ifdef SUPPORT_SMT
|
9093 |
51 |
robfinch |
excmisspc <= {tvec[3'd0][31:8],1'b0,ol[thread],5'h00};
|
9094 |
48 |
robfinch |
excthrd <= iqentry_thrd[head];
|
9095 |
|
|
badaddr[{thread,3'd0}] <= iqentry_a1[head];
|
9096 |
|
|
epc0[thread] <= iqentry_pc[head]+ 32'd4;
|
9097 |
|
|
epc1[thread] <= epc0[thread];
|
9098 |
|
|
epc2[thread] <= epc1[thread];
|
9099 |
|
|
epc3[thread] <= epc2[thread];
|
9100 |
|
|
epc4[thread] <= epc3[thread];
|
9101 |
|
|
epc5[thread] <= epc4[thread];
|
9102 |
|
|
epc6[thread] <= epc5[thread];
|
9103 |
|
|
epc7[thread] <= epc6[thread];
|
9104 |
|
|
epc8[thread] <= epc7[thread];
|
9105 |
|
|
im_stack[thread] <= {im_stack[thread][27:0],im};
|
9106 |
|
|
ol_stack[thread] <= {ol_stack[thread][13:0],ol[thread]};
|
9107 |
|
|
pl_stack[thread] <= {pl_stack[thread][55:0],cpl[thread]};
|
9108 |
|
|
rs_stack[thread] <= {rs_stack[thread][55:0],rgs[thread]};
|
9109 |
|
|
cause[{thread,3'd0}] <= {8'd0,iqentry_exc[head]};
|
9110 |
|
|
mstatus[thread][5:3] <= 3'd0;
|
9111 |
|
|
mstatus[thread][13:6] <= 8'h00;
|
9112 |
|
|
mstatus[thread][19:14] <= 6'd0;
|
9113 |
|
|
`else
|
9114 |
51 |
robfinch |
excmisspc <= {tvec[3'd0][31:8],1'b0,ol,5'h00};
|
9115 |
48 |
robfinch |
excthrd <= iqentry_thrd[head];
|
9116 |
|
|
badaddr[{thread,3'd0}] <= iqentry_a1[head];
|
9117 |
|
|
epc0 <= iqentry_pc[head]+ 32'd4;
|
9118 |
|
|
epc1 <= epc0;
|
9119 |
|
|
epc2 <= epc1;
|
9120 |
|
|
epc3 <= epc2;
|
9121 |
|
|
epc4 <= epc3;
|
9122 |
|
|
epc5 <= epc4;
|
9123 |
|
|
epc6 <= epc5;
|
9124 |
|
|
epc7 <= epc6;
|
9125 |
|
|
epc8 <= epc7;
|
9126 |
|
|
im_stack <= {im_stack[27:0],im};
|
9127 |
|
|
ol_stack <= {ol_stack[13:0],ol};
|
9128 |
|
|
pl_stack <= {pl_stack[55:0],cpl};
|
9129 |
|
|
rs_stack <= {rs_stack[55:0],rgs};
|
9130 |
|
|
cause[{thread,3'd0}] <= {8'd0,iqentry_exc[head]};
|
9131 |
|
|
mstatus[5:3] <= 3'd0;
|
9132 |
|
|
mstatus[13:6] <= 8'h00;
|
9133 |
|
|
mstatus[19:14] <= 6'd0;
|
9134 |
|
|
`endif
|
9135 |
49 |
robfinch |
wb_en <= `TRUE;
|
9136 |
48 |
robfinch |
sema[0] <= 1'b0;
|
9137 |
|
|
ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
|
9138 |
|
|
`ifdef SUPPORT_DBG
|
9139 |
|
|
dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
|
9140 |
|
|
dbg_ctrl[63] <= FALSE;
|
9141 |
|
|
`endif
|
9142 |
|
|
end
|
9143 |
|
|
else
|
9144 |
|
|
case(iqentry_instr[head][`INSTRUCTION_OP])
|
9145 |
|
|
`BRK:
|
9146 |
|
|
// BRK is treated as a nop unless it's a software interrupt or a
|
9147 |
|
|
// hardware interrupt at a higher priority than the current priority.
|
9148 |
|
|
if ((iqentry_instr[head][23:19] > 5'd0) || iqentry_instr[head][18:16] > im) begin
|
9149 |
|
|
excmiss <= TRUE;
|
9150 |
|
|
`ifdef SUPPORT_SMT
|
9151 |
51 |
robfinch |
excmisspc <= {tvec[3'd0][31:8],1'b0,ol[thread],5'h00};
|
9152 |
48 |
robfinch |
excthrd <= iqentry_thrd[head];
|
9153 |
|
|
epc0[thread] <= iqentry_pc[head] + {iqentry_instr[head][23:19],2'b00};
|
9154 |
|
|
epc1[thread] <= epc0[thread];
|
9155 |
|
|
epc2[thread] <= epc1[thread];
|
9156 |
|
|
epc3[thread] <= epc2[thread];
|
9157 |
|
|
epc4[thread] <= epc3[thread];
|
9158 |
|
|
epc5[thread] <= epc4[thread];
|
9159 |
|
|
epc6[thread] <= epc5[thread];
|
9160 |
|
|
epc7[thread] <= epc6[thread];
|
9161 |
|
|
epc8[thread] <= epc7[thread];
|
9162 |
|
|
im_stack[thread] <= {im_stack[thread][27:0],im};
|
9163 |
|
|
ol_stack[thread] <= {ol_stack[thread][13:0],ol[thread]};
|
9164 |
|
|
pl_stack[thread] <= {pl_stack[thread][55:0],cpl[thread]};
|
9165 |
|
|
rs_stack[thread] <= {rs_stack[thread][55:0],rgs[thread]};
|
9166 |
|
|
mstatus[thread][19:14] <= 6'd0;
|
9167 |
|
|
cause[{thread,3'd0}] <= {iqentry_instr[head][31:24],iqentry_instr[head][13:6]};
|
9168 |
|
|
mstatus[thread][5:3] <= 3'd0;
|
9169 |
|
|
mstatus[thread][13:6] <= 8'h00;
|
9170 |
|
|
// For hardware interrupts only, set a new mask level
|
9171 |
|
|
// Select register set according to interrupt level
|
9172 |
|
|
if (iqentry_instr[head][23:19]==5'd0) begin
|
9173 |
|
|
mstatus[thread][2:0] <= 3'd7;//iqentry_instr[head][18:16];
|
9174 |
|
|
mstatus[thread][42:40] <= iqentry_instr[head][18:16];
|
9175 |
|
|
mstatus[thread][19:14] <= {3'b0,iqentry_instr[head][18:16]};
|
9176 |
|
|
end
|
9177 |
|
|
else
|
9178 |
|
|
mstatus[thread][19:14] <= 6'd0;
|
9179 |
|
|
`else
|
9180 |
51 |
robfinch |
excmisspc <= {tvec[3'd0][31:8],1'b0,ol,5'h00};
|
9181 |
48 |
robfinch |
excthrd <= iqentry_thrd[head];
|
9182 |
|
|
epc0 <= iqentry_pc[head] + {iqentry_instr[head][23:19],2'b00};
|
9183 |
|
|
epc1 <= epc0;
|
9184 |
|
|
epc2 <= epc1;
|
9185 |
|
|
epc3 <= epc2;
|
9186 |
|
|
epc4 <= epc3;
|
9187 |
|
|
epc5 <= epc4;
|
9188 |
|
|
epc6 <= epc5;
|
9189 |
|
|
epc7 <= epc6;
|
9190 |
|
|
epc8 <= epc7;
|
9191 |
|
|
im_stack <= {im_stack[27:0],im};
|
9192 |
|
|
ol_stack <= {ol_stack[13:0],ol};
|
9193 |
|
|
pl_stack <= {pl_stack[55:0],cpl};
|
9194 |
|
|
rs_stack <= {rs_stack[55:0],rgs};
|
9195 |
|
|
mstatus[19:14] <= 6'd0;
|
9196 |
|
|
cause[{thread,3'd0}] <= {iqentry_instr[head][31:24],iqentry_instr[head][13:6]};
|
9197 |
|
|
mstatus[5:3] <= 3'd0;
|
9198 |
|
|
mstatus[13:6] <= 8'h00;
|
9199 |
|
|
// For hardware interrupts only, set a new mask level
|
9200 |
|
|
// Select register set according to interrupt level
|
9201 |
|
|
if (iqentry_instr[head][23:19]==5'd0) begin
|
9202 |
|
|
mstatus[2:0] <= 3'd7;//iqentry_instr[head][18:16];
|
9203 |
|
|
mstatus[42:40] <= iqentry_instr[head][18:16];
|
9204 |
|
|
mstatus[19:14] <= {3'b0,iqentry_instr[head][18:16]};
|
9205 |
|
|
end
|
9206 |
|
|
else
|
9207 |
|
|
mstatus[19:14] <= 6'd0;
|
9208 |
|
|
`endif
|
9209 |
|
|
sema[0] <= 1'b0;
|
9210 |
|
|
ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
|
9211 |
|
|
`ifdef SUPPORT_DBG
|
9212 |
|
|
dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
|
9213 |
|
|
dbg_ctrl[63] <= FALSE;
|
9214 |
|
|
`endif
|
9215 |
|
|
end
|
9216 |
|
|
`IVECTOR:
|
9217 |
|
|
casez(iqentry_tgt[head])
|
9218 |
|
|
8'b00100xxx: vm[iqentry_tgt[head][2:0]] <= iqentry_res[head];
|
9219 |
|
|
8'b00101111: vl <= iqentry_res[head];
|
9220 |
|
|
default: ;
|
9221 |
|
|
endcase
|
9222 |
|
|
`R2:
|
9223 |
|
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
9224 |
|
|
`R1: case(iqentry_instr[head][20:16])
|
9225 |
|
|
`CHAIN_OFF: cr0[18] <= 1'b0;
|
9226 |
|
|
`CHAIN_ON: cr0[18] <= 1'b1;
|
9227 |
|
|
//`SETWB: wbrcd[pcr[5:0]] <= 1'b1;
|
9228 |
|
|
default: ;
|
9229 |
|
|
endcase
|
9230 |
|
|
`VMOV: casez(iqentry_tgt[head])
|
9231 |
|
|
12'b1111111_00???: vm[iqentry_tgt[head][2:0]] <= iqentry_res[head];
|
9232 |
|
|
12'b1111111_01111: vl <= iqentry_res[head];
|
9233 |
|
|
default: ;
|
9234 |
|
|
endcase
|
9235 |
|
|
`ifdef SUPPORT_SMT
|
9236 |
|
|
`SEI: mstatus[thread][2:0] <= iqentry_res[head][2:0]; // S1
|
9237 |
|
|
`else
|
9238 |
|
|
`SEI: mstatus[2:0] <= iqentry_res[head][2:0]; // S1
|
9239 |
|
|
`endif
|
9240 |
|
|
`RTI: begin
|
9241 |
|
|
excmiss <= TRUE;
|
9242 |
|
|
`ifdef SUPPORT_SMT
|
9243 |
|
|
excmisspc <= epc0[thread];
|
9244 |
|
|
excthrd <= thread;
|
9245 |
|
|
mstatus[thread][3:0] <= im_stack[thread][3:0];
|
9246 |
|
|
mstatus[thread][5:4] <= ol_stack[thread][1:0];
|
9247 |
|
|
mstatus[thread][13:6] <= pl_stack[thread][7:0];
|
9248 |
|
|
mstatus[thread][19:14] <= rs_stack[thread][5:0];
|
9249 |
|
|
im_stack[thread] <= {4'd15,im_stack[thread][27:4]};
|
9250 |
|
|
ol_stack[thread] <= {2'd0,ol_stack[thread][15:2]};
|
9251 |
|
|
pl_stack[thread] <= {8'h00,pl_stack[thread][63:8]};
|
9252 |
|
|
rs_stack[thread] <= {8'h00,rs_stack[thread][63:8]};
|
9253 |
|
|
epc0[thread] <= epc1[thread];
|
9254 |
|
|
epc1[thread] <= epc2[thread];
|
9255 |
|
|
epc2[thread] <= epc3[thread];
|
9256 |
|
|
epc3[thread] <= epc4[thread];
|
9257 |
|
|
epc4[thread] <= epc5[thread];
|
9258 |
|
|
epc5[thread] <= epc6[thread];
|
9259 |
|
|
epc6[thread] <= epc7[thread];
|
9260 |
|
|
epc7[thread] <= epc8[thread];
|
9261 |
51 |
robfinch |
epc8[thread] <= {tvec[0][31:8], 1'b0, ol[thread], 5'h0};
|
9262 |
48 |
robfinch |
`else
|
9263 |
|
|
excmisspc <= epc0;
|
9264 |
|
|
excthrd <= thread;
|
9265 |
|
|
mstatus[3:0] <= im_stack[3:0];
|
9266 |
|
|
mstatus[5:4] <= ol_stack[1:0];
|
9267 |
|
|
mstatus[13:6] <= pl_stack[7:0];
|
9268 |
|
|
mstatus[19:14] <= rs_stack[5:0];
|
9269 |
|
|
im_stack <= {4'd15,im_stack[31:4]};
|
9270 |
|
|
ol_stack <= {2'd0,ol_stack[15:2]};
|
9271 |
|
|
pl_stack <= {8'h00,pl_stack[63:8]};
|
9272 |
|
|
rs_stack <= {8'h00,rs_stack[63:8]};
|
9273 |
|
|
epc0 <= epc1;
|
9274 |
|
|
epc1 <= epc2;
|
9275 |
|
|
epc2 <= epc3;
|
9276 |
|
|
epc3 <= epc4;
|
9277 |
|
|
epc4 <= epc5;
|
9278 |
|
|
epc5 <= epc6;
|
9279 |
|
|
epc6 <= epc7;
|
9280 |
|
|
epc7 <= epc8;
|
9281 |
51 |
robfinch |
epc8 <= {tvec[0][31:8], 1'b0, ol, 5'h0};
|
9282 |
48 |
robfinch |
`endif
|
9283 |
|
|
sema[0] <= 1'b0;
|
9284 |
|
|
sema[iqentry_res[head][5:0]] <= 1'b0;
|
9285 |
|
|
vqe0 <= ve_hold[ 5: 0];
|
9286 |
|
|
vqet0 <= ve_hold[21:16];
|
9287 |
|
|
vqe1 <= ve_hold[37:32];
|
9288 |
|
|
vqet1 <= ve_hold[53:48];
|
9289 |
|
|
`ifdef SUPPORT_DBG
|
9290 |
|
|
dbg_ctrl[62:55] <= {FALSE,dbg_ctrl[62:56]};
|
9291 |
|
|
dbg_ctrl[63] <= dbg_ctrl[55];
|
9292 |
|
|
`endif
|
9293 |
|
|
end
|
9294 |
49 |
robfinch |
default: ;
|
9295 |
|
|
endcase
|
9296 |
|
|
`MEMNDX:
|
9297 |
|
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
9298 |
48 |
robfinch |
`CACHEX:
|
9299 |
49 |
robfinch |
case(iqentry_instr[head][22:18])
|
9300 |
48 |
robfinch |
5'h03: invic <= TRUE;
|
9301 |
|
|
5'h10: cr0[30] <= FALSE;
|
9302 |
|
|
5'h11: cr0[30] <= TRUE;
|
9303 |
|
|
default: ;
|
9304 |
|
|
endcase
|
9305 |
|
|
default: ;
|
9306 |
|
|
endcase
|
9307 |
|
|
`CSRRW:
|
9308 |
|
|
begin
|
9309 |
51 |
robfinch |
write_csr(iqentry_instr[head][31:18],iqentry_a1[head],thread);
|
9310 |
48 |
robfinch |
end
|
9311 |
|
|
`REX:
|
9312 |
|
|
`ifdef SUPPORT_SMT
|
9313 |
|
|
// Can only redirect to a lower level
|
9314 |
|
|
if (ol[thread] < iqentry_instr[head][13:11]) begin
|
9315 |
|
|
mstatus[thread][5:3] <= iqentry_instr[head][13:11];
|
9316 |
|
|
badaddr[{thread,iqentry_instr[head][13:11]}] <= badaddr[{thread,ol[thread]}];
|
9317 |
|
|
cause[{thread,iqentry_instr[head][13:11]}] <= cause[{thread,ol[thread]}];
|
9318 |
|
|
mstatus[thread][13:6] <= iqentry_instr[head][23:16] | iqentry_a1[head][7:0];
|
9319 |
|
|
end
|
9320 |
|
|
`else
|
9321 |
|
|
if (ol < iqentry_instr[head][13:11]) begin
|
9322 |
|
|
mstatus[5:3] <= iqentry_instr[head][13:11];
|
9323 |
|
|
badaddr[{thread,iqentry_instr[head][13:11]}] <= badaddr[{thread,ol}];
|
9324 |
|
|
cause[{thread,iqentry_instr[head][13:11]}] <= cause[{thread,ol}];
|
9325 |
|
|
mstatus[13:6] <= iqentry_instr[head][23:16] | iqentry_a1[head][7:0];
|
9326 |
|
|
end
|
9327 |
|
|
`endif
|
9328 |
|
|
`CACHE:
|
9329 |
49 |
robfinch |
case(iqentry_instr[head][17:13])
|
9330 |
48 |
robfinch |
5'h03: invic <= TRUE;
|
9331 |
|
|
5'h10: cr0[30] <= FALSE;
|
9332 |
|
|
5'h11: cr0[30] <= TRUE;
|
9333 |
|
|
default: ;
|
9334 |
|
|
endcase
|
9335 |
|
|
`FLOAT:
|
9336 |
|
|
case(iqentry_instr[head][`INSTRUCTION_S2])
|
9337 |
49 |
robfinch |
`FRM: begin
|
9338 |
51 |
robfinch |
fp_rm <= iqentry_res[head][2:0];
|
9339 |
49 |
robfinch |
end
|
9340 |
48 |
robfinch |
`FCX:
|
9341 |
|
|
begin
|
9342 |
51 |
robfinch |
fp_sx <= fp_sx & ~iqentry_res[head][5];
|
9343 |
|
|
fp_inex <= fp_inex & ~iqentry_res[head][4];
|
9344 |
|
|
fp_dbzx <= fp_dbzx & ~(iqentry_res[head][3]|iqentry_res[head][0]);
|
9345 |
|
|
fp_underx <= fp_underx & ~iqentry_res[head][2];
|
9346 |
|
|
fp_overx <= fp_overx & ~iqentry_res[head][1];
|
9347 |
|
|
fp_giopx <= fp_giopx & ~iqentry_res[head][0];
|
9348 |
|
|
fp_infdivx <= fp_infdivx & ~iqentry_res[head][0];
|
9349 |
|
|
fp_zerozerox <= fp_zerozerox & ~iqentry_res[head][0];
|
9350 |
|
|
fp_subinfx <= fp_subinfx & ~iqentry_res[head][0];
|
9351 |
|
|
fp_infzerox <= fp_infzerox & ~iqentry_res[head][0];
|
9352 |
|
|
fp_NaNCmpx <= fp_NaNCmpx & ~iqentry_res[head][0];
|
9353 |
|
|
fp_swtx <= 1'b0;
|
9354 |
48 |
robfinch |
end
|
9355 |
|
|
`FDX:
|
9356 |
|
|
begin
|
9357 |
51 |
robfinch |
fp_inexe <= fp_inexe & ~iqentry_res[head][4];
|
9358 |
|
|
fp_dbzxe <= fp_dbzxe & ~iqentry_res[head][3];
|
9359 |
|
|
fp_underxe <= fp_underxe & ~iqentry_res[head][2];
|
9360 |
|
|
fp_overxe <= fp_overxe & ~iqentry_res[head][1];
|
9361 |
|
|
fp_invopxe <= fp_invopxe & ~iqentry_res[head][0];
|
9362 |
48 |
robfinch |
end
|
9363 |
|
|
`FEX:
|
9364 |
|
|
begin
|
9365 |
51 |
robfinch |
fp_inexe <= fp_inexe | iqentry_res[head][4];
|
9366 |
|
|
fp_dbzxe <= fp_dbzxe | iqentry_res[head][3];
|
9367 |
|
|
fp_underxe <= fp_underxe | iqentry_res[head][2];
|
9368 |
|
|
fp_overxe <= fp_overxe | iqentry_res[head][1];
|
9369 |
|
|
fp_invopxe <= fp_invopxe | iqentry_res[head][0];
|
9370 |
48 |
robfinch |
end
|
9371 |
|
|
default:
|
9372 |
|
|
begin
|
9373 |
|
|
// 31 to 29 is rounding mode
|
9374 |
|
|
// 28 to 24 are exception enables
|
9375 |
|
|
// 23 is nsfp
|
9376 |
|
|
// 22 is a fractie
|
9377 |
51 |
robfinch |
fp_fractie <= iqentry_a0[head][22];
|
9378 |
|
|
fp_raz <= iqentry_a0[head][21];
|
9379 |
48 |
robfinch |
// 20 is a 0
|
9380 |
51 |
robfinch |
fp_neg <= iqentry_a0[head][19];
|
9381 |
|
|
fp_pos <= iqentry_a0[head][18];
|
9382 |
|
|
fp_zero <= iqentry_a0[head][17];
|
9383 |
|
|
fp_inf <= iqentry_a0[head][16];
|
9384 |
48 |
robfinch |
// 15 swtx
|
9385 |
|
|
// 14
|
9386 |
51 |
robfinch |
fp_inex <= fp_inex | (fp_inexe & iqentry_a0[head][14]);
|
9387 |
|
|
fp_dbzx <= fp_dbzx | (fp_dbzxe & iqentry_a0[head][13]);
|
9388 |
|
|
fp_underx <= fp_underx | (fp_underxe & iqentry_a0[head][12]);
|
9389 |
|
|
fp_overx <= fp_overx | (fp_overxe & iqentry_a0[head][11]);
|
9390 |
48 |
robfinch |
//fp_giopx <= fp_giopx | (fp_giopxe & iqentry_res2[head][10]);
|
9391 |
|
|
//fp_invopx <= fp_invopx | (fp_invopxe & iqentry_res2[head][24]);
|
9392 |
|
|
//
|
9393 |
51 |
robfinch |
fp_cvtx <= fp_cvtx | (fp_giopxe & iqentry_a0[head][7]);
|
9394 |
|
|
fp_sqrtx <= fp_sqrtx | (fp_giopxe & iqentry_a0[head][6]);
|
9395 |
|
|
fp_NaNCmpx <= fp_NaNCmpx | (fp_giopxe & iqentry_a0[head][5]);
|
9396 |
|
|
fp_infzerox <= fp_infzerox | (fp_giopxe & iqentry_a0[head][4]);
|
9397 |
|
|
fp_zerozerox <= fp_zerozerox | (fp_giopxe & iqentry_a0[head][3]);
|
9398 |
|
|
fp_infdivx <= fp_infdivx | (fp_giopxe & iqentry_a0[head][2]);
|
9399 |
|
|
fp_subinfx <= fp_subinfx | (fp_giopxe & iqentry_a0[head][1]);
|
9400 |
|
|
fp_snanx <= fp_snanx | (fp_giopxe & iqentry_a0[head][0]);
|
9401 |
48 |
robfinch |
|
9402 |
|
|
end
|
9403 |
|
|
endcase
|
9404 |
|
|
default: ;
|
9405 |
|
|
endcase
|
9406 |
|
|
// Once the flow control instruction commits, NOP it out to allow
|
9407 |
|
|
// pending stores to be issued.
|
9408 |
|
|
iqentry_instr[head][5:0] <= `NOP;
|
9409 |
|
|
end
|
9410 |
|
|
end
|
9411 |
|
|
endtask
|
9412 |
|
|
|
9413 |
|
|
// CSR access tasks
|
9414 |
|
|
task read_csr;
|
9415 |
51 |
robfinch |
input [11:0] csrno;
|
9416 |
48 |
robfinch |
output [63:0] dat;
|
9417 |
|
|
input thread;
|
9418 |
|
|
begin
|
9419 |
|
|
`ifdef SUPPORT_SMT
|
9420 |
|
|
if (csrno[11:10] >= ol[thread])
|
9421 |
|
|
`else
|
9422 |
|
|
if (csrno[11:10] >= ol)
|
9423 |
|
|
`endif
|
9424 |
|
|
casez(csrno[9:0])
|
9425 |
|
|
`CSR_CR0: dat <= cr0;
|
9426 |
|
|
`CSR_HARTID: dat <= hartid;
|
9427 |
|
|
`CSR_TICK: dat <= tick;
|
9428 |
|
|
`CSR_PCR: dat <= pcr;
|
9429 |
|
|
`CSR_PCR2: dat <= pcr2;
|
9430 |
49 |
robfinch |
`CSR_PMR: dat <= pmr;
|
9431 |
48 |
robfinch |
`CSR_WBRCD: dat <= wbrcd;
|
9432 |
|
|
`CSR_SEMA: dat <= sema;
|
9433 |
|
|
`CSR_SBL: dat <= sbl;
|
9434 |
|
|
`CSR_SBU: dat <= sbu;
|
9435 |
|
|
`CSR_TCB: dat <= tcb;
|
9436 |
51 |
robfinch |
`CSR_FSTAT: dat <= {fp_rgs,fp_status};
|
9437 |
48 |
robfinch |
`ifdef SUPPORT_DBG
|
9438 |
|
|
`CSR_DBAD0: dat <= dbg_adr0;
|
9439 |
|
|
`CSR_DBAD1: dat <= dbg_adr1;
|
9440 |
|
|
`CSR_DBAD2: dat <= dbg_adr2;
|
9441 |
|
|
`CSR_DBAD3: dat <= dbg_adr3;
|
9442 |
|
|
`CSR_DBCTRL: dat <= dbg_ctrl;
|
9443 |
|
|
`CSR_DBSTAT: dat <= dbg_stat;
|
9444 |
|
|
`endif
|
9445 |
|
|
`CSR_CAS: dat <= cas;
|
9446 |
|
|
`CSR_TVEC: dat <= tvec[csrno[2:0]];
|
9447 |
|
|
`CSR_BADADR: dat <= badaddr[{thread,csrno[13:11]}];
|
9448 |
|
|
`CSR_CAUSE: dat <= {48'd0,cause[{thread,csrno[13:11]}]};
|
9449 |
|
|
`ifdef SUPPORT_SMT
|
9450 |
|
|
`CSR_IM_STACK: dat <= im_stack[thread];
|
9451 |
|
|
`CSR_OL_STACK: dat <= ol_stack[thread];
|
9452 |
|
|
`CSR_PL_STACK: dat <= pl_stack[thread];
|
9453 |
|
|
`CSR_RS_STACK: dat <= rs_stack[thread];
|
9454 |
|
|
`CSR_STATUS: dat <= mstatus[thread][63:0];
|
9455 |
|
|
`CSR_EPC0: dat <= epc0[thread];
|
9456 |
|
|
`CSR_EPC1: dat <= epc1[thread];
|
9457 |
|
|
`CSR_EPC2: dat <= epc2[thread];
|
9458 |
|
|
`CSR_EPC3: dat <= epc3[thread];
|
9459 |
|
|
`CSR_EPC4: dat <= epc4[thread];
|
9460 |
|
|
`CSR_EPC5: dat <= epc5[thread];
|
9461 |
|
|
`CSR_EPC6: dat <= epc6[thread];
|
9462 |
|
|
`CSR_EPC7: dat <= epc7[thread];
|
9463 |
|
|
`else
|
9464 |
|
|
`CSR_IM_STACK: dat <= im_stack;
|
9465 |
|
|
`CSR_OL_STACK: dat <= ol_stack;
|
9466 |
|
|
`CSR_PL_STACK: dat <= pl_stack;
|
9467 |
|
|
`CSR_RS_STACK: dat <= rs_stack;
|
9468 |
|
|
`CSR_STATUS: dat <= mstatus[63:0];
|
9469 |
|
|
`CSR_EPC0: dat <= epc0;
|
9470 |
|
|
`CSR_EPC1: dat <= epc1;
|
9471 |
|
|
`CSR_EPC2: dat <= epc2;
|
9472 |
|
|
`CSR_EPC3: dat <= epc3;
|
9473 |
|
|
`CSR_EPC4: dat <= epc4;
|
9474 |
|
|
`CSR_EPC5: dat <= epc5;
|
9475 |
|
|
`CSR_EPC6: dat <= epc6;
|
9476 |
|
|
`CSR_EPC7: dat <= epc7;
|
9477 |
|
|
`endif
|
9478 |
|
|
`CSR_CODEBUF: dat <= codebuf[csrno[5:0]];
|
9479 |
|
|
`CSR_TIME: dat <= wc_times;
|
9480 |
|
|
`CSR_INFO:
|
9481 |
|
|
case(csrno[3:0])
|
9482 |
|
|
4'd0: dat <= "Finitron"; // manufacturer
|
9483 |
|
|
4'd1: dat <= " ";
|
9484 |
|
|
4'd2: dat <= "64 bit "; // CPU class
|
9485 |
|
|
4'd3: dat <= " ";
|
9486 |
|
|
4'd4: dat <= "FT64 "; // Name
|
9487 |
|
|
4'd5: dat <= " ";
|
9488 |
|
|
4'd6: dat <= 64'd1; // model #
|
9489 |
|
|
4'd7: dat <= 64'd1; // serial number
|
9490 |
|
|
4'd8: dat <= {32'd16384,32'd16384}; // cache sizes instruction,data
|
9491 |
|
|
4'd9: dat <= 64'd0;
|
9492 |
|
|
default: dat <= 64'd0;
|
9493 |
|
|
endcase
|
9494 |
|
|
default: begin
|
9495 |
|
|
$display("Unsupported CSR:%h",csrno[10:0]);
|
9496 |
|
|
dat <= 64'hEEEEEEEEEEEEEEEE;
|
9497 |
|
|
end
|
9498 |
|
|
endcase
|
9499 |
|
|
else
|
9500 |
|
|
dat <= 64'h0;
|
9501 |
|
|
end
|
9502 |
|
|
endtask
|
9503 |
|
|
|
9504 |
|
|
task write_csr;
|
9505 |
|
|
input [13:0] csrno;
|
9506 |
|
|
input [63:0] dat;
|
9507 |
|
|
input thread;
|
9508 |
|
|
begin
|
9509 |
|
|
`ifdef SUPPORT_SMT
|
9510 |
|
|
if (csrno[11:10] >= ol[thread])
|
9511 |
|
|
`else
|
9512 |
|
|
if (csrno[11:10] >= ol)
|
9513 |
|
|
`endif
|
9514 |
|
|
case(csrno[13:12])
|
9515 |
|
|
2'd1: // CSRRW
|
9516 |
|
|
casez(csrno[9:0])
|
9517 |
|
|
`CSR_CR0: cr0 <= dat;
|
9518 |
|
|
`CSR_PCR: pcr <= dat[31:0];
|
9519 |
|
|
`CSR_PCR2: pcr2 <= dat;
|
9520 |
49 |
robfinch |
`CSR_PMR: case(`NUM_IDU)
|
9521 |
|
|
0,1: pmr[0] <= 1'b1;
|
9522 |
|
|
2:
|
9523 |
|
|
begin
|
9524 |
|
|
if (dat[1:0]==2'b00)
|
9525 |
|
|
pmr[1:0] <= 2'b01;
|
9526 |
|
|
else
|
9527 |
|
|
pmr[1:0] <= dat[1:0];
|
9528 |
|
|
pmr[63:2] <= dat[63:2];
|
9529 |
|
|
end
|
9530 |
|
|
3:
|
9531 |
|
|
begin
|
9532 |
|
|
if (dat[2:0]==3'b000)
|
9533 |
|
|
pmr[2:0] <= 3'b001;
|
9534 |
|
|
else
|
9535 |
|
|
pmr[2:0] <= dat[2:0];
|
9536 |
|
|
pmr[63:3] <= dat[63:3];
|
9537 |
|
|
end
|
9538 |
|
|
default: pmr[0] <= 1'b1;
|
9539 |
|
|
endcase
|
9540 |
48 |
robfinch |
`CSR_WBRCD: wbrcd <= dat;
|
9541 |
|
|
`CSR_SEMA: sema <= dat;
|
9542 |
|
|
`CSR_SBL: sbl <= dat[31:0];
|
9543 |
|
|
`CSR_SBU: sbu <= dat[31:0];
|
9544 |
|
|
`CSR_TCB: tcb <= dat;
|
9545 |
51 |
robfinch |
`CSR_FSTAT: fpu_csr[37:32] <= dat[37:32];
|
9546 |
48 |
robfinch |
`CSR_BADADR: badaddr[{thread,csrno[13:11]}] <= dat;
|
9547 |
|
|
`CSR_CAUSE: cause[{thread,csrno[13:11]}] <= dat[15:0];
|
9548 |
|
|
`ifdef SUPPORT_DBG
|
9549 |
|
|
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
|
9550 |
|
|
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
|
9551 |
|
|
`CSR_DBAD2: dbg_adr2 <= dat[AMSB:0];
|
9552 |
|
|
`CSR_DBAD3: dbg_adr3 <= dat[AMSB:0];
|
9553 |
|
|
`CSR_DBCTRL: dbg_ctrl <= dat;
|
9554 |
|
|
`endif
|
9555 |
|
|
`CSR_CAS: cas <= dat;
|
9556 |
|
|
`CSR_TVEC: tvec[csrno[2:0]] <= dat[31:0];
|
9557 |
|
|
`ifdef SUPPORT_SMT
|
9558 |
|
|
`CSR_IM_STACK: im_stack[thread] <= dat[31:0];
|
9559 |
|
|
`CSR_OL_STACK: ol_stack[thread] <= dat[15:0];
|
9560 |
|
|
`CSR_PL_STACK: pl_stack[thread] <= dat;
|
9561 |
|
|
`CSR_RS_STACK: rs_stack[thread] <= dat;
|
9562 |
|
|
`CSR_STATUS: mstatus[thread][63:0] <= dat;
|
9563 |
|
|
`CSR_EPC0: epc0[thread] <= dat;
|
9564 |
|
|
`CSR_EPC1: epc1[thread] <= dat;
|
9565 |
|
|
`CSR_EPC2: epc2[thread] <= dat;
|
9566 |
|
|
`CSR_EPC3: epc3[thread] <= dat;
|
9567 |
|
|
`CSR_EPC4: epc4[thread] <= dat;
|
9568 |
|
|
`CSR_EPC5: epc5[thread] <= dat;
|
9569 |
|
|
`CSR_EPC6: epc6[thread] <= dat;
|
9570 |
|
|
`CSR_EPC7: epc7[thread] <= dat;
|
9571 |
|
|
`else
|
9572 |
|
|
`CSR_IM_STACK: im_stack <= dat[31:0];
|
9573 |
|
|
`CSR_OL_STACK: ol_stack <= dat[15:0];
|
9574 |
|
|
`CSR_PL_STACK: pl_stack <= dat;
|
9575 |
|
|
`CSR_RS_STACK: rs_stack <= dat;
|
9576 |
|
|
`CSR_STATUS: mstatus[63:0] <= dat;
|
9577 |
|
|
`CSR_EPC0: epc0 <= dat;
|
9578 |
|
|
`CSR_EPC1: epc1 <= dat;
|
9579 |
|
|
`CSR_EPC2: epc2 <= dat;
|
9580 |
|
|
`CSR_EPC3: epc3 <= dat;
|
9581 |
|
|
`CSR_EPC4: epc4 <= dat;
|
9582 |
|
|
`CSR_EPC5: epc5 <= dat;
|
9583 |
|
|
`CSR_EPC6: epc6 <= dat;
|
9584 |
|
|
`CSR_EPC7: epc7 <= dat;
|
9585 |
|
|
`endif
|
9586 |
|
|
`CSR_TIME: begin
|
9587 |
|
|
ld_time <= 6'h3f;
|
9588 |
|
|
wc_time_dat <= dat;
|
9589 |
|
|
end
|
9590 |
|
|
`CSR_CODEBUF: codebuf[csrno[5:0]] <= dat;
|
9591 |
|
|
default: ;
|
9592 |
|
|
endcase
|
9593 |
|
|
2'd2: // CSRRS
|
9594 |
|
|
case(csrno[9:0])
|
9595 |
|
|
`CSR_CR0: cr0 <= cr0 | dat;
|
9596 |
|
|
`CSR_PCR: pcr[31:0] <= pcr[31:0] | dat[31:0];
|
9597 |
|
|
`CSR_PCR2: pcr2 <= pcr2 | dat;
|
9598 |
49 |
robfinch |
`CSR_PMR: pmr <= pmr | dat;
|
9599 |
48 |
robfinch |
`CSR_WBRCD: wbrcd <= wbrcd | dat;
|
9600 |
|
|
`ifdef SUPPORT_DBG
|
9601 |
|
|
`CSR_DBCTRL: dbg_ctrl <= dbg_ctrl | dat;
|
9602 |
|
|
`endif
|
9603 |
|
|
`CSR_SEMA: sema <= sema | dat;
|
9604 |
|
|
`ifdef SUPPORT_SMT
|
9605 |
|
|
`CSR_STATUS: mstatus[thread][63:0] <= mstatus[thread][63:0] | dat;
|
9606 |
|
|
`else
|
9607 |
|
|
`CSR_STATUS: mstatus[63:0] <= mstatus[63:0] | dat;
|
9608 |
|
|
`endif
|
9609 |
|
|
default: ;
|
9610 |
|
|
endcase
|
9611 |
|
|
2'd3: // CSRRC
|
9612 |
|
|
case(csrno[9:0])
|
9613 |
|
|
`CSR_CR0: cr0 <= cr0 & ~dat;
|
9614 |
|
|
`CSR_PCR: pcr <= pcr & ~dat;
|
9615 |
|
|
`CSR_PCR2: pcr2 <= pcr2 & ~dat;
|
9616 |
49 |
robfinch |
`CSR_PMR: begin
|
9617 |
|
|
if (dat[1:0]==2'b11)
|
9618 |
|
|
pmr[1:0] <= 2'b01;
|
9619 |
|
|
else
|
9620 |
|
|
pmr[1:0] <= pmr[1:0] & ~dat[1:0];
|
9621 |
|
|
pmr[63:2] <= pmr[63:2] & ~dat[63:2];
|
9622 |
|
|
end
|
9623 |
48 |
robfinch |
`CSR_WBRCD: wbrcd <= wbrcd & ~dat;
|
9624 |
|
|
`ifdef SUPPORT_DBG
|
9625 |
|
|
`CSR_DBCTRL: dbg_ctrl <= dbg_ctrl & ~dat;
|
9626 |
|
|
`endif
|
9627 |
|
|
`CSR_SEMA: sema <= sema & ~dat;
|
9628 |
|
|
`ifdef SUPPORT_SMT
|
9629 |
|
|
`CSR_STATUS: mstatus[thread][63:0] <= mstatus[thread][63:0] & ~dat;
|
9630 |
|
|
`else
|
9631 |
|
|
`CSR_STATUS: mstatus[63:0] <= mstatus[63:0] & ~dat;
|
9632 |
|
|
`endif
|
9633 |
|
|
default: ;
|
9634 |
|
|
endcase
|
9635 |
|
|
default: ;
|
9636 |
|
|
endcase
|
9637 |
|
|
end
|
9638 |
|
|
endtask
|
9639 |
|
|
|
9640 |
|
|
|
9641 |
|
|
endmodule
|
9642 |
|
|
|
9643 |
|
|
|
9644 |
|
|
module decoder5 (num, out);
|
9645 |
|
|
input [4:0] num;
|
9646 |
|
|
output [31:1] out;
|
9647 |
|
|
reg [31:1] out;
|
9648 |
|
|
|
9649 |
|
|
always @(num)
|
9650 |
|
|
case (num)
|
9651 |
|
|
5'd0 : out <= 31'b0000000000000000000000000000000;
|
9652 |
|
|
5'd1 : out <= 31'b0000000000000000000000000000001;
|
9653 |
|
|
5'd2 : out <= 31'b0000000000000000000000000000010;
|
9654 |
|
|
5'd3 : out <= 31'b0000000000000000000000000000100;
|
9655 |
|
|
5'd4 : out <= 31'b0000000000000000000000000001000;
|
9656 |
|
|
5'd5 : out <= 31'b0000000000000000000000000010000;
|
9657 |
|
|
5'd6 : out <= 31'b0000000000000000000000000100000;
|
9658 |
|
|
5'd7 : out <= 31'b0000000000000000000000001000000;
|
9659 |
|
|
5'd8 : out <= 31'b0000000000000000000000010000000;
|
9660 |
|
|
5'd9 : out <= 31'b0000000000000000000000100000000;
|
9661 |
|
|
5'd10: out <= 31'b0000000000000000000001000000000;
|
9662 |
|
|
5'd11: out <= 31'b0000000000000000000010000000000;
|
9663 |
|
|
5'd12: out <= 31'b0000000000000000000100000000000;
|
9664 |
|
|
5'd13: out <= 31'b0000000000000000001000000000000;
|
9665 |
|
|
5'd14: out <= 31'b0000000000000000010000000000000;
|
9666 |
|
|
5'd15: out <= 31'b0000000000000000100000000000000;
|
9667 |
|
|
5'd16: out <= 31'b0000000000000001000000000000000;
|
9668 |
|
|
5'd17: out <= 31'b0000000000000010000000000000000;
|
9669 |
|
|
5'd18: out <= 31'b0000000000000100000000000000000;
|
9670 |
|
|
5'd19: out <= 31'b0000000000001000000000000000000;
|
9671 |
|
|
5'd20: out <= 31'b0000000000010000000000000000000;
|
9672 |
|
|
5'd21: out <= 31'b0000000000100000000000000000000;
|
9673 |
|
|
5'd22: out <= 31'b0000000001000000000000000000000;
|
9674 |
|
|
5'd23: out <= 31'b0000000010000000000000000000000;
|
9675 |
|
|
5'd24: out <= 31'b0000000100000000000000000000000;
|
9676 |
|
|
5'd25: out <= 31'b0000001000000000000000000000000;
|
9677 |
|
|
5'd26: out <= 31'b0000010000000000000000000000000;
|
9678 |
|
|
5'd27: out <= 31'b0000100000000000000000000000000;
|
9679 |
|
|
5'd28: out <= 31'b0001000000000000000000000000000;
|
9680 |
|
|
5'd29: out <= 31'b0010000000000000000000000000000;
|
9681 |
|
|
5'd30: out <= 31'b0100000000000000000000000000000;
|
9682 |
|
|
5'd31: out <= 31'b1000000000000000000000000000000;
|
9683 |
|
|
endcase
|
9684 |
|
|
|
9685 |
|
|
endmodule
|
9686 |
|
|
|
9687 |
|
|
module decoder6 (num, out);
|
9688 |
|
|
input [5:0] num;
|
9689 |
|
|
output [63:1] out;
|
9690 |
|
|
|
9691 |
|
|
wire [63:0] out1;
|
9692 |
|
|
|
9693 |
|
|
assign out1 = 64'd1 << num;
|
9694 |
|
|
assign out = out1[63:1];
|
9695 |
|
|
|
9696 |
|
|
endmodule
|
9697 |
|
|
|
9698 |
|
|
module decoder7 (num, out);
|
9699 |
|
|
input [6:0] num;
|
9700 |
|
|
output [127:1] out;
|
9701 |
|
|
|
9702 |
|
|
wire [127:0] out1;
|
9703 |
|
|
|
9704 |
|
|
assign out1 = 128'd1 << num;
|
9705 |
|
|
assign out = out1[127:1];
|
9706 |
|
|
|
9707 |
|
|
endmodule
|
9708 |
|
|
|
9709 |
|
|
module decoder8 (num, out);
|
9710 |
|
|
input [7:0] num;
|
9711 |
|
|
output [255:1] out;
|
9712 |
|
|
|
9713 |
|
|
wire [255:0] out1;
|
9714 |
|
|
|
9715 |
|
|
assign out1 = 256'd1 << num;
|
9716 |
|
|
assign out = out1[255:1];
|
9717 |
|
|
|
9718 |
|
|
endmodule
|
9719 |
|
|
|