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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [twoway/] [FT64_BTB.v] - Blame information for rev 52

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Line No. Rev Author Line
1 48 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      FT64_BTB.v
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//              
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// ============================================================================
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//
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module FT64_BTB(rst, wclk, wr, wadr, wdat, valid, rclk, pcA, btgtA, pcB, btgtB, pcC, btgtC, pcD, btgtD,
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    npcA, npcB, npcC, npcD);
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parameter AMSB = 31;
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parameter RSTPC = 32'hFFFC0100;
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input rst;
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input wclk;
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input wr;
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input [AMSB:0] wadr;
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input [AMSB:0] wdat;
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input valid;
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input rclk;
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input [AMSB:0] pcA;
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output [AMSB:0] btgtA;
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input [AMSB:0] pcB;
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output [AMSB:0] btgtB;
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input [AMSB:0] pcC;
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output [AMSB:0] btgtC;
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input [AMSB:0] pcD;
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output [AMSB:0] btgtD;
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input [AMSB:0] npcA;
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input [AMSB:0] npcB;
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input [AMSB:0] npcC;
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input [AMSB:0] npcD;
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integer n;
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reg [(AMSB+1)*2+1:0] mem [0:1023];
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reg [9:0] radrA, radrB, radrC, radrD;
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initial begin
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    for (n = 0; n < 1024; n = n + 1)
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        mem[n] <= RSTPC;
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end
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always @(posedge wclk)
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begin
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    if (wr) #1 mem[wadr[9:0]][AMSB:0] <= wdat;
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    if (wr) #1 mem[wadr[9:0]][(AMSB+1)*2:AMSB+1] <= wadr;
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    if (wr) #1 mem[wadr[9:0]][(AMSB+1)*2+1] <= valid;
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end
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always @(posedge rclk)
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    #1 radrA <= pcA[11:2];
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always @(posedge rclk)
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    #1 radrB <= pcB[11:2];
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always @(posedge rclk)
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    #1 radrC <= pcC[11:2];
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always @(posedge rclk)
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    #1 radrD <= pcD[11:2];
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wire hitA = mem[radrA][(AMSB+1)*2:AMSB+1]==pcA && mem[radrA][(AMSB+1)*2+1];
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wire hitB = mem[radrB][(AMSB+1)*2:AMSB+1]==pcB && mem[radrB][(AMSB+1)*2+1];
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wire hitC = mem[radrC][(AMSB+1)*2:AMSB+1]==pcC && mem[radrC][(AMSB+1)*2+1];
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wire hitD = mem[radrD][(AMSB+1)*2:AMSB+1]==pcD && mem[radrD][(AMSB+1)*2+1];
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assign btgtA = hitA ? mem[radrA][AMSB:0] : npcA;
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assign btgtB = hitB ? mem[radrB][AMSB:0] : npcB;
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assign btgtC = hitC ? mem[radrC][AMSB:0] : npcC;
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assign btgtD = hitD ? mem[radrD][AMSB:0] : npcD;
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endmodule

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