| 1 |
48 |
robfinch |
`timescale 1ns / 1ps
|
| 2 |
|
|
// ============================================================================
|
| 3 |
|
|
// __
|
| 4 |
|
|
// \\__/ o\ (C) 2013-2018 Robert Finch, Waterloo
|
| 5 |
|
|
// \ __ / All rights reserved.
|
| 6 |
|
|
// \/_// robfinch<remove>@finitron.ca
|
| 7 |
|
|
// ||
|
| 8 |
|
|
//
|
| 9 |
|
|
// This source file is free software: you can redistribute it and/or modify
|
| 10 |
|
|
// it under the terms of the GNU Lesser General Public License as published
|
| 11 |
|
|
// by the Free Software Foundation, either version 3 of the License, or
|
| 12 |
|
|
// (at your option) any later version.
|
| 13 |
|
|
//
|
| 14 |
|
|
// This source file is distributed in the hope that it will be useful,
|
| 15 |
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 16 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 17 |
|
|
// GNU General Public License for more details.
|
| 18 |
|
|
//
|
| 19 |
|
|
// You should have received a copy of the GNU General Public License
|
| 20 |
|
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
| 21 |
|
|
//
|
| 22 |
|
|
//
|
| 23 |
|
|
// Register file with two write ports and six read ports.
|
| 24 |
|
|
// ============================================================================
|
| 25 |
|
|
//
|
| 26 |
49 |
robfinch |
`include "FT64_config.vh"
|
| 27 |
48 |
robfinch |
|
| 28 |
|
|
module FT64_regfileRam_sim(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb);
|
| 29 |
49 |
robfinch |
parameter WID=64;
|
| 30 |
48 |
robfinch |
parameter RBIT = 11;
|
| 31 |
|
|
input clka;
|
| 32 |
|
|
input ena;
|
| 33 |
50 |
robfinch |
input [7:0] wea;
|
| 34 |
48 |
robfinch |
input [RBIT:0] addra;
|
| 35 |
|
|
input [WID-1:0] dina;
|
| 36 |
|
|
input clkb;
|
| 37 |
|
|
input enb;
|
| 38 |
|
|
input [RBIT:0] addrb;
|
| 39 |
|
|
output [WID-1:0] doutb;
|
| 40 |
|
|
|
| 41 |
|
|
integer n;
|
| 42 |
|
|
(* RAM_STYLE="BLOCK" *)
|
| 43 |
|
|
reg [64:0] mem [0:4095];
|
| 44 |
|
|
reg [RBIT:0] raddrb;
|
| 45 |
|
|
|
| 46 |
|
|
initial begin
|
| 47 |
|
|
for (n = 0; n < 4096; n = n + 1)
|
| 48 |
|
|
mem[n] = 0;
|
| 49 |
|
|
end
|
| 50 |
|
|
|
| 51 |
|
|
always @(posedge clka) if (ena & wea[0]) mem[addra][7:0] <= dina[7:0];
|
| 52 |
|
|
always @(posedge clka) if (ena & wea[1]) mem[addra][15:8] <= dina[15:8];
|
| 53 |
|
|
always @(posedge clka) if (ena & wea[2]) mem[addra][23:16] <= dina[23:16];
|
| 54 |
|
|
always @(posedge clka) if (ena & wea[3]) mem[addra][31:24] <= dina[31:24];
|
| 55 |
|
|
always @(posedge clka) if (ena & wea[4]) mem[addra][39:32] <= dina[39:32];
|
| 56 |
|
|
always @(posedge clka) if (ena & wea[5]) mem[addra][47:40] <= dina[47:40];
|
| 57 |
|
|
always @(posedge clka) if (ena & wea[6]) mem[addra][55:48] <= dina[55:48];
|
| 58 |
|
|
always @(posedge clka) if (ena & wea[7]) mem[addra][63:56] <= dina[63:56];
|
| 59 |
|
|
|
| 60 |
|
|
always @(posedge clkb)
|
| 61 |
|
|
raddrb <= addrb;
|
| 62 |
|
|
assign doutb = mem[raddrb];
|
| 63 |
|
|
|
| 64 |
|
|
endmodule
|
| 65 |
|
|
|
| 66 |
|
|
module FT64_regfile2w6r_oc(clk4x, clk, wr0, wr1, we0, we1, wa0, wa1, i0, i1,
|
| 67 |
|
|
rclk, ra0, ra1, ra2, ra3, ra4, ra5,
|
| 68 |
|
|
o0, o1, o2, o3, o4, o5);
|
| 69 |
|
|
parameter WID=64;
|
| 70 |
|
|
parameter RBIT = 11;
|
| 71 |
|
|
input clk4x;
|
| 72 |
|
|
input clk;
|
| 73 |
|
|
input wr0;
|
| 74 |
|
|
input wr1;
|
| 75 |
50 |
robfinch |
input [7:0] we0;
|
| 76 |
|
|
input [7:0] we1;
|
| 77 |
48 |
robfinch |
input [RBIT:0] wa0;
|
| 78 |
|
|
input [RBIT:0] wa1;
|
| 79 |
|
|
input [WID-1:0] i0;
|
| 80 |
|
|
input [WID-1:0] i1;
|
| 81 |
|
|
input rclk;
|
| 82 |
|
|
input [RBIT:0] ra0;
|
| 83 |
|
|
input [RBIT:0] ra1;
|
| 84 |
|
|
input [RBIT:0] ra2;
|
| 85 |
|
|
input [RBIT:0] ra3;
|
| 86 |
|
|
input [RBIT:0] ra4;
|
| 87 |
|
|
input [RBIT:0] ra5;
|
| 88 |
|
|
output [WID-1:0] o0;
|
| 89 |
|
|
output [WID-1:0] o1;
|
| 90 |
|
|
output [WID-1:0] o2;
|
| 91 |
|
|
output [WID-1:0] o3;
|
| 92 |
|
|
output [WID-1:0] o4;
|
| 93 |
|
|
output [WID-1:0] o5;
|
| 94 |
|
|
|
| 95 |
|
|
reg wr;
|
| 96 |
|
|
reg [RBIT:0] wa;
|
| 97 |
|
|
reg [WID-1:0] i;
|
| 98 |
|
|
reg [7:0] we;
|
| 99 |
|
|
wire [WID-1:0] o00, o01, o02, o03, o04, o05;
|
| 100 |
|
|
reg wr1x;
|
| 101 |
|
|
reg [RBIT:0] wa1x;
|
| 102 |
|
|
reg [WID-1:0] i1x;
|
| 103 |
|
|
reg [7:0] we1x;
|
| 104 |
|
|
|
| 105 |
|
|
integer n;
|
| 106 |
|
|
|
| 107 |
|
|
`ifdef SIM
|
| 108 |
|
|
FT64_regfileRam_sim urf10 (
|
| 109 |
|
|
.clka(clk4x),
|
| 110 |
|
|
.ena(wr),
|
| 111 |
|
|
.wea(we),
|
| 112 |
|
|
.addra(wa),
|
| 113 |
|
|
.dina(i),
|
| 114 |
|
|
.clkb(rclk),
|
| 115 |
|
|
.enb(1'b1),
|
| 116 |
|
|
.addrb(ra0),
|
| 117 |
|
|
.doutb(o00)
|
| 118 |
|
|
);
|
| 119 |
|
|
|
| 120 |
|
|
FT64_regfileRam_sim urf11 (
|
| 121 |
|
|
.clka(clk4x),
|
| 122 |
|
|
.ena(wr),
|
| 123 |
|
|
.wea(we),
|
| 124 |
|
|
.addra(wa),
|
| 125 |
|
|
.dina(i),
|
| 126 |
|
|
.clkb(rclk),
|
| 127 |
|
|
.enb(1'b1),
|
| 128 |
|
|
.addrb(ra1),
|
| 129 |
|
|
.doutb(o01)
|
| 130 |
|
|
);
|
| 131 |
|
|
|
| 132 |
|
|
FT64_regfileRam_sim urf12 (
|
| 133 |
|
|
.clka(clk4x),
|
| 134 |
|
|
.ena(wr),
|
| 135 |
|
|
.wea(we),
|
| 136 |
|
|
.addra(wa),
|
| 137 |
|
|
.dina(i),
|
| 138 |
|
|
.clkb(rclk),
|
| 139 |
|
|
.enb(1'b1),
|
| 140 |
|
|
.addrb(ra2),
|
| 141 |
|
|
.doutb(o02)
|
| 142 |
|
|
);
|
| 143 |
|
|
|
| 144 |
|
|
FT64_regfileRam_sim urf13 (
|
| 145 |
|
|
.clka(clk4x),
|
| 146 |
|
|
.ena(wr),
|
| 147 |
|
|
.wea(we),
|
| 148 |
|
|
.addra(wa),
|
| 149 |
|
|
.dina(i),
|
| 150 |
|
|
.clkb(rclk),
|
| 151 |
|
|
.enb(1'b1),
|
| 152 |
|
|
.addrb(ra3),
|
| 153 |
|
|
.doutb(o03)
|
| 154 |
|
|
);
|
| 155 |
|
|
|
| 156 |
|
|
FT64_regfileRam_sim urf14 (
|
| 157 |
|
|
.clka(clk4x),
|
| 158 |
|
|
.ena(wr),
|
| 159 |
|
|
.wea(we),
|
| 160 |
|
|
.addra(wa),
|
| 161 |
|
|
.dina(i),
|
| 162 |
|
|
.clkb(rclk),
|
| 163 |
|
|
.enb(1'b1),
|
| 164 |
|
|
.addrb(ra4),
|
| 165 |
|
|
.doutb(o04)
|
| 166 |
|
|
);
|
| 167 |
|
|
|
| 168 |
|
|
FT64_regfileRam_sim urf15 (
|
| 169 |
|
|
.clka(clk4x),
|
| 170 |
|
|
.ena(wr),
|
| 171 |
|
|
.wea(we),
|
| 172 |
|
|
.addra(wa),
|
| 173 |
|
|
.dina(i),
|
| 174 |
|
|
.clkb(rclk),
|
| 175 |
|
|
.enb(1'b1),
|
| 176 |
|
|
.addrb(ra5),
|
| 177 |
|
|
.doutb(o05)
|
| 178 |
|
|
);
|
| 179 |
|
|
`else
|
| 180 |
|
|
FT64_regfileRam urf10 (
|
| 181 |
|
|
.clka(clk4x),
|
| 182 |
|
|
.ena(wr),
|
| 183 |
|
|
.wea(we),
|
| 184 |
|
|
.addra(wa),
|
| 185 |
|
|
.dina(i),
|
| 186 |
|
|
.clkb(rclk),
|
| 187 |
|
|
.enb(1'b1),
|
| 188 |
50 |
robfinch |
.web(1'b0),
|
| 189 |
48 |
robfinch |
.addrb(ra0),
|
| 190 |
50 |
robfinch |
.dinb(8'h00),
|
| 191 |
48 |
robfinch |
.doutb(o00)
|
| 192 |
|
|
);
|
| 193 |
|
|
|
| 194 |
|
|
FT64_regfileRam urf11 (
|
| 195 |
|
|
.clka(clk4x),
|
| 196 |
|
|
.ena(wr),
|
| 197 |
|
|
.wea(we),
|
| 198 |
|
|
.addra(wa),
|
| 199 |
|
|
.dina(i),
|
| 200 |
|
|
.clkb(rclk),
|
| 201 |
|
|
.enb(1'b1),
|
| 202 |
50 |
robfinch |
.web(1'b0),
|
| 203 |
48 |
robfinch |
.addrb(ra1),
|
| 204 |
50 |
robfinch |
.dinb(8'h00),
|
| 205 |
48 |
robfinch |
.doutb(o01)
|
| 206 |
|
|
);
|
| 207 |
|
|
|
| 208 |
|
|
FT64_regfileRam urf12 (
|
| 209 |
|
|
.clka(clk4x),
|
| 210 |
|
|
.ena(wr),
|
| 211 |
|
|
.wea(we),
|
| 212 |
|
|
.addra(wa),
|
| 213 |
|
|
.dina(i),
|
| 214 |
|
|
.clkb(rclk),
|
| 215 |
|
|
.enb(1'b1),
|
| 216 |
50 |
robfinch |
.web(1'b0),
|
| 217 |
48 |
robfinch |
.addrb(ra2),
|
| 218 |
50 |
robfinch |
.dinb(8'h00),
|
| 219 |
48 |
robfinch |
.doutb(o02)
|
| 220 |
|
|
);
|
| 221 |
|
|
|
| 222 |
|
|
FT64_regfileRam urf13 (
|
| 223 |
|
|
.clka(clk4x),
|
| 224 |
|
|
.ena(wr),
|
| 225 |
|
|
.wea(we),
|
| 226 |
|
|
.addra(wa),
|
| 227 |
|
|
.dina(i),
|
| 228 |
|
|
.clkb(rclk),
|
| 229 |
|
|
.enb(1'b1),
|
| 230 |
50 |
robfinch |
.web(1'b0),
|
| 231 |
48 |
robfinch |
.addrb(ra3),
|
| 232 |
50 |
robfinch |
.dinb(8'h00),
|
| 233 |
48 |
robfinch |
.doutb(o03)
|
| 234 |
|
|
);
|
| 235 |
|
|
|
| 236 |
|
|
FT64_regfileRam urf14 (
|
| 237 |
|
|
.clka(clk4x),
|
| 238 |
|
|
.ena(wr),
|
| 239 |
|
|
.wea(we),
|
| 240 |
|
|
.addra(wa),
|
| 241 |
|
|
.dina(i),
|
| 242 |
|
|
.clkb(rclk),
|
| 243 |
|
|
.enb(1'b1),
|
| 244 |
50 |
robfinch |
.web(1'b0),
|
| 245 |
48 |
robfinch |
.addrb(ra4),
|
| 246 |
50 |
robfinch |
.dinb(8'h00),
|
| 247 |
48 |
robfinch |
.doutb(o04)
|
| 248 |
|
|
);
|
| 249 |
|
|
|
| 250 |
|
|
FT64_regfileRam urf15 (
|
| 251 |
|
|
.clka(clk4x),
|
| 252 |
|
|
.ena(wr),
|
| 253 |
|
|
.wea(we),
|
| 254 |
|
|
.addra(wa),
|
| 255 |
|
|
.dina(i),
|
| 256 |
|
|
.clkb(rclk),
|
| 257 |
|
|
.enb(1'b1),
|
| 258 |
50 |
robfinch |
.web(1'b0),
|
| 259 |
48 |
robfinch |
.addrb(ra5),
|
| 260 |
50 |
robfinch |
.dinb(8'h00),
|
| 261 |
48 |
robfinch |
.doutb(o05)
|
| 262 |
|
|
);
|
| 263 |
|
|
`endif
|
| 264 |
|
|
|
| 265 |
|
|
// The same clock edge that would normally update the register file is the
|
| 266 |
|
|
// clock edge that causes the data to disappear for the next cycle. The
|
| 267 |
|
|
// data needs to be held onto so that it can update the register file on
|
| 268 |
|
|
// the next 4x clock.
|
| 269 |
|
|
always @(posedge clk)
|
| 270 |
|
|
begin
|
| 271 |
|
|
wr1x <= wr1;
|
| 272 |
|
|
we1x <= we1;
|
| 273 |
|
|
wa1x <= wa1;
|
| 274 |
|
|
i1x <= i1;
|
| 275 |
|
|
end
|
| 276 |
|
|
|
| 277 |
|
|
reg wclk2;
|
| 278 |
|
|
always @(posedge clk4x)
|
| 279 |
|
|
begin
|
| 280 |
|
|
wclk2 <= clk;
|
| 281 |
|
|
if (clk & ~wclk2) begin
|
| 282 |
|
|
wr <= wr0;
|
| 283 |
|
|
we <= we0;
|
| 284 |
|
|
wa <= wa0;
|
| 285 |
|
|
i <= i0;
|
| 286 |
|
|
end
|
| 287 |
|
|
else if (~clk & wclk2) begin
|
| 288 |
|
|
wr <= wr1x;
|
| 289 |
|
|
we <= we1x;
|
| 290 |
|
|
wa <= wa1x;
|
| 291 |
|
|
i <= i1x;
|
| 292 |
|
|
end
|
| 293 |
|
|
else begin
|
| 294 |
|
|
wr <= 1'b0;
|
| 295 |
|
|
we <= 8'h00;
|
| 296 |
|
|
wa <= 'd0;
|
| 297 |
|
|
i <= 'd0;
|
| 298 |
|
|
end
|
| 299 |
|
|
end
|
| 300 |
|
|
|
| 301 |
|
|
assign o0[7:0] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 302 |
|
|
(wr1 && we1[0] && (ra0==wa1)) ? i1[7:0] :
|
| 303 |
|
|
(wr0 && we0[0] && (ra0==wa0)) ? i0[7:0] : o00[7:0];
|
| 304 |
|
|
assign o0[15:8] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 305 |
|
|
(wr1 && we1[1] && (ra0==wa1)) ? i1[15:8] :
|
| 306 |
|
|
(wr0 && we0[1] && (ra0==wa0)) ? i0[15:8] : o00[15:8];
|
| 307 |
|
|
assign o0[23:16] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 308 |
|
|
(wr1 && we1[2] && (ra0==wa1)) ? i1[23:16] :
|
| 309 |
|
|
(wr0 && we0[2] && (ra0==wa0)) ? i0[23:16] : o00[23:16];
|
| 310 |
|
|
assign o0[31:24] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 311 |
|
|
(wr1 && we1[3] && (ra0==wa1)) ? i1[31:24] :
|
| 312 |
|
|
(wr0 && we0[3] && (ra0==wa0)) ? i0[31:24] : o00[31:24];
|
| 313 |
|
|
assign o0[39:32] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 314 |
|
|
(wr1 && we1[4] && (ra0==wa1)) ? i1[39:32] :
|
| 315 |
|
|
(wr0 && we0[4] && (ra0==wa0)) ? i0[39:32] : o00[39:32];
|
| 316 |
|
|
assign o0[47:40] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 317 |
|
|
(wr1 && we1[5] && (ra0==wa1)) ? i1[47:40] :
|
| 318 |
|
|
(wr0 && we0[5] && (ra0==wa0)) ? i0[47:40] : o00[47:40];
|
| 319 |
|
|
assign o0[55:48] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 320 |
|
|
(wr1 && we1[6] && (ra0==wa1)) ? i1[55:48] :
|
| 321 |
|
|
(wr0 && we0[6] && (ra0==wa0)) ? i0[55:48] : o00[55:48];
|
| 322 |
|
|
assign o0[55:48] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 323 |
|
|
(wr1 && we1[6] && (ra0==wa1)) ? i1[55:48] :
|
| 324 |
|
|
(wr0 && we0[6] && (ra0==wa0)) ? i0[55:48] : o00[55:48];
|
| 325 |
|
|
assign o0[63:56] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 326 |
|
|
(wr1 && we1[7] && (ra0==wa1)) ? i1[63:56] :
|
| 327 |
|
|
(wr0 && we0[7] && (ra0==wa0)) ? i0[63:56] : o00[63:56];
|
| 328 |
|
|
|
| 329 |
|
|
assign o1[7:0] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 330 |
|
|
(wr1 && we1[0] && (ra1==wa1)) ? i1[7:0] :
|
| 331 |
|
|
(wr0 && we0[0] && (ra1==wa0)) ? i0[7:0] : o01[7:0];
|
| 332 |
|
|
assign o1[15:8] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 333 |
|
|
(wr1 && we1[1] && (ra1==wa1)) ? i1[15:8] :
|
| 334 |
|
|
(wr0 && we0[1] && (ra1==wa0)) ? i0[15:8] : o01[15:8];
|
| 335 |
|
|
assign o1[23:16] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 336 |
|
|
(wr1 && we1[2] && (ra1==wa1)) ? i1[23:16] :
|
| 337 |
|
|
(wr0 && we0[2] && (ra1==wa0)) ? i0[23:16] : o01[23:16];
|
| 338 |
|
|
assign o1[31:24] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 339 |
|
|
(wr1 && we1[3] && (ra1==wa1)) ? i1[31:24] :
|
| 340 |
|
|
(wr0 && we0[3] && (ra1==wa0)) ? i0[31:24] : o01[31:24];
|
| 341 |
|
|
assign o1[39:32] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 342 |
|
|
(wr1 && we1[4] && (ra1==wa1)) ? i1[39:32] :
|
| 343 |
|
|
(wr0 && we0[4] && (ra1==wa0)) ? i0[39:32] : o01[39:32];
|
| 344 |
|
|
assign o1[47:40] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 345 |
|
|
(wr1 && we1[5] && (ra1==wa1)) ? i1[47:40] :
|
| 346 |
|
|
(wr0 && we0[5] && (ra1==wa0)) ? i0[47:40] : o01[47:40];
|
| 347 |
|
|
assign o1[55:48] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 348 |
|
|
(wr1 && we1[6] && (ra1==wa1)) ? i1[55:48] :
|
| 349 |
|
|
(wr0 && we0[6] && (ra1==wa0)) ? i0[55:48] : o01[55:48];
|
| 350 |
|
|
assign o1[55:48] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 351 |
|
|
(wr1 && we1[6] && (ra1==wa1)) ? i1[55:48] :
|
| 352 |
|
|
(wr0 && we0[6] && (ra1==wa0)) ? i0[55:48] : o01[55:48];
|
| 353 |
|
|
assign o1[63:56] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 354 |
|
|
(wr1 && we1[7] && (ra1==wa1)) ? i1[63:56] :
|
| 355 |
|
|
(wr0 && we0[7] && (ra1==wa0)) ? i0[63:56] : o01[63:56];
|
| 356 |
|
|
|
| 357 |
|
|
assign o2[7:0] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 358 |
|
|
(wr1 && we1[0] && (ra2==wa1)) ? i1[7:0] :
|
| 359 |
|
|
(wr0 && we0[0] && (ra2==wa0)) ? i0[7:0] : o02[7:0];
|
| 360 |
|
|
assign o2[15:8] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 361 |
|
|
(wr1 && we1[1] && (ra2==wa1)) ? i1[15:8] :
|
| 362 |
|
|
(wr0 && we0[1] && (ra2==wa0)) ? i0[15:8] : o02[15:8];
|
| 363 |
|
|
assign o2[23:16] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 364 |
|
|
(wr1 && we1[2] && (ra2==wa1)) ? i1[23:16] :
|
| 365 |
|
|
(wr0 && we0[2] && (ra2==wa0)) ? i0[23:16] : o02[23:16];
|
| 366 |
|
|
assign o2[31:24] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 367 |
|
|
(wr1 && we1[3] && (ra2==wa1)) ? i1[31:24] :
|
| 368 |
|
|
(wr0 && we0[3] && (ra2==wa0)) ? i0[31:24] : o02[31:24];
|
| 369 |
|
|
assign o2[39:32] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 370 |
|
|
(wr1 && we1[4] && (ra2==wa1)) ? i1[39:32] :
|
| 371 |
|
|
(wr0 && we0[4] && (ra2==wa0)) ? i0[39:32] : o02[39:32];
|
| 372 |
|
|
assign o2[47:40] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 373 |
|
|
(wr1 && we1[5] && (ra2==wa1)) ? i1[47:40] :
|
| 374 |
|
|
(wr0 && we0[5] && (ra2==wa0)) ? i0[47:40] : o02[47:40];
|
| 375 |
|
|
assign o2[55:48] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 376 |
|
|
(wr1 && we1[6] && (ra2==wa1)) ? i1[55:48] :
|
| 377 |
|
|
(wr0 && we0[6] && (ra2==wa0)) ? i0[55:48] : o02[55:48];
|
| 378 |
|
|
assign o2[55:48] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 379 |
|
|
(wr1 && we1[6] && (ra2==wa1)) ? i1[55:48] :
|
| 380 |
|
|
(wr0 && we0[6] && (ra2==wa0)) ? i0[55:48] : o02[55:48];
|
| 381 |
|
|
assign o2[63:56] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 382 |
|
|
(wr1 && we1[7] && (ra2==wa1)) ? i1[63:56] :
|
| 383 |
|
|
(wr0 && we0[7] && (ra2==wa0)) ? i0[63:56] : o02[63:56];
|
| 384 |
|
|
|
| 385 |
|
|
assign o3[7:0] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 386 |
|
|
(wr1 && we1[0] && (ra3==wa1)) ? i1[7:0] :
|
| 387 |
|
|
(wr0 && we0[0] && (ra3==wa0)) ? i0[7:0] : o03[7:0];
|
| 388 |
|
|
assign o3[15:8] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 389 |
|
|
(wr1 && we1[1] && (ra3==wa1)) ? i1[15:8] :
|
| 390 |
|
|
(wr0 && we0[1] && (ra3==wa0)) ? i0[15:8] : o03[15:8];
|
| 391 |
|
|
assign o3[23:16] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 392 |
|
|
(wr1 && we1[2] && (ra3==wa1)) ? i1[23:16] :
|
| 393 |
|
|
(wr0 && we0[2] && (ra3==wa0)) ? i0[23:16] : o03[23:16];
|
| 394 |
|
|
assign o3[31:24] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 395 |
|
|
(wr1 && we1[3] && (ra3==wa1)) ? i1[31:24] :
|
| 396 |
|
|
(wr0 && we0[3] && (ra3==wa0)) ? i0[31:24] : o03[31:24];
|
| 397 |
|
|
assign o3[39:32] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 398 |
|
|
(wr1 && we1[4] && (ra3==wa1)) ? i1[39:32] :
|
| 399 |
|
|
(wr0 && we0[4] && (ra3==wa0)) ? i0[39:32] : o03[39:32];
|
| 400 |
|
|
assign o3[47:40] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 401 |
|
|
(wr1 && we1[5] && (ra3==wa1)) ? i1[47:40] :
|
| 402 |
|
|
(wr0 && we0[5] && (ra3==wa0)) ? i0[47:40] : o03[47:40];
|
| 403 |
|
|
assign o3[55:48] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 404 |
|
|
(wr1 && we1[6] && (ra3==wa1)) ? i1[55:48] :
|
| 405 |
|
|
(wr0 && we0[6] && (ra3==wa0)) ? i0[55:48] : o03[55:48];
|
| 406 |
|
|
assign o3[55:48] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 407 |
|
|
(wr1 && we1[6] && (ra3==wa1)) ? i1[55:48] :
|
| 408 |
|
|
(wr0 && we0[6] && (ra3==wa0)) ? i0[55:48] : o03[55:48];
|
| 409 |
|
|
assign o3[63:56] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 410 |
|
|
(wr1 && we1[7] && (ra3==wa1)) ? i1[63:56] :
|
| 411 |
|
|
(wr0 && we0[7] && (ra3==wa0)) ? i0[63:56] : o03[63:56];
|
| 412 |
|
|
|
| 413 |
|
|
assign o4[7:0] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 414 |
|
|
(wr1 && we1[0] && (ra4==wa1)) ? i1[7:0] :
|
| 415 |
|
|
(wr0 && we0[0] && (ra4==wa0)) ? i0[7:0] : o04[7:0];
|
| 416 |
|
|
assign o4[15:8] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 417 |
|
|
(wr1 && we1[1] && (ra4==wa1)) ? i1[15:8] :
|
| 418 |
|
|
(wr0 && we0[1] && (ra4==wa0)) ? i0[15:8] : o04[15:8];
|
| 419 |
|
|
assign o4[23:16] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 420 |
|
|
(wr1 && we1[2] && (ra4==wa1)) ? i1[23:16] :
|
| 421 |
|
|
(wr0 && we0[2] && (ra4==wa0)) ? i0[23:16] : o04[23:16];
|
| 422 |
|
|
assign o4[31:24] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 423 |
|
|
(wr1 && we1[3] && (ra4==wa1)) ? i1[31:24] :
|
| 424 |
|
|
(wr0 && we0[3] && (ra4==wa0)) ? i0[31:24] : o04[31:24];
|
| 425 |
|
|
assign o4[39:32] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 426 |
|
|
(wr1 && we1[4] && (ra4==wa1)) ? i1[39:32] :
|
| 427 |
|
|
(wr0 && we0[4] && (ra4==wa0)) ? i0[39:32] : o04[39:32];
|
| 428 |
|
|
assign o4[47:40] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 429 |
|
|
(wr1 && we1[5] && (ra4==wa1)) ? i1[47:40] :
|
| 430 |
|
|
(wr0 && we0[5] && (ra4==wa0)) ? i0[47:40] : o04[47:40];
|
| 431 |
|
|
assign o4[55:48] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 432 |
|
|
(wr1 && we1[6] && (ra4==wa1)) ? i1[55:48] :
|
| 433 |
|
|
(wr0 && we0[6] && (ra4==wa0)) ? i0[55:48] : o04[55:48];
|
| 434 |
|
|
assign o4[55:48] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 435 |
|
|
(wr1 && we1[6] && (ra4==wa1)) ? i1[55:48] :
|
| 436 |
|
|
(wr0 && we0[6] && (ra4==wa0)) ? i0[55:48] : o04[55:48];
|
| 437 |
|
|
assign o4[63:56] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 438 |
|
|
(wr1 && we1[7] && (ra4==wa1)) ? i1[63:56] :
|
| 439 |
|
|
(wr0 && we0[7] && (ra4==wa0)) ? i0[63:56] : o04[63:56];
|
| 440 |
|
|
|
| 441 |
|
|
assign o5[7:0] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 442 |
|
|
(wr1 && we1[0] && (ra5==wa1)) ? i1[7:0] :
|
| 443 |
|
|
(wr0 && we0[0] && (ra5==wa0)) ? i0[7:0] : o05[7:0];
|
| 444 |
|
|
assign o5[15:8] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 445 |
|
|
(wr1 && we1[1] && (ra5==wa1)) ? i1[15:8] :
|
| 446 |
|
|
(wr0 && we0[1] && (ra5==wa0)) ? i0[15:8] : o05[15:8];
|
| 447 |
|
|
assign o5[23:16] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 448 |
|
|
(wr1 && we1[2] && (ra5==wa1)) ? i1[23:16] :
|
| 449 |
|
|
(wr0 && we0[2] && (ra5==wa0)) ? i0[23:16] : o05[23:16];
|
| 450 |
|
|
assign o5[31:24] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 451 |
|
|
(wr1 && we1[3] && (ra5==wa1)) ? i1[31:24] :
|
| 452 |
|
|
(wr0 && we0[3] && (ra5==wa0)) ? i0[31:24] : o05[31:24];
|
| 453 |
|
|
assign o5[39:32] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 454 |
|
|
(wr1 && we1[4] && (ra5==wa1)) ? i1[39:32] :
|
| 455 |
|
|
(wr0 && we0[4] && (ra5==wa0)) ? i0[39:32] : o05[39:32];
|
| 456 |
|
|
assign o5[47:40] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 457 |
|
|
(wr1 && we1[5] && (ra5==wa1)) ? i1[47:40] :
|
| 458 |
|
|
(wr0 && we0[5] && (ra5==wa0)) ? i0[47:40] : o05[47:40];
|
| 459 |
|
|
assign o5[55:48] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 460 |
|
|
(wr1 && we1[6] && (ra5==wa1)) ? i1[55:48] :
|
| 461 |
|
|
(wr0 && we0[6] && (ra5==wa0)) ? i0[55:48] : o05[55:48];
|
| 462 |
|
|
assign o5[55:48] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 463 |
|
|
(wr1 && we1[6] && (ra5==wa1)) ? i1[55:48] :
|
| 464 |
|
|
(wr0 && we0[6] && (ra5==wa0)) ? i0[55:48] : o05[55:48];
|
| 465 |
|
|
assign o5[63:56] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 466 |
|
|
(wr1 && we1[7] && (ra5==wa1)) ? i1[63:56] :
|
| 467 |
|
|
(wr0 && we0[7] && (ra5==wa0)) ? i0[63:56] : o05[63:56];
|
| 468 |
|
|
/*
|
| 469 |
|
|
assign o5 = ra5[4:0]==5'd0 ? {WID{1'b0}} :
|
| 470 |
|
|
(wr1 && (ra5==wa1)) ? i1 :
|
| 471 |
|
|
(wr0 && (ra5==wa0)) ? i0 : o05;
|
| 472 |
|
|
|
| 473 |
|
|
*/
|
| 474 |
|
|
endmodule
|
| 475 |
|
|
|
