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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [common/] [FT64_idecoder.v] - Blame information for rev 60

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1 60 robfinch 
// ============================================================================
2 
//        __
3 
//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
4 
//    \  __ /    All rights reserved.
5 
//     \/_//     robfinch<remove>@finitron.ca
6 
//       ||
7 
//
8 
//      FT64_idecoder.v
9 
//
10 
// This source file is free software: you can redistribute it and/or modify
11 
// it under the terms of the GNU Lesser General Public License as published
12 
// by the Free Software Foundation, either version 3 of the License, or
13 
// (at your option) any later version.
14 
//
15 
// This source file is distributed in the hope that it will be useful,
16 
// but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 
// GNU General Public License for more details.
19 
//
20 
// You should have received a copy of the GNU General Public License
21 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
22 
//
23 
// ============================================================================
24 
//
25 
`include ".\FT64_config.vh"
26 
`include ".\FT64_defines.vh"
27 
 
28 
module FT64_idecoder(clk,idv_i,id_i,instr,vl,ven,thrd,predict_taken,Rt,bus,id_o,idv_o,debug_on,pred_on);
29 
input clk;
30 
input idv_i;
31 
input [4:0] id_i;
32 
input [47:0] instr;
33 
input [7:0] vl;
34 
input [5:0] ven;
35 
input thrd;
36 
input predict_taken;
37 
input [4:0] Rt;
38 
output reg [143:0] bus;
39 
output reg [4:0] id_o;
40 
output reg idv_o;
41 
input debug_on;
42 
input pred_on;
43 
 
44 
parameter TRUE = 1'b1;
45 
parameter FALSE = 1'b0;
46 
// Memory access sizes
47 
parameter byt = 3'd0;
48 
parameter wyde = 3'd1;
49 
parameter tetra = 3'd2;
50 
parameter octa = 3'd3;
51 
 
52 
// Really IsPredictableBranch
53 
// Does not include BccR's
54 
//function IsBranch;
55 
//input [47:0] isn;
56 
//casez(isn[`INSTRUCTION_OP])
57 
//`Bcc:   IsBranch = TRUE;
58 
//`BBc:   IsBranch = TRUE;
59 
//`BEQI:  IsBranch = TRUE;
60 
//`CHK:   IsBranch = TRUE;
61 
//default:    IsBranch = FALSE;
62 
//endcase
63 
//endfunction
64 
 
65 
wire [10:0] brdisp = instr[31:21];
66 
 
67 
wire iAlu;
68 
mIsALU uialu1
69 
(
70 
        .instr(instr),
71 
        .IsALU(iAlu)
72 
);
73 
 
74 
function IsTLB;
75 
input [47:0] isn;
76 
case(isn[`INSTRUCTION_OP])
77 
`R2:
78 
  case(isn[`INSTRUCTION_S2])
79 
  `TLB:   IsTLB = TRUE;
80 
  default:    IsTLB = FALSE;
81 
  endcase
82 
default:    IsTLB = FALSE;
83 
endcase
84 
endfunction
85 
 
86 
reg IsALU;
87 
always @*
88 
case(instr[`INSTRUCTION_OP])
89 
`R2:
90 
        if (instr[`INSTRUCTION_L2]==2'b00)
91 
                case(instr[`INSTRUCTION_S2])
92 
                `VMOV:          IsALU = TRUE;
93 
    `RTI:       IsALU = FALSE;
94 
    default:    IsALU = TRUE;
95 
    endcase
96 
  else
97 
        IsALU = TRUE;
98 
`BRK:   IsALU = FALSE;
99 
`Bcc:   IsALU = FALSE;
100 
`BBc:   IsALU = FALSE;
101 
`BEQI:  IsALU = FALSE;
102 
`CHK:   IsALU = FALSE;
103 
`JAL:   IsALU = FALSE;
104 
`JMP:   IsALU = FALSE;
105 
`CALL:  IsALU = FALSE;
106 
`RET:   IsALU = FALSE;
107 
`FVECTOR:
108 
        case(instr[`INSTRUCTION_S2])
109 
  `VSHL,`VSHR,`VASR:  IsALU = TRUE;
110 
  default:    IsALU = FALSE;  // Integer
111 
  endcase
112 
`IVECTOR:
113 
        case(instr[`INSTRUCTION_S2])
114 
  `VSHL,`VSHR,`VASR:  IsALU = TRUE;
115 
  default:    IsALU = TRUE;  // Integer
116 
  endcase
117 
`FLOAT:         IsALU = FALSE;
118 
default:    IsALU = TRUE;
119 
endcase
120 
 
121 
function IsAlu0Only;
122 
input [47:0] isn;
123 
begin
124 
case(isn[`INSTRUCTION_OP])
125 
`R2:
126 
        if (isn[`INSTRUCTION_L2]==2'b00)
127 
                case(isn[`INSTRUCTION_S2])
128 
                `TLB:                           IsAlu0Only = TRUE;
129 
                `R1:        IsAlu0Only = TRUE;
130 
                `SHIFTR,`SHIFT31,`SHIFT63:
131 
                        IsAlu0Only = !(instr[25:23]==`SHL || instr[25:23]==`ASL);
132 
                `MULU,`MULSU,`MUL,
133 
                `MULUH,`MULSUH,`MULH,
134 
                `MODU,`MODSU,`MOD: IsAlu0Only = TRUE;
135 
                `DIVU,`DIVSU,`DIV: IsAlu0Only = TRUE;
136 
                `MIN,`MAX:  IsAlu0Only = TRUE;
137 
                default:    IsAlu0Only = FALSE;
138 
                endcase
139 
        else
140 
                IsAlu0Only = FALSE;
141 
`MEMNDX:        IsAlu0Only = TRUE;
142 
`IVECTOR,`FVECTOR:
143 
        case(isn[`INSTRUCTION_S2])
144 
        `VSHL,`VSHR,`VASR:  IsAlu0Only = TRUE;
145 
        default: IsAlu0Only = FALSE;
146 
        endcase
147 
`BITFIELD:  IsAlu0Only = TRUE;
148 
`MULUI,`MULI,
149 
`DIVUI,`DIVI,
150 
`MODI:   IsAlu0Only = TRUE;
151 
`CSRRW: IsAlu0Only = TRUE;
152 
default:    IsAlu0Only = FALSE;
153 
endcase
154 
end
155 
endfunction
156 
 
157 
function IsFPU;
158 
input [47:0] isn;
159 
begin
160 
case(isn[`INSTRUCTION_OP])
161 
`FLOAT: IsFPU = TRUE;
162 
`FVECTOR:
163 
                    case(isn[`INSTRUCTION_S2])
164 
            `VSHL,`VSHR,`VASR:  IsFPU = FALSE;
165 
            default:    IsFPU = TRUE;
166 
            endcase
167 
default:    IsFPU = FALSE;
168 
endcase
169 
end
170 
endfunction
171 
 
172 
reg IsFlowCtrl;
173 
always @*
174 
case(instr[`INSTRUCTION_OP])
175 
`BRK:    IsFlowCtrl <= TRUE;
176 
`R2:    case(instr[`INSTRUCTION_S2])
177 
        `RTI:   IsFlowCtrl <= TRUE;
178 
        default:    IsFlowCtrl <= FALSE;
179 
        endcase
180 
`Bcc:   IsFlowCtrl <= TRUE;
181 
`BBc:           IsFlowCtrl <= TRUE;
182 
`BEQI:  IsFlowCtrl <= TRUE;
183 
`CHK:   IsFlowCtrl <= TRUE;
184 
`JAL:   IsFlowCtrl <= TRUE;
185 
`JMP:           IsFlowCtrl <= TRUE;
186 
`CALL:  IsFlowCtrl <= TRUE;
187 
`RET:   IsFlowCtrl <= TRUE;
188 
default:    IsFlowCtrl <= FALSE;
189 
endcase
190 
 
191 
//function IsFlowCtrl;
192 
//input [47:0] isn;
193 
//begin
194 
//case(isn[`INSTRUCTION_OP])
195 
//`BRK:    IsFlowCtrl = TRUE;
196 
//`RR:    case(isn[`INSTRUCTION_S2])
197 
//        `RTI:   IsFlowCtrl = TRUE;
198 
//        default:    IsFlowCtrl = FALSE;
199 
//        endcase
200 
//`Bcc:   IsFlowCtrl = TRUE;
201 
//`BBc:         IsFlowCtrl = TRUE;
202 
//`BEQI:  IsFlowCtrl = TRUE;
203 
//`CHK:   IsFlowCtrl = TRUE;
204 
//`JAL:   IsFlowCtrl = TRUE;
205 
//`JMP:         IsFlowCtrl = TRUE;
206 
//`CALL:  IsFlowCtrl = TRUE;
207 
//`RET:   IsFlowCtrl = TRUE;
208 
//default:    IsFlowCtrl = FALSE;
209 
//endcase
210 
//end
211 
//endfunction
212 
 
213 
// fnCanException
214 
//
215 
// Used by memory issue logic (stores).
216 
// Returns TRUE if the instruction can cause an exception.
217 
// In debug mode any instruction could potentially cause a breakpoint exception.
218 
// Rather than check all the addresses for potential debug exceptions it's
219 
// simpler to just have it so that all instructions could exception. This will
220 
// slow processing down somewhat as stores will only be done at the head of the
221 
// instruction queue, but it's debug mode so we probably don't care.
222 
//
223 
function fnCanException;
224 
input [47:0] isn;
225 
begin
226 
// ToDo add debug_on as input
227 
`ifdef SUPPORT_DBG
228 
if (debug_on)
229 
    fnCanException = `TRUE;
230 
else
231 
`endif
232 
case(isn[`INSTRUCTION_OP])
233 
`FLOAT:
234 
    case(isn[`INSTRUCTION_S2])
235 
    `FDIV,`FMUL,`FADD,`FSUB,`FTX:
236 
        fnCanException = `TRUE;
237 
    default:    fnCanException = `FALSE;
238 
    endcase
239 
`DIVI,`MODI,`MULI:
240 
    fnCanException = `TRUE;
241 
`R2:
242 
    case(isn[`INSTRUCTION_S2])
243 
    `MUL,
244 
    `DIV,`MULSU,`DIVSU,
245 
    `MOD,`MODSU:
246 
       fnCanException = TRUE;
247 
    `RTI:   fnCanException = TRUE;
248 
    default:    fnCanException = FALSE;
249 
    endcase
250 
// Had branches that could exception if looping to self. But in a tight loop
251 
// it affects store performance.
252 
// -> A branch may only exception if it loops back to itself.
253 
`Bcc,`BBc,`BEQI:        fnCanException = isn[7] ? brdisp == 11'h7FF : brdisp == 11'h7FE;
254 
`CHK:   fnCanException = TRUE;
255 
default:
256 
// Stores can stil exception if there is a write buffer, but we allow following
257 
// stores to be issued by ignoring the fact they can exception because the stores
258 
// can be undone by invalidating the write buffer.
259 
`ifdef HAS_WB
260 
    fnCanException = IsMem(isn) && !IsStore(isn);
261 
`else
262 
    fnCanException = IsMem(isn);
263 
`endif
264 
endcase
265 
end
266 
endfunction
267 
 
268 
function IsLoad;
269 
input [47:0] isn;
270 
case(isn[`INSTRUCTION_OP])
271 
`MEMNDX:        IsLoad = !isn[31];
272 
`LB:    IsLoad = TRUE;
273 
`LBU:   IsLoad = TRUE;
274 
`Lx:    IsLoad = TRUE;
275 
`LxU:   IsLoad = TRUE;
276 
`LWR:   IsLoad = TRUE;
277 
`LV:    IsLoad = TRUE;
278 
`LVx:   IsLoad = TRUE;
279 
`LVxU:  IsLoad = TRUE;
280 
default:    IsLoad = FALSE;
281 
endcase
282 
endfunction
283 
 
284 
function IsVolatileLoad;
285 
input [47:0] isn;
286 
case(isn[`INSTRUCTION_OP])
287 
`MEMNDX:
288 
        if (isn[`INSTRUCTION_L2]==2'b00)
289 
    case({isn[31:28],isn[22:21]})
290 
    `LWRX:      IsVolatileLoad = TRUE;
291 
    `LVBX:      IsVolatileLoad = TRUE;
292 
    `LVBUX:     IsVolatileLoad = TRUE;
293 
    `LVCX:      IsVolatileLoad = TRUE;
294 
    `LVCUX:     IsVolatileLoad = TRUE;
295 
    `LVHX:      IsVolatileLoad = TRUE;
296 
    `LVHUX:     IsVolatileLoad = TRUE;
297 
    `LVWX:      IsVolatileLoad = TRUE;
298 
    default: IsVolatileLoad = FALSE;
299 
    endcase
300 
        else
301 
                IsVolatileLoad = FALSE;
302 
`LWR:   IsVolatileLoad = TRUE;
303 
`LVx:   IsVolatileLoad = TRUE;
304 
`LVxU:  IsVolatileLoad = TRUE;
305 
default:    IsVolatileLoad = FALSE;
306 
endcase
307 
endfunction
308 
 
309 
function IsStore;
310 
input [47:0] isn;
311 
case(isn[`INSTRUCTION_OP])
312 
`MEMNDX:
313 
        if (isn[`INSTRUCTION_L2]==2'b10) begin
314 
                if (isn[31])
315 
                        case({isn[31:28],isn[17:16]})
316 
                        `PUSH:  IsStore = TRUE;
317 
            default:    IsStore = FALSE;
318 
                        endcase
319 
                else
320 
                        IsStore = FALSE;
321 
        end
322 
        else if (isn[`INSTRUCTION_L2]==2'b00)
323 
                case({isn[31:28],isn[17:16]})
324 
                `PUSH:  IsStore = TRUE;
325 
    `SBX:   IsStore = TRUE;
326 
    `SCX:   IsStore = TRUE;
327 
    `SHX:   IsStore = TRUE;
328 
    `SWX:   IsStore = TRUE;
329 
    `SWCX:  IsStore = TRUE;
330 
    `SVX:   IsStore = TRUE;
331 
    `CASX:  IsStore = TRUE;
332 
    `INC:       IsStore = TRUE;
333 
    default:    IsStore = FALSE;
334 
    endcase
335 
        else
336 
                IsStore = FALSE;
337 
`SB:    IsStore = TRUE;
338 
`Sx:    IsStore = TRUE;
339 
`SWC:   IsStore = TRUE;
340 
`INC:   IsStore = TRUE;
341 
`SV:    IsStore = TRUE;
342 
`CAS:   IsStore = TRUE;
343 
`AMO:   IsStore = TRUE;
344 
default:    IsStore = FALSE;
345 
endcase
346 
endfunction
347 
 
348 
function IsPush;
349 
input [47:0] isn;
350 
case(isn[`INSTRUCTION_OP])
351 
`MEMNDX:
352 
        if (isn[`INSTRUCTION_L2]==2'b10) begin
353 
                if (isn[31])
354 
                        case({isn[31:28],isn[17:16]})
355 
                        `PUSH:  IsPush = TRUE;
356 
            default:    IsPush = FALSE;
357 
                        endcase
358 
                else
359 
                        IsPush = FALSE;
360 
        end
361 
        else if (isn[`INSTRUCTION_L2]==2'b00)
362 
                case({isn[31:28],isn[17:16]})
363 
                `PUSH:  IsPush = TRUE;
364 
    default:    IsPush = FALSE;
365 
    endcase
366 
        else
367 
                IsPush = FALSE;
368 
default:    IsPush = FALSE;
369 
endcase
370 
endfunction
371 
 
372 
function [0:0] IsMem;
373 
input [47:0] isn;
374 
case(isn[`INSTRUCTION_OP])
375 
`MEMNDX:        IsMem = TRUE;
376 
`AMO:           IsMem = TRUE;
377 
`LB:    IsMem = TRUE;
378 
`LBU:   IsMem = TRUE;
379 
`Lx:    IsMem = TRUE;
380 
`LxU:   IsMem = TRUE;
381 
`LWR:   IsMem = TRUE;
382 
`LV,`SV:    IsMem = TRUE;
383 
`INC:           IsMem = TRUE;
384 
`SB:    IsMem = TRUE;
385 
`Sx:    IsMem = TRUE;
386 
`SWC:   IsMem = TRUE;
387 
`CAS:   IsMem = TRUE;
388 
`LVx:           IsMem = TRUE;
389 
`LVxU:  IsMem = TRUE;
390 
default:    IsMem = FALSE;
391 
endcase
392 
endfunction
393 
 
394 
function IsMemNdx;
395 
input [47:0] isn;
396 
case(isn[`INSTRUCTION_OP])
397 
`MEMNDX:        IsMemNdx = TRUE;
398 
default:    IsMemNdx = FALSE;
399 
endcase
400 
endfunction
401 
 
402 
function [2:0] MemSize;
403 
input [47:0] isn;
404 
case(isn[`INSTRUCTION_OP])
405 
`MEMNDX:
406 
        if (isn[`INSTRUCTION_L2]==2'b00) begin
407 
                if (IsLoad(isn))
408 
            case({isn[31:28],isn[22:21]})
409 
            `LVBX,`LVBUX:       MemSize = byt;
410 
            `LBX,`LBUX:   MemSize = byt;
411 
            `LVCX,`LVCUX:                        MemSize = wyde;
412 
            `LCX,`LCUX:   MemSize = wyde;
413 
            `LVHX,`LVHUX:               MemSize = tetra;
414 
            `LHX:   MemSize = tetra;
415 
            `LHUX: MemSize = tetra;
416 
            `LVWX:                       MemSize = octa;
417 
            `LWX:   MemSize = octa;
418 
            `LWRX: MemSize = octa;
419 
            `LVX:   MemSize = octa;
420 
            `LVx:
421 
                case(isn[20:18])
422 
                3'd0,3'd1:      MemSize = byt;
423 
                3'd2,3'd3:      MemSize = wyde;
424 
                3'd4,3'd5:      MemSize = tetra;
425 
                default:        MemSize = octa;
426 
                endcase
427 
            default: MemSize = octa;
428 
                endcase
429 
          else
430 
                        case({isn[31:28],isn[17:16]})
431 
            `SBX:   MemSize = byt;
432 
            `SCX:   MemSize = wyde;
433 
            `SHX:   MemSize = tetra;
434 
            `SWX:   MemSize = octa;
435 
            `SWCX: MemSize = octa;
436 
            `SVX:   MemSize = octa;
437 
            default: MemSize = octa;
438 
                        endcase
439 
  end
440 
        else
441 
                MemSize = octa;
442 
`LB,`LBU:    MemSize = byt;
443 
`Lx,`LxU,`LVx,`LVxU:
444 
        casez(isn[20:18])
445 
        3'b100: MemSize = octa;
446 
        3'b?10: MemSize = tetra;
447 
        3'b??1: MemSize = wyde;
448 
        default:        MemSize = octa;
449 
        endcase
450 
`LWR:  MemSize = octa;
451 
`LV:    MemSize = octa;
452 
`AMO:
453 
        case(isn[23:21])
454 
        3'd0:   MemSize = byt;
455 
        3'd1:   MemSize = wyde;
456 
        3'd2:   MemSize = tetra;
457 
        3'd3:   MemSize = octa;
458 
        default:        MemSize = octa;
459 
        endcase
460 
`SB:    MemSize = byt;
461 
`Sx:
462 
        casez(isn[15:13])
463 
        3'b100: MemSize = octa;
464 
        3'b?10: MemSize = tetra;
465 
        3'b??1: MemSize = wyde;
466 
        default:        MemSize = octa;
467 
        endcase
468 
`SWC:  MemSize = octa;
469 
`SV:    MemSize = octa;
470 
default:    MemSize = octa;
471 
endcase
472 
endfunction
473 
 
474 
function IsCAS;
475 
input [47:0] isn;
476 
case(isn[`INSTRUCTION_OP])
477 
`MEMNDX:
478 
        if (isn[`INSTRUCTION_L2]==2'b00)
479 
                case({isn[31:28],isn[17:16]})
480 
    `CASX:   IsCAS = TRUE;
481 
    default:    IsCAS = FALSE;
482 
    endcase
483 
        else
484 
                IsCAS = FALSE;
485 
`CAS:       IsCAS = TRUE;
486 
default:    IsCAS = FALSE;
487 
endcase
488 
endfunction
489 
 
490 
function IsAMO;
491 
input [47:0] isn;
492 
case(isn[`INSTRUCTION_OP])
493 
`AMO:       IsAMO = TRUE;
494 
default:    IsAMO = FALSE;
495 
endcase
496 
endfunction
497 
 
498 
function IsInc;
499 
input [47:0] isn;
500 
case(isn[`INSTRUCTION_OP])
501 
`MEMNDX:
502 
        if (isn[`INSTRUCTION_L2]==2'b00)
503 
                case({isn[31:28],isn[17:16]})
504 
    `INCX:   IsInc = TRUE;
505 
    default:    IsInc = FALSE;
506 
    endcase
507 
        else
508 
                IsInc = FALSE;
509 
`INC:    IsInc = TRUE;
510 
default:    IsInc = FALSE;
511 
endcase
512 
endfunction
513 
 
514 
function IsFSync;
515 
input [47:0] isn;
516 
IsFSync = (isn[`INSTRUCTION_OP]==`FLOAT && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`FSYNC);
517 
endfunction
518 
 
519 
function IsMemdb;
520 
input [47:0] isn;
521 
IsMemdb = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMDB);
522 
endfunction
523 
 
524 
function IsMemsb;
525 
input [47:0] isn;
526 
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
527 
endfunction
528 
 
529 
function IsSEI;
530 
input [47:0] isn;
531 
IsSEI = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`SEI);
532 
endfunction
533 
 
534 
function IsShift48;
535 
input [47:0] isn;
536 
case(isn[`INSTRUCTION_OP])
537 
`R2:
538 
        if (isn[`INSTRUCTION_L2]==2'b01)
539 
    case(isn[47:42])
540 
    `SHIFTR: IsShift48 = TRUE;
541 
    default: IsShift48 = FALSE;
542 
    endcase
543 
  else
544 
        IsShift48 = FALSE;
545 
default: IsShift48 = FALSE;
546 
endcase
547 
endfunction
548 
 
549 
function IsShift;
550 
input [47:0] isn;
551 
case(isn[`INSTRUCTION_OP])
552 
`R2:
553 
        if (isn[`INSTRUCTION_L2]==2'b00)
554 
    case(isn[31:26])
555 
    `SHIFTR: IsShift = TRUE;
556 
    `SHIFT31: IsShift = TRUE;
557 
    `SHIFT63: IsShift = TRUE;
558 
    default: IsShift = FALSE;
559 
    endcase
560 
  else
561 
        IsShift = FALSE;
562 
default: IsShift = FALSE;
563 
endcase
564 
endfunction
565 
 
566 
function IsCmp;
567 
input [47:0] isn;
568 
case(isn[`INSTRUCTION_OP])
569 
`R2:
570 
        if (isn[`INSTRUCTION_L2]==2'b00)
571 
    case(isn[31:26])
572 
    `CMP: IsCmp = TRUE;
573 
    default: IsCmp = FALSE;
574 
    endcase
575 
  else
576 
        IsCmp = FALSE;
577 
`CMPI:  IsCmp = TRUE;
578 
default: IsCmp = FALSE;
579 
endcase
580 
endfunction
581 
 
582 
function IsLWRX;
583 
input [47:0] isn;
584 
case(isn[`INSTRUCTION_OP])
585 
`MEMNDX:
586 
        if (isn[`INSTRUCTION_L2]==2'b00)
587 
    case({isn[31:28],isn[22:21]})
588 
    `LWRX:   IsLWRX = TRUE;
589 
    default:    IsLWRX = FALSE;
590 
    endcase
591 
        else
592 
                IsLWRX = FALSE;
593 
default:    IsLWRX = FALSE;
594 
endcase
595 
endfunction
596 
 
597 
// Aquire / release bits are only available on indexed SWC / LWR
598 
function IsSWCX;
599 
input [47:0] isn;
600 
case(isn[`INSTRUCTION_OP])
601 
`MEMNDX:
602 
        if (isn[`INSTRUCTION_L2]==2'b00)
603 
                case({isn[31:28],isn[17:16]})
604 
    `SWCX:   IsSWCX = TRUE;
605 
    default:    IsSWCX = FALSE;
606 
    endcase
607 
        else
608 
                IsSWCX = FALSE;
609 
default:    IsSWCX = FALSE;
610 
endcase
611 
endfunction
612 
 
613 
function IsJmp;
614 
input [47:0] isn;
615 
IsJmp = isn[`INSTRUCTION_OP]==`JMP;
616 
endfunction
617 
 
618 
// Really IsPredictableBranch
619 
// Does not include BccR's
620 
function IsBranch;
621 
input [47:0] isn;
622 
casez(isn[`INSTRUCTION_OP])
623 
`Bcc:   IsBranch = TRUE;
624 
`BBc:   IsBranch = TRUE;
625 
`BEQI:  IsBranch = TRUE;
626 
`CHK:   IsBranch = TRUE;
627 
default:    IsBranch = FALSE;
628 
endcase
629 
endfunction
630 
 
631 
function IsJAL;
632 
input [47:0] isn;
633 
IsJAL = isn[`INSTRUCTION_OP]==`JAL;
634 
endfunction
635 
 
636 
function IsRet;
637 
input [47:0] isn;
638 
IsRet = isn[`INSTRUCTION_OP]==`RET;
639 
endfunction
640 
 
641 
function IsIrq;
642 
input [47:0] isn;
643 
IsIrq = isn[`INSTRUCTION_OP]==`BRK && isn[25:21]==5'h0;
644 
endfunction
645 
 
646 
function IsBrk;
647 
input [47:0] isn;
648 
IsBrk = isn[`INSTRUCTION_OP]==`BRK;
649 
endfunction
650 
 
651 
function IsRti;
652 
input [47:0] isn;
653 
IsRti = isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_S2]==`RTI;
654 
endfunction
655 
 
656 
function IsSync;
657 
input [47:0] isn;
658 
IsSync = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`SYNC) || IsRti(isn);
659 
endfunction
660 
 
661 
// Has an extendable 14-bit constant
662 
function HasConst;
663 
input [47:0] isn;
664 
casez(isn[`INSTRUCTION_OP])
665 
`ADDI:  HasConst = TRUE;
666 
`SLTI:  HasConst = TRUE;
667 
`SLTUI: HasConst = TRUE;
668 
`SGTI:  HasConst = TRUE;
669 
`SGTUI: HasConst = TRUE;
670 
`ANDI:  HasConst = TRUE;
671 
`ORI:   HasConst = TRUE;
672 
`XORI:  HasConst = TRUE;
673 
`XNORI: HasConst = TRUE;
674 
`MULUI: HasConst = TRUE;
675 
`MULI:  HasConst = TRUE;
676 
`MULFI: HasConst = TRUE;
677 
`DIVUI: HasConst = TRUE;
678 
`DIVI:  HasConst = TRUE;
679 
`MODI:  HasConst = TRUE;
680 
`LB:    HasConst = TRUE;
681 
`LBU:   HasConst = TRUE;
682 
`Lx:    HasConst = TRUE;
683 
`LxU:   HasConst = TRUE;
684 
`LWR:           HasConst = TRUE;
685 
`LV:    HasConst = TRUE;
686 
`SB:    HasConst = TRUE;
687 
`Sx:    HasConst = TRUE;
688 
`SWC:   HasConst = TRUE;
689 
`INC:           HasConst = TRUE;
690 
`SV:    HasConst = TRUE;
691 
`CAS:   HasConst = TRUE;
692 
`JAL:   HasConst = TRUE;
693 
`CALL:  HasConst = TRUE;
694 
`RET:   HasConst = TRUE;
695 
`LVx:           HasConst = TRUE;
696 
`LVxU:  HasConst = TRUE;
697 
default:    HasConst = FALSE;
698 
endcase
699 
endfunction
700 
 
701 
function IsOddball;
702 
input [47:0] instr;
703 
//if (|iqentry_exc[head])
704 
//    IsOddball = TRUE;
705 
//else
706 
case(instr[`INSTRUCTION_OP])
707 
`BRK:   IsOddball = TRUE;
708 
`IVECTOR:
709 
    case(instr[`INSTRUCTION_S2])
710 
    `VSxx:  IsOddball = TRUE;
711 
    default:    IsOddball = FALSE;
712 
    endcase
713 
`RR:
714 
    case(instr[`INSTRUCTION_S2])
715 
    `VMOV:  IsOddball = TRUE;
716 
    `SEI,`RTI: IsOddball = TRUE;
717 
    default:    IsOddball = FALSE;
718 
    endcase
719 
`MEMNDX:
720 
                case({instr[31:28],instr[17:16]})
721 
    `CACHEX:  IsOddball = TRUE;
722 
    default:    IsOddball = FALSE;
723 
    endcase
724 
`CSRRW,`REX,`CACHE,`FLOAT:  IsOddball = TRUE;
725 
default:    IsOddball = FALSE;
726 
endcase
727 
endfunction
728 
 
729 
function IsRFW;
730 
input [47:0] isn;
731 
casez(isn[`INSTRUCTION_OP])
732 
`IVECTOR:   IsRFW = TRUE;
733 
`FVECTOR:   IsRFW = TRUE;
734 
`R2:
735 
        if (isn[`INSTRUCTION_L2]==2'b00)
736 
    casez(isn[`INSTRUCTION_S2])
737 
    `TLB:               IsRFW = TRUE;
738 
    `R1:
739 
                case(isn[22:18])
740 
                `MEMDB,`MEMSB,`SYNC,`SETWB,5'h14,5'h15: IsRFW = FALSE;
741 
                default:        IsRFW = TRUE;
742 
                endcase
743 
    `ADD:   IsRFW = TRUE;
744 
    `SUB:   IsRFW = TRUE;
745 
    `SLT:   IsRFW = TRUE;
746 
    `SLTU:  IsRFW = TRUE;
747 
    `SLE:   IsRFW = TRUE;
748 
    `SLEU:  IsRFW = TRUE;
749 
    `AND:   IsRFW = TRUE;
750 
    `OR:    IsRFW = TRUE;
751 
    `XOR:   IsRFW = TRUE;
752 
    `NAND:      IsRFW = TRUE;
753 
    `NOR:               IsRFW = TRUE;
754 
    `XNOR:      IsRFW = TRUE;
755 
    `MULU:  IsRFW = TRUE;
756 
    `MULSU: IsRFW = TRUE;
757 
    `MUL:   IsRFW = TRUE;
758 
    `MULUH:  IsRFW = TRUE;
759 
    `MULSUH: IsRFW = TRUE;
760 
    `MULH:   IsRFW = TRUE;
761 
    `MULF:      IsRFW = TRUE;
762 
    `FXMUL:     IsRFW = TRUE;
763 
    `DIVU:  IsRFW = TRUE;
764 
    `DIVSU: IsRFW = TRUE;
765 
    `DIV:IsRFW = TRUE;
766 
    `MODU:  IsRFW = TRUE;
767 
    `MODSU: IsRFW = TRUE;
768 
    `MOD:IsRFW = TRUE;
769 
    `MOV:       IsRFW = TRUE;
770 
    `VMOV:      IsRFW = TRUE;
771 
    `SHIFTR,`SHIFT31,`SHIFT63:
772 
                IsRFW = TRUE;
773 
    `MIN,`MAX:    IsRFW = TRUE;
774 
    `SEI:       IsRFW = TRUE;
775 
    default:    IsRFW = FALSE;
776 
    endcase
777 
        else if (isn[`INSTRUCTION_L2]==2'b01)
778 
                case(isn[47:42])
779 
                `CMOVEZ:        IsRFW = TRUE;
780 
                `CMOVNZ:        IsRFW = TRUE;
781 
                default:        IsRFW = FALSE;
782 
                endcase
783 
        else if (isn[7]==1'b1)
784 
    casez(isn[`INSTRUCTION_S2])
785 
    `ADD:   IsRFW = TRUE;
786 
    `SUB:   IsRFW = TRUE;
787 
    `AND:   IsRFW = TRUE;
788 
    `OR:    IsRFW = TRUE;
789 
    `XOR:   IsRFW = TRUE;
790 
    `MOV:       IsRFW = TRUE;
791 
    `SHIFTR,`SHIFT31,`SHIFT63:
792 
                IsRFW = TRUE;
793 
    default:    IsRFW = FALSE;
794 
    endcase
795 
        else
796 
                IsRFW = FALSE;
797 
`MEMNDX:
798 
        if (isn[`INSTRUCTION_L2]==2'b10) begin
799 
                if (IsLoad(isn))
800 
                        IsRFW = TRUE;
801 
                else
802 
                        case({isn[31:28],isn[17:16]})
803 
                        `PUSH:  IsRFW = TRUE;
804 
            `CASX:  IsRFW = TRUE;
805 
            default:    IsRFW = FALSE;
806 
            endcase
807 
        end
808 
        else if (isn[`INSTRUCTION_L2]==2'b00) begin
809 
                if (IsLoad(isn))
810 
            case({isn[31:28],isn[22:21]})
811 
            `LBX:   IsRFW = TRUE;
812 
            `LBUX:  IsRFW = TRUE;
813 
            `LCX:   IsRFW = TRUE;
814 
            `LCUX:  IsRFW = TRUE;
815 
            `LHX:   IsRFW = TRUE;
816 
            `LHUX:  IsRFW = TRUE;
817 
            `LWX:   IsRFW = TRUE;
818 
            `LVBX:  IsRFW = TRUE;
819 
            `LVBUX: IsRFW = TRUE;
820 
            `LVCX:  IsRFW = TRUE;
821 
            `LVCUX: IsRFW = TRUE;
822 
            `LVHX:  IsRFW = TRUE;
823 
            `LVHUX: IsRFW = TRUE;
824 
            `LVWX:  IsRFW = TRUE;
825 
            `LWX:   IsRFW = TRUE;
826 
            `LWRX:  IsRFW = TRUE;
827 
            `LVX:   IsRFW = TRUE;
828 
            default:    IsRFW = FALSE;
829 
                endcase
830 
          else
831 
                        case({isn[31:28],isn[17:16]})
832 
                        `PUSH:  IsRFW = TRUE;
833 
            `CASX:  IsRFW = TRUE;
834 
            default:    IsRFW = FALSE;
835 
            endcase
836 
  end
837 
        else
838 
                IsRFW = FALSE;
839 
`BBc:   IsRFW = FALSE;
840 
`BITFIELD:  IsRFW = TRUE;
841 
`ADDI:      IsRFW = TRUE;
842 
`SLTI:      IsRFW = TRUE;
843 
`SLTUI:     IsRFW = TRUE;
844 
`SGTI:      IsRFW = TRUE;
845 
`SGTUI:     IsRFW = TRUE;
846 
`ANDI:      IsRFW = TRUE;
847 
`ORI:       IsRFW = TRUE;
848 
`XORI:      IsRFW = TRUE;
849 
`XNORI:     IsRFW = TRUE;
850 
`MULUI:     IsRFW = TRUE;
851 
`MULI:      IsRFW = TRUE;
852 
`MULFI:                 IsRFW = TRUE;
853 
`DIVUI:     IsRFW = TRUE;
854 
`DIVI:      IsRFW = TRUE;
855 
`MODI:      IsRFW = TRUE;
856 
`JAL:       IsRFW = TRUE;
857 
`CALL:      IsRFW = TRUE;
858 
`RET:       IsRFW = TRUE;
859 
`LB:        IsRFW = TRUE;
860 
`LBU:       IsRFW = TRUE;
861 
`Lx:        IsRFW = TRUE;
862 
`LxU:       IsRFW = TRUE;
863 
`LWR:       IsRFW = TRUE;
864 
`LV:        IsRFW = TRUE;
865 
`LVx:                           IsRFW = TRUE;
866 
`LVxU:                  IsRFW = TRUE;
867 
`CAS:       IsRFW = TRUE;
868 
`AMO:                           IsRFW = TRUE;
869 
`CSRRW:                 IsRFW = TRUE;
870 
`AUIPC:                 IsRFW = TRUE;
871 
`LUI:                           IsRFW = TRUE;
872 
default:    IsRFW = FALSE;
873 
endcase
874 
endfunction
875 
 
876 
// Determines which lanes of the target register get updated.
877 
function [7:0] fnWe;
878 
input [47:0] isn;
879 
casez(isn[`INSTRUCTION_OP])
880 
`R2:
881 
        case(isn[`INSTRUCTION_S2])
882 
        `CMP:   fnWe = 8'h00;                   // CMP sets predicate registers so doesn't update general register file.
883 
        default: fnWe = 8'hFF;
884 
        endcase
885 
`CMPI:  fnWe = 8'h00;
886 
default: fnWe = 8'hFF;
887 
endcase
888 
/*
889 
casez(isn[`INSTRUCTION_OP])
890 
`R2:
891 
        case(isn[`INSTRUCTION_S2])
892 
        `R1:
893 
                case(isn[22:18])
894 
                `ABS,`CNTLZ,`CNTLO,`CNTPOP:
895 
                        case(isn[25:23])
896 
                        3'b000: fnWe = 8'h01;
897 
                        3'b001: fnWe = 8'h03;
898 
                        3'b010: fnWe = 8'h0F;
899 
                        3'b011: fnWe = 8'hFF;
900 
                        default:        fnWe = 8'hFF;
901 
                        endcase
902 
                default: fnWe = 8'hFF;
903 
                endcase
904 
        `SHIFT31:       fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
905 
        `SHIFT63:       fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
906 
        `SLT,`SLTU,`SLE,`SLEU,
907 
        `ADD,`SUB,
908 
        `AND,`OR,`XOR,
909 
        `NAND,`NOR,`XNOR,
910 
        `DIV,`DIVU,`DIVSU,
911 
        `MOD,`MODU,`MODSU,
912 
        `MUL,`MULU,`MULSU,
913 
        `MULH,`MULUH,`MULSUH,
914 
        `FXMUL:
915 
                case(isn[25:23])
916 
                3'b000: fnWe = 8'h01;
917 
                3'b001: fnWe = 8'h03;
918 
                3'b010: fnWe = 8'h0F;
919 
                3'b011: fnWe = 8'hFF;
920 
                default:        fnWe = 8'hFF;
921 
                endcase
922 
        default: fnWe = 8'hFF;
923 
        endcase
924 
default:        fnWe = 8'hFF;
925 
endcase
926 
*/
927 
endfunction
928 
 
929 
// Detect if a source is automatically valid
930 
function Source1Valid;
931 
input [47:0] isn;
932 
casez(isn[`INSTRUCTION_OP])
933 
`BRK:   Source1Valid = TRUE;
934 
`Bcc:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
935 
`BBc:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
936 
`BEQI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
937 
`CHK:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
938 
`R2:    case(isn[`INSTRUCTION_S2])
939 
        `SHIFT31:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
940 
        `SHIFT63:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
941 
        `SHIFTR:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
942 
        default:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
943 
        endcase
944 
`MEMNDX:        Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
945 
`ADDI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
946 
`SLTI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
947 
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
948 
`SGTI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
949 
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
950 
`ANDI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
951 
`ORI:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
952 
`XORI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
953 
`XNORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
954 
`MULUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
955 
`AMO:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
956 
`LB:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
957 
`LBU:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
958 
`Lx:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
959 
`LxU:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
960 
`LWR:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
961 
`LV:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
962 
`LVx:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
963 
`SB:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
964 
`Sx:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
965 
`SWC:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
966 
`SV:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
967 
`INC:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
968 
`CAS:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
969 
`JAL:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
970 
`RET:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
971 
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
972 
`BITFIELD:      case(isn[31:28])
973 
                        `BFINSI:        Source1Valid = TRUE;
974 
                        default:        Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
975 
                        endcase
976 
`IVECTOR:
977 
                        Source1Valid = FALSE;
978 
default:    Source1Valid = TRUE;
979 
endcase
980 
endfunction
981 
 
982 
function Source2Valid;
983 
input [47:0] isn;
984 
casez(isn[`INSTRUCTION_OP])
985 
`BRK:   Source2Valid = TRUE;
986 
`Bcc:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
987 
`BBc:   Source2Valid = TRUE;
988 
`BEQI:  Source2Valid = TRUE;
989 
`CHK:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
990 
`R2:    case(isn[`INSTRUCTION_S2])
991 
        `R1:       Source2Valid = TRUE;
992 
        `SHIFTR:   Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
993 
        `SHIFT31:  Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
994 
        `SHIFT63:  Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
995 
        default:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
996 
        endcase
997 
`MEMNDX:
998 
                                if (IsLoad(isn))
999 
                                        case({isn[31:28],isn[22:21]})
1000 
                `LVX: Source2Valid = FALSE;
1001 
                default:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1002 
                endcase
1003 
        else
1004 
                                        case({isn[31:28],isn[17:16]})
1005 
                `SVX: Source2Valid = FALSE;
1006 
                default:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1007 
                endcase
1008 
`ADDI:  Source2Valid = TRUE;
1009 
`SLTI:  Source2Valid = TRUE;
1010 
`SLTUI: Source2Valid = TRUE;
1011 
`SGTI:  Source2Valid = TRUE;
1012 
`SGTUI: Source2Valid = TRUE;
1013 
`ANDI:  Source2Valid = TRUE;
1014 
`ORI:   Source2Valid = TRUE;
1015 
`XORI:  Source2Valid = TRUE;
1016 
`XNORI: Source2Valid = TRUE;
1017 
`MULUI: Source2Valid = TRUE;
1018 
`LB:    Source2Valid = TRUE;
1019 
`LBU:   Source2Valid = TRUE;
1020 
`Lx:    Source2Valid = TRUE;
1021 
`LxU:   Source2Valid = TRUE;
1022 
`LWR:   Source2Valid = TRUE;
1023 
`LVx:   Source2Valid = TRUE;
1024 
`INC:           Source2Valid = TRUE;
1025 
`SB:    Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1026 
`Sx:    Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1027 
`SWC:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1028 
`CAS:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1029 
`JAL:   Source2Valid = TRUE;
1030 
`RET:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1031 
`IVECTOR:
1032 
                    case(isn[`INSTRUCTION_S2])
1033 
            `VABS:  Source2Valid = TRUE;
1034 
            `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
1035 
                Source2Valid = FALSE;
1036 
            `VADDS,`VSUBS,`VANDS,`VORS,`VXORS:
1037 
                Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1038 
            `VBITS2V:   Source2Valid = TRUE;
1039 
            `V2BITS:    Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
1040 
            `VSHL,`VSHR,`VASR:  Source2Valid = isn[22:21]==2'd2;
1041 
            default:    Source2Valid = FALSE;
1042 
            endcase
1043 
`LV:        Source2Valid = TRUE;
1044 
`SV:        Source2Valid = FALSE;
1045 
`AMO:           Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
1046 
default:    Source2Valid = TRUE;
1047 
endcase
1048 
endfunction
1049 
 
1050 
function Source3Valid;
1051 
input [47:0] isn;
1052 
case(isn[`INSTRUCTION_OP])
1053 
`IVECTOR:
1054 
    case(isn[`INSTRUCTION_S2])
1055 
    `VEX:       Source3Valid = TRUE;
1056 
    default:    Source3Valid = TRUE;
1057 
    endcase
1058 
`CHK:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1059 
`R2:
1060 
        if (isn[`INSTRUCTION_L2]==2'b01)
1061 
                case(isn[47:42])
1062 
    `CMOVEZ,`CMOVNZ:  Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1063 
                default:        Source3Valid = TRUE;
1064 
                endcase
1065 
        else
1066 
    case(isn[`INSTRUCTION_S2])
1067 
    `MAJ:               Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1068 
    default:    Source3Valid = TRUE;
1069 
    endcase
1070 
`MEMNDX:
1071 
        if (isn[`INSTRUCTION_L2]==2'b00)
1072 
                case({isn[31:28],isn[17:16]})
1073 
    `SBX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1074 
    `SCX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1075 
    `SHX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1076 
    `SWX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1077 
    `SWCX:  Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1078 
    `CASX:  Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
1079 
    default:    Source3Valid = TRUE;
1080 
    endcase
1081 
  else
1082 
        Source3Valid = TRUE;
1083 
default:    Source3Valid = TRUE;
1084 
endcase
1085 
endfunction
1086 
 
1087 
wire isRet = IsRet(instr);
1088 
wire isJal = IsJAL(instr);
1089 
wire isBrk = IsBrk(instr);
1090 
wire isRti = IsRti(instr);
1091 
 
1092 
`ifdef REGISTER_DECODE
1093 
always @(posedge clk)
1094 
`else
1095 
always @*
1096 
`endif
1097 
begin
1098 
        bus <= 144'h0;
1099 
        bus[`IB_CMP] <= IsCmp(instr);
1100 
        if (IsStore(instr))
1101 
                bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:23],instr[17:13]} :
1102 
                                                                                                                                                                {{50{instr[31]}},instr[31:23],instr[17:13]};
1103 
        else
1104 
                bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :
1105 
                                                                                                                                                                {{50{instr[31]}},instr[31:18]};
1106 
`ifdef SUPPORT_DCI
1107 
        if (instr[`INSTRUCTION_OP]==`CMPRSSD)
1108 
                bus[`IB_LN] <= 3'd2 | pred_on;
1109 
        else
1110 
`endif
1111 
                case(instr[7:6])
1112 
                2'b00:  bus[`IB_LN] <= 3'd4 | pred_on;
1113 
                2'b01:  bus[`IB_LN] <= 3'd6 | pred_on;
1114 
                default: bus[`IB_LN] <= 3'd2 | pred_on;
1115 
                endcase
1116 
//      bus[`IB_RT]              <= fnRt(instr,ven,vl,thrd) | {thrd,7'b0};
1117 
//      bus[`IB_RC]              <= fnRc(instr,ven,thrd) | {thrd,7'b0};
1118 
//      bus[`IB_RA]              <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
1119 
        bus[`IB_IMM]     <= HasConst(instr);
1120 
//      bus[`IB_A3V]   <= Source3Valid(instr);
1121 
//      bus[`IB_A2V]   <= Source2Valid(instr);
1122 
//      bus[`IB_A1V]   <= Source1Valid(instr);
1123 
        bus[`IB_TLB]     <= IsTLB(instr);
1124 
        bus[`IB_SZ]    <= instr[`INSTRUCTION_OP]==`R2 ? instr[25:23] : 3'd3;    // 3'd3=word size
1125 
        bus[`IB_IRQ]     <= IsIrq(instr);
1126 
        bus[`IB_BRK]     <= isBrk;
1127 
        bus[`IB_RTI]     <= isRti;
1128 
        bus[`IB_RET]     <= isRet;
1129 
        bus[`IB_JAL]     <= isJal;
1130 
        // IB_BT is now used to indicate when to update the branch target buffer.
1131 
        // This occurs when one of the instructions with an unknown or calculated
1132 
        // target is present.
1133 
        bus[`IB_BT]              <= isJal | isRet | isBrk | isRti;
1134 
        bus[`IB_ALU]   <= IsALU;
1135 
        bus[`IB_ALU0]  <= IsAlu0Only(instr);
1136 
        bus[`IB_FPU]   <= IsFPU(instr);
1137 
        bus[`IB_FC]              <= IsFlowCtrl;
1138 
        bus[`IB_CANEX] <= fnCanException(instr);
1139 
        bus[`IB_LOADV] <= IsVolatileLoad(instr);
1140 
        bus[`IB_LOAD]    <= IsLoad(instr);
1141 
        bus[`IB_PRELOAD] <=   IsLoad(instr) && Rt==5'd0;
1142 
        bus[`IB_STORE]  <= IsStore(instr);
1143 
        bus[`IB_PUSH]   <= IsPush(instr);
1144 
        bus[`IB_ODDBALL] <= IsOddball(instr);
1145 
        bus[`IB_MEMSZ]  <= MemSize(instr);
1146 
        bus[`IB_MEM]            <= IsMem(instr);
1147 
        bus[`IB_MEMNDX] <= IsMemNdx(instr);
1148 
        bus[`IB_RMW]            <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
1149 
        bus[`IB_MEMDB]  <= IsMemdb(instr);
1150 
        bus[`IB_MEMSB]  <= IsMemsb(instr);
1151 
        bus[`IB_SHFT]   <= IsShift48(instr);//|IsShift(instr);
1152 
        bus[`IB_SEI]            <= IsSEI(instr);
1153 
        bus[`IB_AQ]                     <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[25];
1154 
        bus[`IB_RL]                     <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[24];
1155 
        bus[`IB_JMP]            <= IsJmp(instr);
1156 
        bus[`IB_BR]                     <= IsBranch(instr);
1157 
        bus[`IB_SYNC]           <= IsSync(instr)||IsBrk(instr)||IsRti(instr);
1158 
        bus[`IB_FSYNC]  <= IsFSync(instr);
1159 
        bus[`IB_RFW]            <= (Rt==5'd0) ? 1'b0 : IsRFW(instr);// && !IsCmp(instr);
1160 
        bus[`IB_PRFW]   <= IsCmp(instr);
1161 
        bus[`IB_WE]                     <= fnWe(instr);
1162 
        id_o <= id_i;
1163 
        idv_o <= idv_i;
1164 
end
1165 
 
1166 
endmodule
1167 
 
1168 
module mIsALU(instr, IsALU);
1169 
input [47:0] instr;
1170 
output reg IsALU;
1171 
parameter TRUE = 1'b1;
1172 
parameter FALSE = 1'b0;
1173 
 
1174 
always @*
1175 
casez(instr[`INSTRUCTION_OP])
1176 
`R2:
1177 
  if (instr[`INSTRUCTION_L2]==2'b00)
1178 
                case(instr[`INSTRUCTION_S2])
1179 
                `VMOV:          IsALU = TRUE;
1180 
    `RTI:       IsALU = FALSE;
1181 
    default:    IsALU = TRUE;
1182 
    endcase
1183 
    else
1184 
        IsALU = TRUE;
1185 
`BRK:   IsALU = FALSE;
1186 
`Bcc:   IsALU = FALSE;
1187 
`BBc:   IsALU = FALSE;
1188 
`BEQI:  IsALU = FALSE;
1189 
`CHK:   IsALU = FALSE;
1190 
`JAL:   IsALU = FALSE;
1191 
`JMP:   IsALU = FALSE;
1192 
`CALL:  IsALU = FALSE;
1193 
`RET:   IsALU = FALSE;
1194 
`FVECTOR:
1195 
        case(instr[`INSTRUCTION_S2])
1196 
  `VSHL,`VSHR,`VASR:  IsALU = TRUE;
1197 
  default:    IsALU = FALSE;  // Integer
1198 
  endcase
1199 
`IVECTOR:
1200 
        case(instr[`INSTRUCTION_S2])
1201 
  `VSHL,`VSHR,`VASR:  IsALU = TRUE;
1202 
  default:    IsALU = TRUE;  // Integer
1203 
  endcase
1204 
`FLOAT:         IsALU = FALSE;
1205 
default:    IsALU = TRUE;
1206 
endcase
1207 
 
1208 
endmodule

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