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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [lib/] [ffo.v] - Blame information for rev 60

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1 60 robfinch 
 
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// Find first one
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module ffo6(i, o);
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input [5:0] i;
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output reg [2:0] o;
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always @*
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casex(i)
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6'b1xxxxx:  o <= 3'd5;
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6'b01xxxx:  o <= 3'd4;
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6'b001xxx:  o <= 3'd3;
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6'b0001xx:  o <= 3'd2;
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6'b00001x:  o <= 3'd1;
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6'b000001:  o <= 3'd0;
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default:    o <= 3'd7;
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endcase
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endmodule
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module ffo12(i, o);
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input [11:0] i;
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output reg [3:0] o;
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wire [2:0] o1,o2;
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ffo6 u1 (i[11:6],o1);
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ffo6 u2 (i[5:0],o2);
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always @*
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if (o1==3'd7 && o2==3'd7)
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    o <= 4'd15;
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else if (o1==3'd7)
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    o <= o2;
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else
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    o <= 3'd6 + o1;
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endmodule
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module ffo24(i, o);
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input [23:0] i;
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output reg [4:0] o;
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wire [3:0] o1,o2;
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ffo12 u1 (i[23:12],o1);
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ffo12 u2 (i[11:0],o2);
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always @*
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if (o1==4'd15 && o2==4'd15)
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    o <= 5'd31;
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else if (o1==4'd15)
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    o <= o2;
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else
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    o <= 4'd12 + o1;
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endmodule
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module ffo48(i, o);
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input [47:0] i;
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output reg [5:0] o;
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wire [4:0] o1,o2;
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ffo24 u1 (i[47:24],o1);
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ffo24 u2 (i[23:0],o2);
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always @*
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if (o1==5'd31 && o2==5'd31)
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    o <= 6'd63;
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else if (o1==5'd31)
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    o <= o2;
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else
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    o <= 5'd24 + o1;
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endmodule
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module ffo96(i, o);
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input [95:0] i;
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output reg [6:0] o;
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wire [5:0] o1,o2;
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ffo48 u1 (i[95:48],o1);
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ffo48 u2 (i[47:0],o2);
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always @*
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if (o1==6'd63 && o2==6'd63)
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    o <= 7'd127;
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else if (o1==6'd63)
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    o <= o2;
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else
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    o <= 6'd48 + o1;
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endmodule
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