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// ============================================================================
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT64_fetchbuf.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`include "FT64_config.vh"
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`include "FT64_defines.vh"
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// FETCH
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//
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// fetch exactly two instructions from memory into the fetch buffer
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// unless either one of the buffers is still full, in which case we
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// do nothing (kinda like alpha approach)
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// Like to turn this into an independent module at some point.
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//
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module FT64_fetchbuf(rst, clk4x, clk, fcu_clk,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cmpgrp,
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freezePC, thread_en,
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regLR,
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insn0, insn1, phit,
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threadx,
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branchmiss, misspc, branchmiss_thrd, predict_taken0, predict_taken1,
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predict_takenA, predict_takenB, predict_takenC, predict_takenD,
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queued1, queued2, queuedNop,
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pc0, pc1, fetchbuf, fetchbufA_v, fetchbufB_v, fetchbufC_v, fetchbufD_v,
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fetchbufA_instr, fetchbufA_pc,
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fetchbufB_instr, fetchbufB_pc,
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fetchbufC_instr, fetchbufC_pc,
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fetchbufD_instr, fetchbufD_pc,
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fetchbuf0_instr, fetchbuf1_instr, fetchbuf0_insln, fetchbuf1_insln,
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fetchbuf0_thrd, fetchbuf1_thrd,
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fetchbuf0_pc, fetchbuf1_pc,
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fetchbuf0_v, fetchbuf1_v,
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codebuf0, codebuf1,
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btgtA, btgtB, btgtC, btgtD,
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nop_fetchbuf,
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take_branch0, take_branch1,
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stompedRets,
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panic
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);
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parameter AMSB = `AMSB;
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parameter RSTPC = 64'hFFFC0100;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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input rst;
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input clk4x;
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input clk;
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input fcu_clk;
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input cs_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input we_i;
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input [15:0] adr_i;
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input [47:0] dat_i;
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input [2:0] cmpgrp;
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input freezePC;
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input thread_en;
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input [4:0] regLR;
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input [47:0] insn0;
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input [47:0] insn1;
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input phit;
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output threadx;
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input branchmiss;
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input [AMSB:0] misspc;
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input branchmiss_thrd;
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output predict_taken0;
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output predict_taken1;
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input predict_takenA;
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input predict_takenB;
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input predict_takenC;
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input predict_takenD;
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input queued1;
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input queued2;
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input queuedNop;
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output reg [AMSB:0] pc0;
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output reg [AMSB:0] pc1;
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output reg fetchbuf;
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output reg fetchbufA_v;
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output reg fetchbufB_v;
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output reg fetchbufC_v;
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output reg fetchbufD_v;
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output fetchbuf0_thrd;
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output fetchbuf1_thrd;
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output reg [47:0] fetchbufA_instr;
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output reg [47:0] fetchbufB_instr;
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output reg [47:0] fetchbufC_instr;
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output reg [47:0] fetchbufD_instr;
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output reg [AMSB:0] fetchbufA_pc;
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output reg [AMSB:0] fetchbufB_pc;
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output reg [AMSB:0] fetchbufC_pc;
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output reg [AMSB:0] fetchbufD_pc;
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output [47:0] fetchbuf0_instr;
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output [47:0] fetchbuf1_instr;
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output [AMSB:0] fetchbuf0_pc;
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output [AMSB:0] fetchbuf1_pc;
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output [2:0] fetchbuf0_insln;
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output [2:0] fetchbuf1_insln;
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output fetchbuf0_v;
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output fetchbuf1_v;
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input [47:0] codebuf0;
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input [47:0] codebuf1;
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input [AMSB:0] btgtA;
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input [AMSB:0] btgtB;
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input [AMSB:0] btgtC;
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input [AMSB:0] btgtD;
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input [3:0] nop_fetchbuf;
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output take_branch0;
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output take_branch1;
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input [3:0] stompedRets;
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output reg [3:0] panic;
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integer n;
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//`include "FT64_decode.vh"
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function IsBranch;
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input [47:0] isn;
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casex(isn[`INSTRUCTION_OP])
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`Bcc: IsBranch = TRUE;
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`BBc: IsBranch = TRUE;
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`BEQI: IsBranch = TRUE;
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`BCHK: IsBranch = TRUE;
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default: IsBranch = FALSE;
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endcase
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endfunction
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function IsJAL;
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input [47:0] isn;
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IsJAL = isn[`INSTRUCTION_OP]==`JAL;
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endfunction
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function IsJmp;
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input [47:0] isn;
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IsJmp = isn[`INSTRUCTION_OP]==`JMP;
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endfunction
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function IsCall;
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input [47:0] isn;
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IsCall = isn[`INSTRUCTION_OP]==`CALL;
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endfunction
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function IsRet;
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input [47:0] isn;
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IsRet = isn[`INSTRUCTION_OP]==`RET;
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endfunction
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function IsBrk;
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input [47:0] isn;
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IsBrk = isn[`INSTRUCTION_OP]==`BRK;
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endfunction
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function IsRTI;
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input [47:0] isn;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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endfunction
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function [2:0] fnInsLength;
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input [47:0] ins;
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`ifdef SUPPORT_DCI
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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fnInsLength = 3'd2;
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else
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`endif
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case(ins[7:6])
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2'd0: fnInsLength = 3'd4;
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2'd1: fnInsLength = 3'd6;
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default: fnInsLength = 3'd2;
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endcase
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endfunction
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wire [2:0] fetchbufA_inslen;
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wire [2:0] fetchbufB_inslen;
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wire [2:0] fetchbufC_inslen;
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wire [2:0] fetchbufD_inslen;
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FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen);
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FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen);
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FT64_InsLength uilC (fetchbufC_instr, fetchbufC_inslen);
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FT64_InsLength uilD (fetchbufD_instr, fetchbufD_inslen);
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wire [47:0] xinsn0;
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wire [47:0] xinsn1;
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FT64_iexpander ux1
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(
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.cinstr(insn0[15:0]),
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.expand(xinsn0)
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);
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FT64_iexpander ux2
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(
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.cinstr(insn1[15:0]),
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.expand(xinsn1)
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);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Table of decompressed instructions.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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assign ack_o = cs_i & cyc_i & stb_i;
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`ifdef SUPPORT_DCI
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reg [47:0] DecompressTable [0:2047];
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always @(posedge clk)
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if (cs_i & cyc_i & stb_i & we_i)
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DecompressTable[adr_i[12:3]] <= dat_i[47:0];
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wire [47:0] expand0 = DecompressTable[{cmpgrp,insn0[15:8]}];
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wire [47:0] expand1 = DecompressTable[{cmpgrp,insn1[15:8]}];
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`endif
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg thread;
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reg stompedRet;
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reg ret0Counted, ret1Counted;
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wire [AMSB:0] retpc0, retpc1;
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reg did_branchback0;
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reg did_branchback1;
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assign predict_taken0 = (fetchbuf==1'b0) ? predict_takenA : predict_takenC;
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assign predict_taken1 = (fetchbuf==1'b0) ? predict_takenB : predict_takenD;
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reg [AMSB:0] branch_pcA;
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reg [AMSB:0] branch_pcB;
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reg [AMSB:0] branch_pcC;
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reg [AMSB:0] branch_pcD;
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always @*
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case(fetchbufA_instr[`INSTRUCTION_OP])
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`RET: branch_pcA = retpc0;
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`JMP,`CALL: branch_pcA = fetchbufA_instr[6] ? {fetchbufA_instr[39:8],1'b0} : {fetchbufA_pc[31:25],fetchbufA_instr[31:8],1'b0};
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`R2: branch_pcA = btgtA; // RTI
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`BRK,`JAL: branch_pcA = btgtA;
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default:
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begin
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branch_pcA[31:8] = fetchbufA_pc[31:8] +
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(fetchbufA_instr[7:6]==2'b01 ? {{4{fetchbufA_instr[47]}},fetchbufA_instr[47:28]} : {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:28]});
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branch_pcA[7:0] = {fetchbufA_instr[27:23],fetchbufA_instr[17:16],1'b0};
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branch_pcA[63:32] = fetchbufA_pc[63:32];
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end
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endcase
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always @*
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case(fetchbufB_instr[`INSTRUCTION_OP])
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`RET: branch_pcB = retpc1;
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`JMP,`CALL: branch_pcB = fetchbufB_instr[6] ? {fetchbufB_instr[39:8],1'b0} : {fetchbufB_pc[31:25],fetchbufB_instr[31:8],1'b0};
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`R2: branch_pcB = btgtB; // RTI
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`BRK,`JAL: branch_pcB = btgtB;
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default:
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begin
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branch_pcB[31:8] = fetchbufB_pc[31:8] +
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(fetchbufB_instr[7:6]==2'b01 ? {{4{fetchbufB_instr[47]}},fetchbufB_instr[47:28]} : {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:28]});
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branch_pcB[7:0] = {fetchbufB_instr[27:23],fetchbufB_instr[17:16],1'b0};
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branch_pcB[63:32] = fetchbufB_pc[63:32];
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end
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endcase
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always @*
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case(fetchbufC_instr[`INSTRUCTION_OP])
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`RET: branch_pcC = retpc0;
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`JMP,`CALL: branch_pcC = fetchbufC_instr[6] ? {fetchbufC_instr[39:8],1'b0} : {fetchbufC_pc[31:25],fetchbufC_instr[31:8],1'b0};
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`R2: branch_pcC = btgtC; // RTI
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`BRK,`JAL: branch_pcC = btgtC;
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default:
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begin
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branch_pcC[31:8] = fetchbufC_pc[31:8] +
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(fetchbufC_instr[7:6]==2'b01 ? {{4{fetchbufC_instr[47]}},fetchbufC_instr[47:28]} : {{20{fetchbufC_instr[31]}},fetchbufC_instr[31:28]});
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branch_pcC[7:0] = {fetchbufC_instr[27:23],fetchbufC_instr[17:16],1'b0};
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branch_pcC[63:32] = fetchbufC_pc[63:32];
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end
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endcase
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always @*
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case(fetchbufD_instr[`INSTRUCTION_OP])
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`RET: branch_pcD = retpc1;
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`JMP,`CALL: branch_pcD = fetchbufD_instr[6] ? {fetchbufD_instr[39:8],1'b0} : {fetchbufD_pc[31:25],fetchbufD_instr[31:8],1'b0};
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`R2: branch_pcD = btgtD; // RTI
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`BRK,`JAL: branch_pcD = btgtD;
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default:
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begin
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branch_pcD[31:8] = fetchbufD_pc[31:8] +
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(fetchbufD_instr[7:6]==2'b01 ? {{4{fetchbufD_instr[47]}},fetchbufD_instr[47:28]} : {{20{fetchbufD_instr[31]}},fetchbufD_instr[31:28]});
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branch_pcD[7:0] = {fetchbufD_instr[27:23],fetchbufD_instr[17:16],1'b0};
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branch_pcD[63:32] = fetchbufD_pc[63:32];
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end
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endcase
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wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE}) ||
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((IsRet(fetchbufA_instr)||IsJmp(fetchbufA_instr)||IsCall(fetchbufA_instr)||
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IsRTI(fetchbufA_instr)|| IsBrk(fetchbufA_instr) || IsJAL(fetchbufA_instr)) &&
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fetchbufA_v);
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wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE}) ||
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|
|
((IsRet(fetchbufB_instr)|IsJmp(fetchbufB_instr)|IsCall(fetchbufB_instr) ||
|
314 |
|
|
IsRTI(fetchbufB_instr)|| IsBrk(fetchbufB_instr) || IsJAL(fetchbufB_instr)) &&
|
315 |
|
|
fetchbufB_v);
|
316 |
|
|
wire take_branchC = ({fetchbufC_v, IsBranch(fetchbufC_instr), predict_takenC} == {`VAL, `TRUE, `TRUE}) ||
|
317 |
|
|
((IsRet(fetchbufC_instr)|IsJmp(fetchbufC_instr)|IsCall(fetchbufC_instr) ||
|
318 |
|
|
IsRTI(fetchbufC_instr)|| IsBrk(fetchbufC_instr) || IsJAL(fetchbufC_instr)) &&
|
319 |
|
|
fetchbufC_v);
|
320 |
|
|
wire take_branchD = ({fetchbufD_v, IsBranch(fetchbufD_instr), predict_takenD} == {`VAL, `TRUE, `TRUE}) ||
|
321 |
|
|
((IsRet(fetchbufD_instr)|IsJmp(fetchbufD_instr)|IsCall(fetchbufD_instr) ||
|
322 |
|
|
IsRTI(fetchbufD_instr)|| IsBrk(fetchbufD_instr) || IsJAL(fetchbufD_instr)) &&
|
323 |
|
|
fetchbufD_v);
|
324 |
|
|
|
325 |
|
|
assign take_branch0 = fetchbuf==1'b0 ? take_branchA : take_branchC;
|
326 |
|
|
assign take_branch1 = fetchbuf==1'b0 ? take_branchB : take_branchD;
|
327 |
|
|
wire take_branch = take_branch0 || take_branch1;
|
328 |
|
|
/*
|
329 |
|
|
always @*
|
330 |
|
|
begin
|
331 |
|
|
pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;
|
332 |
|
|
pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
|
333 |
|
|
end
|
334 |
|
|
*/
|
335 |
|
|
assign threadx = fetchbuf;
|
336 |
|
|
|
337 |
|
|
`ifdef FCU_ENH
|
338 |
|
|
FT64_RSB #(AMSB) ursb1
|
339 |
|
|
(
|
340 |
|
|
.rst(rst),
|
341 |
|
|
.clk(fcu_clk),
|
342 |
|
|
.regLR(regLR),
|
343 |
|
|
.queued1(queued1),
|
344 |
|
|
.queued2(queued2),
|
345 |
|
|
.fetchbuf0_v(fetchbuf0_v),
|
346 |
|
|
.fetchbuf0_pc(fetchbuf0_pc),
|
347 |
|
|
.fetchbuf0_instr(fetchbuf0_instr),
|
348 |
|
|
.fetchbuf1_v(fetchbuf1_v),
|
349 |
|
|
.fetchbuf1_pc(fetchbuf1_pc),
|
350 |
|
|
.fetchbuf1_instr(fetchbuf1_instr),
|
351 |
|
|
.stompedRets(stompedRets),
|
352 |
|
|
.stompedRet(stompedRet),
|
353 |
|
|
.pc(retpc0)
|
354 |
|
|
);
|
355 |
|
|
|
356 |
|
|
FT64_RSB #(AMSB) ursb2
|
357 |
|
|
(
|
358 |
|
|
.rst(rst),
|
359 |
|
|
.clk(fcu_clk),
|
360 |
|
|
.regLR(regLR),
|
361 |
|
|
.queued1(queued1),
|
362 |
|
|
.queued2(1'b0),
|
363 |
|
|
.fetchbuf0_v(fetchbuf1_v),
|
364 |
|
|
.fetchbuf0_pc(fetchbuf1_pc),
|
365 |
|
|
.fetchbuf0_instr(fetchbuf1_instr),
|
366 |
|
|
.fetchbuf1_v(1'b0),
|
367 |
|
|
.fetchbuf1_pc(32'h00000000),
|
368 |
|
|
.fetchbuf1_instr(`NOP_INSN),
|
369 |
|
|
.stompedRets(stompedRets[3:1]),
|
370 |
|
|
.stompedRet(stompedRet),
|
371 |
|
|
.pc(retpc1)
|
372 |
|
|
);
|
373 |
|
|
`else
|
374 |
|
|
assign retpc0 = RSTPC;
|
375 |
|
|
assign retpc1 = RSTPC;
|
376 |
|
|
`endif
|
377 |
|
|
|
378 |
|
|
wire peclk, neclk;
|
379 |
|
|
edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
|
380 |
|
|
|
381 |
|
|
always @(posedge clk)
|
382 |
|
|
if (rst) begin
|
383 |
|
|
pc0 <= RSTPC;
|
384 |
|
|
pc1 <= RSTPC;
|
385 |
|
|
fetchbufA_v <= 0;
|
386 |
|
|
fetchbufB_v <= 0;
|
387 |
|
|
fetchbufC_v <= 0;
|
388 |
|
|
fetchbufD_v <= 0;
|
389 |
|
|
fetchbuf <= 0;
|
390 |
|
|
panic <= `PANIC_NONE;
|
391 |
|
|
end
|
392 |
|
|
else begin
|
393 |
|
|
|
394 |
|
|
did_branchback0 <= take_branch0;
|
395 |
|
|
did_branchback1 <= take_branch1;
|
396 |
|
|
|
397 |
|
|
stompedRet = FALSE;
|
398 |
|
|
|
399 |
|
|
begin
|
400 |
|
|
|
401 |
|
|
// On a branch miss with threading enabled all fectch buffers are
|
402 |
|
|
// invalidated even though the data in the fetch buffer would be valid
|
403 |
|
|
// for the thread that isn't in a branchmiss state. This is done to
|
404 |
|
|
// keep things simple. For the thread that doesn't miss the current
|
405 |
|
|
// data for the fetch buffer needs to be retrieved again, so the pc
|
406 |
|
|
// for that thread is assigned the current fetchbuf pc.
|
407 |
|
|
// For the thread that misses the pc is simply assigned the misspc.
|
408 |
|
|
if (branchmiss) begin
|
409 |
|
|
$display("***********");
|
410 |
|
|
$display("Branch miss");
|
411 |
|
|
$display("***********");
|
412 |
|
|
if (branchmiss_thrd) begin
|
413 |
|
|
pc1 <= misspc;
|
414 |
|
|
fetchbufB_v <= `INV;
|
415 |
|
|
fetchbufD_v <= `INV;
|
416 |
|
|
end
|
417 |
|
|
else begin
|
418 |
|
|
pc0 <= misspc;
|
419 |
|
|
if (thread_en) begin
|
420 |
|
|
fetchbufA_v <= `INV;
|
421 |
|
|
fetchbufC_v <= `INV;
|
422 |
|
|
end
|
423 |
|
|
else begin
|
424 |
|
|
fetchbufA_v <= `INV;
|
425 |
|
|
fetchbufB_v <= `INV;
|
426 |
|
|
fetchbufC_v <= `INV;
|
427 |
|
|
fetchbufD_v <= `INV;
|
428 |
|
|
fetchbuf <= 1'b0;
|
429 |
|
|
end
|
430 |
|
|
end
|
431 |
|
|
$display("********************");
|
432 |
|
|
$display("********************");
|
433 |
|
|
$display("********************");
|
434 |
|
|
$display("Branch miss");
|
435 |
|
|
$display("misspc=%h", misspc);
|
436 |
|
|
$display("********************");
|
437 |
|
|
$display("********************");
|
438 |
|
|
$display("********************");
|
439 |
|
|
end
|
440 |
|
|
else if (take_branch) begin
|
441 |
|
|
|
442 |
|
|
// update the fetchbuf valid bits as well as fetchbuf itself
|
443 |
|
|
// ... this must be based on which things are backwards branches, how many things
|
444 |
|
|
// will get enqueued (0, 1, or 2), and how old the instructions are
|
445 |
|
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, fetchbufB_v, fetchbufC_v, fetchbufD_v})
|
446 |
|
|
|
447 |
|
|
4'b0000: ; // do nothing
|
448 |
|
|
4'b0001: if (thread_en) FetchC();
|
449 |
|
|
4'b0010: if (thread_en) FetchD();
|
450 |
|
|
4'b0011: ;
|
451 |
|
|
4'b0100 :
|
452 |
|
|
begin
|
453 |
|
|
if (thread_en) begin
|
454 |
|
|
FetchC();
|
455 |
|
|
pc1 <= branch_pcB;
|
456 |
|
|
end
|
457 |
|
|
else
|
458 |
|
|
pc0 <= branch_pcB;
|
459 |
|
|
fetchbufB_v <= !(queued1|queuedNop); // if it can be queued, it will
|
460 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
461 |
|
|
end
|
462 |
|
|
4'b0101:
|
463 |
|
|
begin
|
464 |
|
|
if (thread_en) begin
|
465 |
|
|
pc1 <= branch_pcB;
|
466 |
|
|
FetchC();
|
467 |
|
|
end
|
468 |
|
|
else
|
469 |
|
|
pc0 <= branch_pcB;
|
470 |
|
|
fetchbufD_v <= `INV;
|
471 |
|
|
fetchbufB_v <= !(queued1|queuedNop);
|
472 |
|
|
end
|
473 |
|
|
4'b0110:
|
474 |
|
|
begin
|
475 |
|
|
if (thread_en)
|
476 |
|
|
pc1 <= branch_pcB;
|
477 |
|
|
else begin
|
478 |
|
|
pc0 <= branch_pcB;
|
479 |
|
|
fetchbufC_v <= `INV;
|
480 |
|
|
end
|
481 |
|
|
fetchbufB_v <= !(queued1|queuedNop);
|
482 |
|
|
end
|
483 |
|
|
4'b0111:
|
484 |
|
|
begin
|
485 |
|
|
if (thread_en) begin
|
486 |
|
|
pc1 <= branch_pcB;
|
487 |
|
|
fetchbufD_v <= `INV;
|
488 |
|
|
end
|
489 |
|
|
else begin
|
490 |
|
|
pc0 <= branch_pcB;
|
491 |
|
|
fetchbufC_v <= `INV;
|
492 |
|
|
fetchbufD_v <= `INV;
|
493 |
|
|
end
|
494 |
|
|
fetchbufB_v <= !(queued1|queuedNop); // if it can be queued, it will
|
495 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
496 |
|
|
end
|
497 |
|
|
4'b1000 :
|
498 |
|
|
begin
|
499 |
|
|
if (thread_en) FetchD();
|
500 |
|
|
pc0 <= branch_pcA;
|
501 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
502 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
503 |
|
|
end
|
504 |
|
|
4'b1001:
|
505 |
|
|
begin
|
506 |
|
|
pc0 <= branch_pcA;
|
507 |
|
|
if (!thread_en)
|
508 |
|
|
fetchbufD_v <= `INV;
|
509 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
510 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
511 |
|
|
end
|
512 |
|
|
4'b1010:
|
513 |
|
|
begin
|
514 |
|
|
pc0 <= branch_pcA;
|
515 |
|
|
fetchbufC_v <= `INV;
|
516 |
|
|
if (thread_en) FetchD();
|
517 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
518 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
519 |
|
|
end
|
520 |
|
|
4'b1011:
|
521 |
|
|
begin
|
522 |
|
|
pc0 <= branch_pcA;
|
523 |
|
|
fetchbufC_v <= `INV;
|
524 |
|
|
if (!thread_en)
|
525 |
|
|
fetchbufD_v <= `INV;
|
526 |
|
|
fetchbufA_v <=!(queued1|queuedNop); // if it can be queued, it will
|
527 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
528 |
|
|
end
|
529 |
|
|
4'b1100:
|
530 |
|
|
if (thread_en) begin
|
531 |
|
|
if (take_branchA && take_branchB) begin
|
532 |
|
|
pc0 <= branch_pcA;
|
533 |
|
|
pc1 <= branch_pcB;
|
534 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
535 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
536 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
537 |
|
|
end
|
538 |
|
|
else if (take_branchA) begin
|
539 |
|
|
FetchD();
|
540 |
|
|
pc0 <= branch_pcA;
|
541 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
542 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
543 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
544 |
|
|
end
|
545 |
|
|
else if (take_branchB) begin
|
546 |
|
|
FetchC();
|
547 |
|
|
pc1 <= branch_pcB;
|
548 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
549 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
550 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
551 |
|
|
end
|
552 |
|
|
end
|
553 |
|
|
else begin
|
554 |
|
|
if (take_branchA) begin
|
555 |
|
|
pc0 <= branch_pcA;
|
556 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
557 |
|
|
fetchbufB_v <= `INV;
|
558 |
|
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
559 |
|
|
end
|
560 |
|
|
else if (take_branchB) begin
|
561 |
|
|
pc0 <= branch_pcB;
|
562 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
563 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
564 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
565 |
|
|
end
|
566 |
|
|
// else hardware error
|
567 |
|
|
end
|
568 |
|
|
4'b1101:
|
569 |
|
|
if (thread_en) begin
|
570 |
|
|
if (take_branchA && take_branchB) begin
|
571 |
|
|
pc0 <= branch_pcA;
|
572 |
|
|
pc1 <= branch_pcB;
|
573 |
|
|
fetchbufD_v <= `INV;
|
574 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
575 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
576 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
577 |
|
|
end
|
578 |
|
|
else if (take_branchA) begin
|
579 |
|
|
pc0 <= branch_pcA;
|
580 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
581 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
582 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
583 |
|
|
end
|
584 |
|
|
else if (take_branchB) begin
|
585 |
|
|
FetchC();
|
586 |
|
|
pc1 <= branch_pcB;
|
587 |
|
|
fetchbufD_v <= `INV;
|
588 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
589 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
590 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
591 |
|
|
end
|
592 |
|
|
end
|
593 |
|
|
else begin
|
594 |
|
|
fetchbufD_v <= `INV;
|
595 |
|
|
if (take_branchA) begin
|
596 |
|
|
pc0 <= branch_pcA;
|
597 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
598 |
|
|
fetchbufB_v <= `INV;
|
599 |
|
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
600 |
|
|
end
|
601 |
|
|
else if (take_branchB) begin
|
602 |
|
|
pc0 <= branch_pcB;
|
603 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
604 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
605 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
606 |
|
|
end
|
607 |
|
|
// else hardware error
|
608 |
|
|
end
|
609 |
|
|
4'b1110:
|
610 |
|
|
if (thread_en) begin
|
611 |
|
|
if (take_branchA && take_branchB) begin
|
612 |
|
|
pc0 <= branch_pcA;
|
613 |
|
|
pc1 <= branch_pcB;
|
614 |
|
|
fetchbufC_v <= `INV;
|
615 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
616 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
617 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
618 |
|
|
end
|
619 |
|
|
else if (take_branchA) begin
|
620 |
|
|
FetchD();
|
621 |
|
|
pc0 <= branch_pcA;
|
622 |
|
|
fetchbufC_v <= `INV;
|
623 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
624 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
625 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
626 |
|
|
end
|
627 |
|
|
else if (take_branchB) begin
|
628 |
|
|
pc1 <= branch_pcB;
|
629 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
630 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
631 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
632 |
|
|
end
|
633 |
|
|
end
|
634 |
|
|
else begin
|
635 |
|
|
fetchbufC_v <= `INV;
|
636 |
|
|
if (take_branchA) begin
|
637 |
|
|
pc0 <= branch_pcA;
|
638 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
639 |
|
|
fetchbufB_v <= `INV;
|
640 |
|
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
641 |
|
|
end
|
642 |
|
|
else if (take_branchB) begin
|
643 |
|
|
pc0 <= branch_pcB;
|
644 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
645 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
646 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
647 |
|
|
end
|
648 |
|
|
// else hardware error
|
649 |
|
|
end
|
650 |
|
|
4'b1111:
|
651 |
|
|
begin
|
652 |
|
|
if (thread_en) begin
|
653 |
|
|
if (take_branchA & take_branchB) begin
|
654 |
|
|
pc0 <= branch_pcA;
|
655 |
|
|
pc1 <= branch_pcB;
|
656 |
|
|
fetchbufC_v <= `INV;
|
657 |
|
|
fetchbufD_v <= `INV;
|
658 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
659 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
660 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
661 |
|
|
end
|
662 |
|
|
else if (take_branchA) begin
|
663 |
|
|
pc0 <= branch_pcA;
|
664 |
|
|
fetchbufC_v <= `INV;
|
665 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
666 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
667 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
668 |
|
|
end
|
669 |
|
|
else if (take_branchB) begin
|
670 |
|
|
pc1 <= branch_pcB;
|
671 |
|
|
fetchbufD_v <= `INV;
|
672 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
673 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
674 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
675 |
|
|
end
|
676 |
|
|
end
|
677 |
|
|
else begin
|
678 |
|
|
if (take_branchA) begin
|
679 |
|
|
pc0 <= branch_pcA;
|
680 |
|
|
fetchbufB_v <= `INV;
|
681 |
|
|
fetchbufC_v <= `INV;
|
682 |
|
|
fetchbufD_v <= `INV;
|
683 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
684 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
685 |
|
|
end
|
686 |
|
|
else if (take_branchB) begin
|
687 |
|
|
pc0 <= branch_pcB;
|
688 |
|
|
fetchbufC_v <= `INV;
|
689 |
|
|
fetchbufD_v <= `INV;
|
690 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
691 |
|
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
692 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
693 |
|
|
end
|
694 |
|
|
end
|
695 |
|
|
end
|
696 |
|
|
default: ;
|
697 |
|
|
endcase
|
698 |
|
|
else case ({fetchbufC_v, fetchbufD_v, fetchbufA_v, fetchbufB_v})
|
699 |
|
|
|
700 |
|
|
4'b0000: ; // do nothing
|
701 |
|
|
4'b0001: if (thread_en) FetchA();
|
702 |
|
|
4'b0010: if (thread_en) FetchB();
|
703 |
|
|
4'b0011: ;
|
704 |
|
|
4'b0100 :
|
705 |
|
|
begin
|
706 |
|
|
if (thread_en) begin
|
707 |
|
|
FetchA();
|
708 |
|
|
pc1 <= branch_pcD;
|
709 |
|
|
end
|
710 |
|
|
else
|
711 |
|
|
pc0 <= branch_pcD;
|
712 |
|
|
fetchbufD_v <= !(queued1|queuedNop); // if it can be queued, it will
|
713 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
714 |
|
|
end
|
715 |
|
|
4'b0101:
|
716 |
|
|
begin
|
717 |
|
|
if (thread_en) begin
|
718 |
|
|
pc1 <= branch_pcD;
|
719 |
|
|
FetchA();
|
720 |
|
|
end
|
721 |
|
|
else
|
722 |
|
|
pc0 <= branch_pcD;
|
723 |
|
|
fetchbufB_v <= `INV;
|
724 |
|
|
fetchbufD_v <= !(queued1|queuedNop);
|
725 |
|
|
end
|
726 |
|
|
4'b0110:
|
727 |
|
|
begin
|
728 |
|
|
if (thread_en)
|
729 |
|
|
pc1 <= branch_pcD;
|
730 |
|
|
else begin
|
731 |
|
|
pc0 <= branch_pcD;
|
732 |
|
|
fetchbufA_v <= `INV;
|
733 |
|
|
end
|
734 |
|
|
fetchbufD_v <= !(queued1|queuedNop);
|
735 |
|
|
end
|
736 |
|
|
4'b0111:
|
737 |
|
|
begin
|
738 |
|
|
if (thread_en) begin
|
739 |
|
|
pc1 <= branch_pcD;
|
740 |
|
|
fetchbufB_v <= `INV;
|
741 |
|
|
end
|
742 |
|
|
else begin
|
743 |
|
|
pc0 <= branch_pcD;
|
744 |
|
|
fetchbufA_v <= `INV;
|
745 |
|
|
fetchbufB_v <= `INV;
|
746 |
|
|
end
|
747 |
|
|
fetchbufD_v <= !(queued1|queuedNop); // if it can be queued, it will
|
748 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
749 |
|
|
end
|
750 |
|
|
4'b1000 :
|
751 |
|
|
begin
|
752 |
|
|
if (thread_en) FetchB();
|
753 |
|
|
pc0 <= branch_pcC;
|
754 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
755 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
756 |
|
|
end
|
757 |
|
|
4'b1001:
|
758 |
|
|
begin
|
759 |
|
|
pc0 <= branch_pcC;
|
760 |
|
|
if (!thread_en)
|
761 |
|
|
fetchbufB_v <= `INV;
|
762 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
763 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
764 |
|
|
end
|
765 |
|
|
4'b1010:
|
766 |
|
|
begin
|
767 |
|
|
pc0 <= branch_pcC;
|
768 |
|
|
fetchbufA_v <= `INV;
|
769 |
|
|
if (thread_en) FetchB();
|
770 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
771 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
772 |
|
|
end
|
773 |
|
|
4'b1011:
|
774 |
|
|
begin
|
775 |
|
|
pc0 <= branch_pcC;
|
776 |
|
|
fetchbufA_v <= `INV;
|
777 |
|
|
if (!thread_en)
|
778 |
|
|
fetchbufB_v <= `INV;
|
779 |
|
|
fetchbufC_v <=!(queued1|queuedNop); // if it can be queued, it will
|
780 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
781 |
|
|
end
|
782 |
|
|
4'b1100:
|
783 |
|
|
if (thread_en) begin
|
784 |
|
|
if (take_branchC && take_branchD) begin
|
785 |
|
|
pc0 <= branch_pcC;
|
786 |
|
|
pc1 <= branch_pcD;
|
787 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
788 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
789 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
790 |
|
|
end
|
791 |
|
|
else if (take_branchC) begin
|
792 |
|
|
FetchB();
|
793 |
|
|
pc0 <= branch_pcC;
|
794 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
795 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
796 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
797 |
|
|
end
|
798 |
|
|
else if (take_branchD) begin
|
799 |
|
|
FetchA();
|
800 |
|
|
pc1 <= branch_pcD;
|
801 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
802 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
803 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
804 |
|
|
end
|
805 |
|
|
end
|
806 |
|
|
else begin
|
807 |
|
|
if (take_branchC) begin
|
808 |
|
|
pc0 <= branch_pcC;
|
809 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
810 |
|
|
fetchbufD_v <= `INV;
|
811 |
|
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
812 |
|
|
end
|
813 |
|
|
else if (take_branchD) begin
|
814 |
|
|
pc0 <= branch_pcD;
|
815 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
816 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
817 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
818 |
|
|
end
|
819 |
|
|
// else hardware error
|
820 |
|
|
end
|
821 |
|
|
4'b1101:
|
822 |
|
|
if (thread_en) begin
|
823 |
|
|
if (take_branchC && take_branchD) begin
|
824 |
|
|
pc0 <= branch_pcC;
|
825 |
|
|
pc1 <= branch_pcD;
|
826 |
|
|
fetchbufB_v <= `INV;
|
827 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
828 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
829 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
830 |
|
|
end
|
831 |
|
|
else if (take_branchC) begin
|
832 |
|
|
pc0 <= branch_pcC;
|
833 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
834 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
835 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
836 |
|
|
end
|
837 |
|
|
else if (take_branchC) begin
|
838 |
|
|
FetchA();
|
839 |
|
|
pc1 <= branch_pcD;
|
840 |
|
|
fetchbufB_v <= `INV;
|
841 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
842 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
843 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
844 |
|
|
end
|
845 |
|
|
end
|
846 |
|
|
else begin
|
847 |
|
|
fetchbufB_v <= `INV;
|
848 |
|
|
if (take_branchC) begin
|
849 |
|
|
pc0 <= branch_pcC;
|
850 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
851 |
|
|
fetchbufD_v <= `INV;
|
852 |
|
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
853 |
|
|
end
|
854 |
|
|
else if (take_branchD) begin
|
855 |
|
|
pc0 <= branch_pcD;
|
856 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
857 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
858 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
859 |
|
|
end
|
860 |
|
|
// else hardware error
|
861 |
|
|
end
|
862 |
|
|
4'b1110:
|
863 |
|
|
if (thread_en) begin
|
864 |
|
|
if (take_branchC && take_branchD) begin
|
865 |
|
|
pc0 <= branch_pcC;
|
866 |
|
|
pc1 <= branch_pcD;
|
867 |
|
|
fetchbufA_v <= `INV;
|
868 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
869 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
870 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
871 |
|
|
end
|
872 |
|
|
else if (take_branchC) begin
|
873 |
|
|
FetchB();
|
874 |
|
|
pc0 <= branch_pcC;
|
875 |
|
|
fetchbufA_v <= `INV;
|
876 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
877 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
878 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
879 |
|
|
end
|
880 |
|
|
else if (take_branchD) begin
|
881 |
|
|
pc1 <= branch_pcD;
|
882 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
883 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
884 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
885 |
|
|
end
|
886 |
|
|
end
|
887 |
|
|
else begin
|
888 |
|
|
fetchbufA_v <= `INV;
|
889 |
|
|
if (take_branchC) begin
|
890 |
|
|
pc0 <= branch_pcC;
|
891 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
892 |
|
|
fetchbufD_v <= `INV;
|
893 |
|
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
894 |
|
|
end
|
895 |
|
|
else if (take_branchD) begin
|
896 |
|
|
pc0 <= branch_pcD;
|
897 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
898 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
899 |
|
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
900 |
|
|
end
|
901 |
|
|
// else hardware error
|
902 |
|
|
end
|
903 |
|
|
4'b1111:
|
904 |
|
|
begin
|
905 |
|
|
if (thread_en) begin
|
906 |
|
|
if (take_branchC & take_branchD) begin
|
907 |
|
|
pc0 <= branch_pcC;
|
908 |
|
|
pc1 <= branch_pcD;
|
909 |
|
|
fetchbufA_v <= `INV;
|
910 |
|
|
fetchbufB_v <= `INV;
|
911 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
912 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
913 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
914 |
|
|
end
|
915 |
|
|
else if (take_branchC) begin
|
916 |
|
|
pc0 <= branch_pcD;
|
917 |
|
|
fetchbufA_v <= `INV;
|
918 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
919 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
920 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
921 |
|
|
end
|
922 |
|
|
else if (take_branchD) begin
|
923 |
|
|
pc1 <= branch_pcD;
|
924 |
|
|
fetchbufB_v <= `INV;
|
925 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
926 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
927 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
928 |
|
|
end
|
929 |
|
|
end
|
930 |
|
|
else begin
|
931 |
|
|
if (take_branchC) begin
|
932 |
|
|
pc0 <= branch_pcC;
|
933 |
|
|
fetchbufD_v <= `INV;
|
934 |
|
|
fetchbufA_v <= `INV;
|
935 |
|
|
fetchbufB_v <= `INV;
|
936 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
937 |
|
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
938 |
|
|
end
|
939 |
|
|
else if (take_branchD) begin
|
940 |
|
|
pc0 <= branch_pcD;
|
941 |
|
|
fetchbufA_v <= `INV;
|
942 |
|
|
fetchbufB_v <= `INV;
|
943 |
|
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
944 |
|
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
945 |
|
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
946 |
|
|
end
|
947 |
|
|
end
|
948 |
|
|
end
|
949 |
|
|
default: ;
|
950 |
|
|
endcase
|
951 |
|
|
end // if branchback
|
952 |
|
|
|
953 |
|
|
else begin // there is no branchback in the system
|
954 |
|
|
//
|
955 |
|
|
// update fetchbufX_v and fetchbuf ... relatively simple, as
|
956 |
|
|
// there are no backwards branches in the mix
|
957 |
|
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, fetchbufB_v, (queued1|queuedNop), (queued2|queuedNop)})
|
958 |
|
|
4'b00_00 : ; // do nothing
|
959 |
|
|
4'b00_01: ;
|
960 |
|
|
4'b00_10: ;
|
961 |
|
|
4'b00_11: ;
|
962 |
|
|
4'b01_00: ; // do nothing
|
963 |
|
|
4'b01_01: ;
|
964 |
|
|
4'b01_10,
|
965 |
|
|
4'b01_11:
|
966 |
|
|
begin // enqueue fbB and flip fetchbuf
|
967 |
|
|
fetchbufB_v <= `INV;
|
968 |
|
|
fetchbuf <= ~fetchbuf;
|
969 |
|
|
end
|
970 |
|
|
4'b10_00: ; // do nothing
|
971 |
|
|
4'b10_01: ;
|
972 |
|
|
4'b10_10,
|
973 |
|
|
4'b10_11:
|
974 |
|
|
begin // enqueue fbA and flip fetchbuf
|
975 |
|
|
fetchbufA_v <= `INV;
|
976 |
|
|
fetchbuf <= ~fetchbuf;
|
977 |
|
|
end
|
978 |
|
|
4'b11_00: ; // do nothing
|
979 |
|
|
4'b11_01: ;
|
980 |
|
|
4'b11_10:
|
981 |
|
|
begin // enqueue fbA but leave fetchbuf
|
982 |
|
|
fetchbufA_v <= `INV;
|
983 |
|
|
end
|
984 |
|
|
4'b11_11:
|
985 |
|
|
begin // enqueue both and flip fetchbuf
|
986 |
|
|
fetchbufA_v <= `INV;
|
987 |
|
|
fetchbufB_v <= `INV;
|
988 |
|
|
fetchbuf <= ~fetchbuf;
|
989 |
|
|
end
|
990 |
|
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
991 |
|
|
endcase
|
992 |
|
|
else case ({fetchbufC_v, fetchbufD_v, (queued1|queuedNop), (queued2|queuedNop)})
|
993 |
|
|
4'b00_00 : ; // do nothing
|
994 |
|
|
4'b00_01: ;
|
995 |
|
|
4'b00_10 : ; // do nothing
|
996 |
|
|
4'b00_11 : ; // do nothing
|
997 |
|
|
4'b01_00 : ; // do nothing
|
998 |
|
|
4'b01_01 : ;
|
999 |
|
|
4'b01_10,
|
1000 |
|
|
4'b01_11 :
|
1001 |
|
|
begin // enqueue fbD and flip fetchbuf
|
1002 |
|
|
fetchbufD_v <= `INV;
|
1003 |
|
|
fetchbuf <= ~fetchbuf;
|
1004 |
|
|
end
|
1005 |
|
|
4'b10_00 : ; // do nothing
|
1006 |
|
|
4'b10_01: ;
|
1007 |
|
|
4'b10_10,
|
1008 |
|
|
4'b10_11:
|
1009 |
|
|
begin // enqueue fbC and flip fetchbuf
|
1010 |
|
|
fetchbufC_v <= `INV;
|
1011 |
|
|
fetchbuf <= ~fetchbuf;
|
1012 |
|
|
end
|
1013 |
|
|
4'b11_00 : ; // do nothing
|
1014 |
|
|
4'b11_01: ;
|
1015 |
|
|
4'b11_10:
|
1016 |
|
|
begin // enqueue fbC but leave fetchbuf
|
1017 |
|
|
fetchbufC_v <= `INV;
|
1018 |
|
|
end
|
1019 |
|
|
4'b11_11:
|
1020 |
|
|
begin // enqueue both and flip fetchbuf
|
1021 |
|
|
fetchbufC_v <= `INV;
|
1022 |
|
|
fetchbufD_v <= `INV;
|
1023 |
|
|
fetchbuf <= ~fetchbuf;
|
1024 |
|
|
end
|
1025 |
|
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
1026 |
|
|
endcase
|
1027 |
|
|
//
|
1028 |
|
|
// get data iff the fetch buffers are empty
|
1029 |
|
|
//
|
1030 |
|
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
|
1031 |
|
|
FetchAB();
|
1032 |
|
|
// fetchbuf steering logic correction
|
1033 |
|
|
if (fetchbufC_v==`INV && fetchbufD_v==`INV && phit)
|
1034 |
|
|
fetchbuf <= 1'b0;
|
1035 |
|
|
end
|
1036 |
|
|
else if (fetchbufC_v == `INV && fetchbufD_v == `INV)
|
1037 |
|
|
FetchCD();
|
1038 |
|
|
end
|
1039 |
|
|
//
|
1040 |
|
|
// get data iff the fetch buffers are empty
|
1041 |
|
|
//
|
1042 |
|
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV && fetchbufC_v==`INV && fetchbufD_v==`INV) begin
|
1043 |
|
|
FetchAB();
|
1044 |
|
|
fetchbuf <= 1'b0;
|
1045 |
|
|
end
|
1046 |
|
|
end
|
1047 |
|
|
|
1048 |
|
|
// The fetchbuffer is invalidated at the end of a vector instruction
|
1049 |
|
|
// queue.
|
1050 |
|
|
if (nop_fetchbuf[0]) fetchbufA_v <= `INV;
|
1051 |
|
|
if (nop_fetchbuf[1]) fetchbufB_v <= `INV;
|
1052 |
|
|
if (nop_fetchbuf[2]) fetchbufC_v <= `INV;
|
1053 |
|
|
if (nop_fetchbuf[3]) fetchbufD_v <= `INV;
|
1054 |
|
|
end
|
1055 |
|
|
|
1056 |
|
|
assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufC_instr;
|
1057 |
|
|
assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufC_inslen;
|
1058 |
|
|
assign fetchbuf0_v = (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufC_v ;
|
1059 |
|
|
assign fetchbuf0_pc = (fetchbuf == 1'b0) ? fetchbufA_pc : fetchbufC_pc ;
|
1060 |
|
|
assign fetchbuf1_instr = (fetchbuf == 1'b0) ? fetchbufB_instr : fetchbufD_instr;
|
1061 |
|
|
assign fetchbuf1_insln = (fetchbuf == 1'b0) ? fetchbufB_inslen: fetchbufD_inslen;
|
1062 |
|
|
assign fetchbuf1_v = (fetchbuf == 1'b0) ? fetchbufB_v : fetchbufD_v ;
|
1063 |
|
|
assign fetchbuf1_pc = (fetchbuf == 1'b0) ? fetchbufB_pc : fetchbufD_pc ;
|
1064 |
|
|
assign fetchbuf0_thrd = 1'b0;
|
1065 |
|
|
assign fetchbuf1_thrd = thread_en;
|
1066 |
|
|
|
1067 |
|
|
reg [2:0] insln0, insln1;
|
1068 |
|
|
always @*
|
1069 |
|
|
begin
|
1070 |
|
|
`ifdef SUPPORT_DCI
|
1071 |
|
|
if (insn0[5:0]==`CMPRSSD)
|
1072 |
|
|
insln0 <= 3'd2;
|
1073 |
|
|
else
|
1074 |
|
|
`endif
|
1075 |
|
|
if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
|
1076 |
|
|
insln0 <= fnInsLength(codebuf0);
|
1077 |
|
|
else
|
1078 |
|
|
insln0 <= fnInsLength(insn0);
|
1079 |
|
|
end
|
1080 |
|
|
|
1081 |
|
|
always @*
|
1082 |
|
|
begin
|
1083 |
|
|
`ifdef SUPPORT_DCI
|
1084 |
|
|
if (insn1[5:0]==`CMPRSSD)
|
1085 |
|
|
insln1 <= 3'd2;
|
1086 |
|
|
else
|
1087 |
|
|
`endif
|
1088 |
|
|
if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
|
1089 |
|
|
insln1 <= fnInsLength(codebuf1);
|
1090 |
|
|
else
|
1091 |
|
|
insln1 <= fnInsLength(insn1);
|
1092 |
|
|
end
|
1093 |
|
|
|
1094 |
|
|
reg [47:0] cinsn0, cinsn1;
|
1095 |
|
|
|
1096 |
|
|
always @*
|
1097 |
|
|
begin
|
1098 |
|
|
`ifdef SUPPORT_DCI
|
1099 |
|
|
if (insn0[5:0]==`CMPRSSD)
|
1100 |
|
|
cinsn0 <= expand0;
|
1101 |
|
|
else
|
1102 |
|
|
`endif
|
1103 |
|
|
if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
|
1104 |
|
|
cinsn0 <= codebuf0;
|
1105 |
|
|
else if (insn0[7])
|
1106 |
|
|
cinsn0 <= xinsn0;
|
1107 |
|
|
else
|
1108 |
|
|
cinsn0 <= insn0;
|
1109 |
|
|
end
|
1110 |
|
|
|
1111 |
|
|
always @*
|
1112 |
|
|
begin
|
1113 |
|
|
`ifdef SUPPORT_DCI
|
1114 |
|
|
if (insn1[5:0]==`CMPRSSD)
|
1115 |
|
|
cinsn1 <= expand1;
|
1116 |
|
|
else
|
1117 |
|
|
`endif
|
1118 |
|
|
if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
|
1119 |
|
|
cinsn1 <= codebuf1;
|
1120 |
|
|
else if (insn1[7])
|
1121 |
|
|
cinsn1 <= xinsn1;
|
1122 |
|
|
else
|
1123 |
|
|
cinsn1 <= insn1;
|
1124 |
|
|
end
|
1125 |
|
|
|
1126 |
|
|
task FetchA;
|
1127 |
|
|
begin
|
1128 |
|
|
fetchbufA_instr <= cinsn0;
|
1129 |
|
|
fetchbufA_v <= `VAL;
|
1130 |
|
|
fetchbufA_pc <= pc0;
|
1131 |
|
|
if (phit && ~freezePC) begin
|
1132 |
|
|
if (thread_en)
|
1133 |
|
|
pc0 <= pc0 + insln0;
|
1134 |
|
|
else if (`WAYS > 1)
|
1135 |
|
|
pc0 <= pc0 + insln0 + insln1;
|
1136 |
|
|
else
|
1137 |
|
|
pc0 <= pc0 + insln0;
|
1138 |
|
|
end
|
1139 |
|
|
end
|
1140 |
|
|
endtask
|
1141 |
|
|
|
1142 |
|
|
task FetchB;
|
1143 |
|
|
begin
|
1144 |
|
|
fetchbufB_instr <= cinsn1;
|
1145 |
|
|
fetchbufB_v <= `WAYS > 1;
|
1146 |
|
|
if (thread_en)
|
1147 |
|
|
fetchbufB_pc <= pc1;
|
1148 |
|
|
else
|
1149 |
|
|
fetchbufB_pc <= pc0 + insln0;
|
1150 |
|
|
if (phit & thread_en)
|
1151 |
|
|
pc1 <= pc1 + insln1;
|
1152 |
|
|
end
|
1153 |
|
|
endtask
|
1154 |
|
|
|
1155 |
|
|
|
1156 |
|
|
task FetchAB;
|
1157 |
|
|
begin
|
1158 |
|
|
FetchA();
|
1159 |
|
|
FetchB();
|
1160 |
|
|
end
|
1161 |
|
|
endtask
|
1162 |
|
|
|
1163 |
|
|
task FetchC;
|
1164 |
|
|
begin
|
1165 |
|
|
fetchbufC_instr <= cinsn0;
|
1166 |
|
|
fetchbufC_v <= `VAL;
|
1167 |
|
|
fetchbufC_pc <= pc0;
|
1168 |
|
|
if (phit && ~freezePC) begin
|
1169 |
|
|
if (thread_en)
|
1170 |
|
|
pc0 <= pc0 + insln0;
|
1171 |
|
|
else if (`WAYS > 1)
|
1172 |
|
|
pc0 <= pc0 + insln0 + insln1;
|
1173 |
|
|
else
|
1174 |
|
|
pc0 <= pc0 + insln0;
|
1175 |
|
|
end
|
1176 |
|
|
end
|
1177 |
|
|
endtask
|
1178 |
|
|
|
1179 |
|
|
task FetchD;
|
1180 |
|
|
begin
|
1181 |
|
|
fetchbufD_instr <= cinsn1;
|
1182 |
|
|
fetchbufD_v <= `WAYS > 1;
|
1183 |
|
|
if (thread_en)
|
1184 |
|
|
fetchbufD_pc <= pc1;
|
1185 |
|
|
else
|
1186 |
|
|
fetchbufD_pc <= pc0 + insln0;
|
1187 |
|
|
if (phit & thread_en)
|
1188 |
|
|
pc1 <= pc1 + insln1;
|
1189 |
|
|
end
|
1190 |
|
|
endtask
|
1191 |
|
|
|
1192 |
|
|
task FetchCD;
|
1193 |
|
|
begin
|
1194 |
|
|
FetchC();
|
1195 |
|
|
FetchD();
|
1196 |
|
|
end
|
1197 |
|
|
endtask
|
1198 |
|
|
|
1199 |
|
|
endmodule
|
1200 |
|
|
|