1 |
60 |
robfinch |
// ============================================================================
|
2 |
|
|
// __
|
3 |
|
|
// \\__/ o\ (C) 2018 Robert Finch, Waterloo
|
4 |
|
|
// \ __ / All rights reserved.
|
5 |
|
|
// \/_// robfinch<remove>@finitron.ca
|
6 |
|
|
// ||
|
7 |
|
|
//
|
8 |
|
|
// FT64_fetchbuf_x1.v
|
9 |
|
|
//
|
10 |
|
|
// This source file is free software: you can redistribute it and/or modify
|
11 |
|
|
// it under the terms of the GNU Lesser General Public License as published
|
12 |
|
|
// by the Free Software Foundation, either version 3 of the License, or
|
13 |
|
|
// (at your option) any later version.
|
14 |
|
|
//
|
15 |
|
|
// This source file is distributed in the hope that it will be useful,
|
16 |
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
17 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
18 |
|
|
// GNU General Public License for more details.
|
19 |
|
|
//
|
20 |
|
|
// You should have received a copy of the GNU General Public License
|
21 |
|
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
22 |
|
|
//
|
23 |
|
|
// ============================================================================
|
24 |
|
|
//
|
25 |
|
|
`include "FT64_config.vh"
|
26 |
|
|
`include "FT64_defines.vh"
|
27 |
|
|
|
28 |
|
|
// FETCH
|
29 |
|
|
//
|
30 |
|
|
// fetch exactly one instructions from memory into the fetch buffer
|
31 |
|
|
// unless either one of the buffers is still full, in which case we
|
32 |
|
|
// do nothing (kinda like alpha approach)
|
33 |
|
|
//
|
34 |
|
|
module FT64_fetchbuf_x1(rst, clk4x, clk, fcu_clk,
|
35 |
|
|
cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
|
36 |
|
|
cmpgrp,
|
37 |
|
|
freezePC, thread_en, pred_on,
|
38 |
|
|
regLR,
|
39 |
|
|
insn0, phit,
|
40 |
|
|
threadx,
|
41 |
|
|
branchmiss, misspc, branchmiss_thrd, predict_taken0,
|
42 |
|
|
predict_takenA, predict_takenB,
|
43 |
|
|
queued1, queuedNop,
|
44 |
|
|
pc0, fetchbuf, fetchbufA_v, fetchbufB_v,
|
45 |
|
|
fetchbufA_instr, fetchbufA_pc, fetchbufA_pbyte,
|
46 |
|
|
fetchbufB_instr, fetchbufB_pc, fetchbufB_pbyte,
|
47 |
|
|
fetchbuf0_instr, fetchbuf0_insln,
|
48 |
|
|
fetchbuf0_thrd,
|
49 |
|
|
fetchbuf0_pc,
|
50 |
|
|
fetchbuf0_v,
|
51 |
|
|
fetchbuf0_pbyte,
|
52 |
|
|
codebuf0,
|
53 |
|
|
btgtA, btgtB,
|
54 |
|
|
nop_fetchbuf,
|
55 |
|
|
take_branch0,
|
56 |
|
|
stompedRets,
|
57 |
|
|
panic
|
58 |
|
|
);
|
59 |
|
|
parameter AMSB = `AMSB;
|
60 |
|
|
parameter RSTPC = 64'hFFFFFFFFFFFC0100;
|
61 |
|
|
parameter TRUE = 1'b1;
|
62 |
|
|
parameter FALSE = 1'b0;
|
63 |
|
|
input rst;
|
64 |
|
|
input clk4x;
|
65 |
|
|
input clk;
|
66 |
|
|
input fcu_clk;
|
67 |
|
|
input cs_i;
|
68 |
|
|
input cyc_i;
|
69 |
|
|
input stb_i;
|
70 |
|
|
output ack_o;
|
71 |
|
|
input we_i;
|
72 |
|
|
input [15:0] adr_i;
|
73 |
|
|
input [55:0] dat_i;
|
74 |
|
|
input [2:0] cmpgrp;
|
75 |
|
|
input freezePC;
|
76 |
|
|
input thread_en;
|
77 |
|
|
input pred_on;
|
78 |
|
|
input [4:0] regLR;
|
79 |
|
|
input [55:0] insn0;
|
80 |
|
|
input phit;
|
81 |
|
|
output threadx;
|
82 |
|
|
input branchmiss;
|
83 |
|
|
input [AMSB:0] misspc;
|
84 |
|
|
input branchmiss_thrd;
|
85 |
|
|
output predict_taken0;
|
86 |
|
|
input predict_takenA;
|
87 |
|
|
input predict_takenB;
|
88 |
|
|
input queued1;
|
89 |
|
|
input queuedNop;
|
90 |
|
|
output reg [AMSB:0] pc0;
|
91 |
|
|
output reg fetchbuf;
|
92 |
|
|
output reg fetchbufA_v;
|
93 |
|
|
output reg fetchbufB_v;
|
94 |
|
|
output fetchbuf0_thrd;
|
95 |
|
|
output reg [47:0] fetchbufA_instr;
|
96 |
|
|
output reg [7:0] fetchbufA_pbyte;
|
97 |
|
|
output reg [47:0] fetchbufB_instr;
|
98 |
|
|
output reg [7:0] fetchbufB_pbyte;
|
99 |
|
|
output reg [AMSB:0] fetchbufA_pc;
|
100 |
|
|
output reg [AMSB:0] fetchbufB_pc;
|
101 |
|
|
output [47:0] fetchbuf0_instr;
|
102 |
|
|
output [AMSB:0] fetchbuf0_pc;
|
103 |
|
|
output [2:0] fetchbuf0_insln;
|
104 |
|
|
output fetchbuf0_v;
|
105 |
|
|
output [7:0] fetchbuf0_pbyte;
|
106 |
|
|
input [55:0] codebuf0;
|
107 |
|
|
input [AMSB:0] btgtA;
|
108 |
|
|
input [AMSB:0] btgtB;
|
109 |
|
|
input [3:0] nop_fetchbuf;
|
110 |
|
|
output take_branch0;
|
111 |
|
|
input [3:0] stompedRets;
|
112 |
|
|
output reg [3:0] panic;
|
113 |
|
|
integer n;
|
114 |
|
|
|
115 |
|
|
reg [55:0] cinsn0;
|
116 |
|
|
|
117 |
|
|
//`include "FT64_decode.vh"
|
118 |
|
|
|
119 |
|
|
function IsBranch;
|
120 |
|
|
input [47:0] isn;
|
121 |
|
|
casex(isn[`INSTRUCTION_OP])
|
122 |
|
|
`Bcc: IsBranch = TRUE;
|
123 |
|
|
`BBc: IsBranch = TRUE;
|
124 |
|
|
`BEQI: IsBranch = TRUE;
|
125 |
|
|
`BCHK: IsBranch = TRUE;
|
126 |
|
|
default: IsBranch = FALSE;
|
127 |
|
|
endcase
|
128 |
|
|
endfunction
|
129 |
|
|
|
130 |
|
|
function IsJAL;
|
131 |
|
|
input [47:0] isn;
|
132 |
|
|
IsJAL = isn[`INSTRUCTION_OP]==`JAL;
|
133 |
|
|
endfunction
|
134 |
|
|
|
135 |
|
|
function IsJmp;
|
136 |
|
|
input [47:0] isn;
|
137 |
|
|
IsJmp = isn[`INSTRUCTION_OP]==`JMP;
|
138 |
|
|
endfunction
|
139 |
|
|
|
140 |
|
|
function IsCall;
|
141 |
|
|
input [47:0] isn;
|
142 |
|
|
IsCall = isn[`INSTRUCTION_OP]==`CALL;
|
143 |
|
|
endfunction
|
144 |
|
|
|
145 |
|
|
function IsRet;
|
146 |
|
|
input [47:0] isn;
|
147 |
|
|
IsRet = isn[`INSTRUCTION_OP]==`RET;
|
148 |
|
|
endfunction
|
149 |
|
|
|
150 |
|
|
function IsBrk;
|
151 |
|
|
input [47:0] isn;
|
152 |
|
|
IsBrk = isn[`INSTRUCTION_OP]==`BRK;
|
153 |
|
|
endfunction
|
154 |
|
|
|
155 |
|
|
function IsRTI;
|
156 |
|
|
input [47:0] isn;
|
157 |
|
|
IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
|
158 |
|
|
endfunction
|
159 |
|
|
|
160 |
|
|
function [2:0] fnInsLength;
|
161 |
|
|
input [47:0] ins;
|
162 |
|
|
`ifdef SUPPORT_DCI
|
163 |
|
|
if (ins[`INSTRUCTION_OP]==`CMPRSSD)
|
164 |
|
|
fnInsLength = 3'd2 | pred_on;
|
165 |
|
|
else
|
166 |
|
|
`endif
|
167 |
|
|
case(ins[7:6])
|
168 |
|
|
2'd0: fnInsLength = 3'd4 | pred_on;
|
169 |
|
|
2'd1: fnInsLength = 3'd6 | pred_on;
|
170 |
|
|
default: fnInsLength = 3'd2 | pred_on;
|
171 |
|
|
endcase
|
172 |
|
|
endfunction
|
173 |
|
|
|
174 |
|
|
wire [2:0] fetchbufA_inslen;
|
175 |
|
|
wire [2:0] fetchbufB_inslen;
|
176 |
|
|
FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen, pred_on);
|
177 |
|
|
FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen, pred_on);
|
178 |
|
|
|
179 |
|
|
wire [47:0] xinsn0;
|
180 |
|
|
|
181 |
|
|
FT64_iexpander ux1
|
182 |
|
|
(
|
183 |
|
|
.cinstr(pred_on ? insn0[23:8] : insn0[15:0]),
|
184 |
|
|
.expand(xinsn0)
|
185 |
|
|
);
|
186 |
|
|
|
187 |
|
|
|
188 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
189 |
|
|
// Table of decompressed instructions.
|
190 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
191 |
|
|
assign ack_o = cs_i & cyc_i & stb_i;
|
192 |
|
|
`ifdef SUPPORT_DCI
|
193 |
|
|
reg [47:0] DecompressTable [0:2047];
|
194 |
|
|
always @(posedge clk)
|
195 |
|
|
if (cs_i & cyc_i & stb_i & we_i)
|
196 |
|
|
DecompressTable[adr_i[12:3]] <= dat_i[47:0];
|
197 |
|
|
wire [47:0] expand0 = DecompressTable[{cmpgrp,pred_on ? insn0[23:16]:insn0[15:8]}];
|
198 |
|
|
`endif
|
199 |
|
|
|
200 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
201 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
202 |
|
|
|
203 |
|
|
reg thread;
|
204 |
|
|
reg stompedRet;
|
205 |
|
|
reg ret0Counted;
|
206 |
|
|
wire [AMSB:0] retpc0;
|
207 |
|
|
|
208 |
|
|
assign predict_taken0 = (fetchbuf==1'b0) ? ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE})
|
209 |
|
|
: ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE});
|
210 |
|
|
|
211 |
|
|
reg [AMSB:0] branch_pcA;
|
212 |
|
|
reg [AMSB:0] branch_pcB;
|
213 |
|
|
|
214 |
|
|
always @*
|
215 |
|
|
begin
|
216 |
|
|
case(fetchbufA_instr[`INSTRUCTION_OP])
|
217 |
|
|
`RET: branch_pcA = retpc0;
|
218 |
|
|
`JMP,`CALL:
|
219 |
|
|
begin
|
220 |
|
|
branch_pcA[39:0] = fetchbufA_instr[6] ? {fetchbufA_instr[47:8]} : {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
|
221 |
|
|
branch_pcA[63:40] = fetchbufA_pc[63:40];
|
222 |
|
|
end
|
223 |
|
|
`R2: branch_pcA = btgtA; // RTI
|
224 |
|
|
`BRK,`JAL: branch_pcA = btgtA;
|
225 |
|
|
default:
|
226 |
|
|
begin
|
227 |
|
|
branch_pcA[31:8] = fetchbufA_pc[31:8] +
|
228 |
|
|
((fetchbufA_instr[7:6]==2'b01) ? {{5{fetchbufA_instr[47]}},fetchbufA_instr[47:29]} : {{21{fetchbufA_instr[31]}},fetchbufA_instr[31:29]});
|
229 |
|
|
branch_pcA[7:0] = {fetchbufA_instr[28:23],fetchbufA_instr[17:16]};
|
230 |
|
|
branch_pcA[63:32] = fetchbufA_pc[63:32];
|
231 |
|
|
end
|
232 |
|
|
endcase
|
233 |
|
|
end
|
234 |
|
|
|
235 |
|
|
always @*
|
236 |
|
|
begin
|
237 |
|
|
case(fetchbufB_instr[`INSTRUCTION_OP])
|
238 |
|
|
`RET: branch_pcB = retpc0;
|
239 |
|
|
`JMP,`CALL:
|
240 |
|
|
begin
|
241 |
|
|
branch_pcB[39:0] = fetchbufB_instr[6] ? {fetchbufB_instr[47:8]} : {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
|
242 |
|
|
branch_pcB[63:40] = fetchbufB_pc[63:40];
|
243 |
|
|
end
|
244 |
|
|
`R2: branch_pcB = btgtB; // RTI
|
245 |
|
|
`BRK,`JAL: branch_pcB = btgtB;
|
246 |
|
|
default:
|
247 |
|
|
begin
|
248 |
|
|
branch_pcB[31:8] = fetchbufB_pc[31:8] +
|
249 |
|
|
((fetchbufB_instr[7:6]==2'b01) ? {{5{fetchbufB_instr[47]}},fetchbufB_instr[47:29]} : {{21{fetchbufB_instr[31]}},fetchbufB_instr[31:29]});
|
250 |
|
|
branch_pcB[7:0] = {fetchbufB_instr[28:23],fetchbufB_instr[17:16]};
|
251 |
|
|
branch_pcB[63:32] = fetchbufB_pc[63:32];
|
252 |
|
|
end
|
253 |
|
|
endcase
|
254 |
|
|
end
|
255 |
|
|
|
256 |
|
|
wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE}) || ((
|
257 |
|
|
`ifdef FCU_ENH
|
258 |
|
|
IsRet(fetchbufA_instr)
|
259 |
|
|
|| IsRTI(fetchbufA_instr)|| IsBrk(fetchbufA_instr) || IsJAL(fetchbufA_instr) ||
|
260 |
|
|
`endif
|
261 |
|
|
IsJmp(fetchbufA_instr)||IsCall(fetchbufA_instr)) &&
|
262 |
|
|
fetchbufA_v);
|
263 |
|
|
wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE}) || ((
|
264 |
|
|
`ifdef FCU_ENH
|
265 |
|
|
IsRet(fetchbufB_instr)
|
266 |
|
|
|| IsRTI(fetchbufB_instr)|| IsBrk(fetchbufB_instr) || IsJAL(fetchbufB_instr) ||
|
267 |
|
|
`endif
|
268 |
|
|
IsJmp(fetchbufB_instr)||IsCall(fetchbufB_instr)) &&
|
269 |
|
|
fetchbufB_v);
|
270 |
|
|
|
271 |
|
|
wire take_branch = (fetchbuf==1'b0) ? take_branchA : take_branchB;
|
272 |
|
|
assign take_branch0 = take_branch;
|
273 |
|
|
|
274 |
|
|
/*
|
275 |
|
|
always @*
|
276 |
|
|
begin
|
277 |
|
|
pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;
|
278 |
|
|
pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
|
279 |
|
|
end
|
280 |
|
|
*/
|
281 |
|
|
assign threadx = fetchbuf;
|
282 |
|
|
|
283 |
|
|
`ifdef FCU_ENH
|
284 |
|
|
FT64_RSB #(AMSB) ursb1
|
285 |
|
|
(
|
286 |
|
|
.rst(rst),
|
287 |
|
|
.clk(fcu_clk),
|
288 |
|
|
.regLR(regLR),
|
289 |
|
|
.queued1(queued1),
|
290 |
|
|
.queued2(1'b0),
|
291 |
|
|
.fetchbuf0_v(fetchbuf0_v),
|
292 |
|
|
.fetchbuf0_pc(fetchbuf0_pc),
|
293 |
|
|
.fetchbuf0_instr(fetchbuf0_instr),
|
294 |
|
|
.fetchbuf1_v(1'b0),
|
295 |
|
|
.fetchbuf1_pc(RSTPC),
|
296 |
|
|
.fetchbuf1_instr(`NOP_INSN),
|
297 |
|
|
.stompedRets(stompedRets),
|
298 |
|
|
.stompedRet(stompedRet),
|
299 |
|
|
.pc(retpc0)
|
300 |
|
|
);
|
301 |
|
|
|
302 |
|
|
`else
|
303 |
|
|
assign retpc0 = RSTPC;
|
304 |
|
|
assign retpc1 = RSTPC;
|
305 |
|
|
`endif
|
306 |
|
|
|
307 |
|
|
wire peclk, neclk;
|
308 |
|
|
edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
|
309 |
|
|
|
310 |
|
|
reg did_branch;
|
311 |
|
|
|
312 |
|
|
always @(posedge clk)
|
313 |
|
|
if (rst) begin
|
314 |
|
|
pc0 <= RSTPC;
|
315 |
|
|
fetchbufA_v <= 1'b0;
|
316 |
|
|
fetchbufB_v <= 1'b0;
|
317 |
|
|
fetchbuf <= 1'b0;
|
318 |
|
|
panic <= `PANIC_NONE;
|
319 |
|
|
did_branch <= 1'b0;
|
320 |
|
|
end
|
321 |
|
|
else begin
|
322 |
|
|
|
323 |
|
|
did_branch <= take_branch & ~branchmiss;
|
324 |
|
|
|
325 |
|
|
begin
|
326 |
|
|
|
327 |
|
|
// On a branch miss with threading enabled all fectch buffers are
|
328 |
|
|
// invalidated even though the data in the fetch buffer would be valid
|
329 |
|
|
// for the thread that isn't in a branchmiss state. This is done to
|
330 |
|
|
// keep things simple. For the thread that doesn't miss the current
|
331 |
|
|
// data for the fetch buffer needs to be retrieved again, so the pc
|
332 |
|
|
// for that thread is assigned the current fetchbuf pc.
|
333 |
|
|
// For the thread that misses the pc is simply assigned the misspc.
|
334 |
|
|
if (branchmiss) begin
|
335 |
|
|
pc0 <= misspc;
|
336 |
|
|
fetchbufA_v <= `INV;
|
337 |
|
|
fetchbufB_v <= `INV;
|
338 |
|
|
fetchbuf <= 1'b0;
|
339 |
|
|
$display("********************");
|
340 |
|
|
$display("********************");
|
341 |
|
|
$display("********************");
|
342 |
|
|
$display("Branch miss");
|
343 |
|
|
$display("misspc=%h", misspc);
|
344 |
|
|
$display("********************");
|
345 |
|
|
$display("********************");
|
346 |
|
|
$display("********************");
|
347 |
|
|
end
|
348 |
|
|
// else if (cinsn0[`INSTRUCTION_OP]==`CALL || cinsn0[`INSTRUCTION_OP]==`JMP) begin
|
349 |
|
|
// pc0[31:0] = cinsn0[6] ? {cinsn0[47:8]} : {pc0[31:24],cinsn0[31:8]};
|
350 |
|
|
// fetchbufA_v <= `INV;
|
351 |
|
|
// fetchbufB_v <= `INV;
|
352 |
|
|
// fetchbuf <= 1'b0;
|
353 |
|
|
// end
|
354 |
|
|
else if (take_branch) begin
|
355 |
|
|
if (fetchbuf == 1'b0) begin
|
356 |
|
|
// In this case fetchbufA must be valid, or take_branch wouldn't be.
|
357 |
|
|
case(fetchbufB_v)
|
358 |
|
|
1'b0:
|
359 |
|
|
begin
|
360 |
|
|
pc0 <= branch_pcA;
|
361 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
362 |
|
|
fetchbuf <= (queued1|queuedNop);
|
363 |
|
|
end
|
364 |
|
|
1'b1:
|
365 |
|
|
if (did_branch) begin
|
366 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
367 |
|
|
fetchbuf <= (queued1|queuedNop);
|
368 |
|
|
FetchB();
|
369 |
|
|
end
|
370 |
|
|
else
|
371 |
|
|
begin
|
372 |
|
|
pc0 <= branch_pcA;
|
373 |
|
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
374 |
|
|
fetchbufB_v <= `INV;
|
375 |
|
|
fetchbuf <= (queued1|queuedNop);
|
376 |
|
|
end
|
377 |
|
|
endcase
|
378 |
|
|
end
|
379 |
|
|
else begin
|
380 |
|
|
case(fetchbufA_v)
|
381 |
|
|
1'b0:
|
382 |
|
|
begin
|
383 |
|
|
pc0 <= branch_pcB;
|
384 |
|
|
fetchbufB_v <= !(queued1|queuedNop);
|
385 |
|
|
fetchbuf <= !(queued1|queuedNop);
|
386 |
|
|
end
|
387 |
|
|
1'b1:
|
388 |
|
|
if (did_branch) begin
|
389 |
|
|
fetchbufB_v <= !(queued1|queuedNop);
|
390 |
|
|
fetchbuf <= ~(queued1|queuedNop);
|
391 |
|
|
FetchA();
|
392 |
|
|
end
|
393 |
|
|
else
|
394 |
|
|
begin
|
395 |
|
|
pc0 <= branch_pcB;
|
396 |
|
|
fetchbufB_v <= !(queued1|queuedNop);
|
397 |
|
|
fetchbufA_v <= `INV;
|
398 |
|
|
fetchbuf <= !(queued1|queuedNop);
|
399 |
|
|
end
|
400 |
|
|
endcase
|
401 |
|
|
end
|
402 |
|
|
end // if branch
|
403 |
|
|
|
404 |
|
|
else begin // there is no branchback in the system
|
405 |
|
|
// update fetchbufX_v and fetchbuf ... relatively simple, as
|
406 |
|
|
// there are no backwards branches in the mix
|
407 |
|
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, (queued1|queuedNop)})
|
408 |
|
|
2'b00: ; // do nothing
|
409 |
|
|
2'b10: ;
|
410 |
|
|
2'b11: begin fetchbufA_v <= `INV; fetchbuf <= ~fetchbuf; end
|
411 |
|
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
412 |
|
|
endcase
|
413 |
|
|
else case ({fetchbufB_v, (queued1|queuedNop)})
|
414 |
|
|
2'b00: ; // do nothing
|
415 |
|
|
2'b10: ;
|
416 |
|
|
2'b11: begin fetchbufB_v <= `INV; fetchbuf <= ~fetchbuf; end
|
417 |
|
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
418 |
|
|
endcase
|
419 |
|
|
//
|
420 |
|
|
// get data iff the fetch buffers are empty
|
421 |
|
|
//
|
422 |
|
|
if (fetchbufA_v == `INV) begin
|
423 |
|
|
FetchA();
|
424 |
|
|
// fetchbuf steering logic correction
|
425 |
|
|
if (fetchbufB_v==`INV && phit)
|
426 |
|
|
fetchbuf <= 1'b0;
|
427 |
|
|
end
|
428 |
|
|
else if (fetchbufB_v == `INV) begin
|
429 |
|
|
FetchB();
|
430 |
|
|
end
|
431 |
|
|
end
|
432 |
|
|
//
|
433 |
|
|
// get data iff the fetch buffers are empty
|
434 |
|
|
//
|
435 |
|
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
|
436 |
|
|
FetchA();
|
437 |
|
|
fetchbuf <= 1'b0;
|
438 |
|
|
end
|
439 |
|
|
// // Steer fetchbuf to the valid buffer.
|
440 |
|
|
// else if (fetchbufB_v == `INV)
|
441 |
|
|
// fetchbuf <= 1'b0;
|
442 |
|
|
// else if (fetchbufA_v == `INV)
|
443 |
|
|
// fetchbuf <= 1'b1;
|
444 |
|
|
// else if (fetchbufA_v == `INV) begin
|
445 |
|
|
// FetchA();
|
446 |
|
|
// end
|
447 |
|
|
// else if (fetchbufB_v == `INV) begin
|
448 |
|
|
// FetchB();
|
449 |
|
|
// end
|
450 |
|
|
end
|
451 |
|
|
|
452 |
|
|
// The fetchbuffer is invalidated at the end of a vector instruction
|
453 |
|
|
// queue.
|
454 |
|
|
if (nop_fetchbuf[0]) fetchbufA_v <= `INV;
|
455 |
|
|
if (nop_fetchbuf[1]) fetchbufB_v <= `INV;
|
456 |
|
|
end
|
457 |
|
|
|
458 |
|
|
assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufB_instr;
|
459 |
|
|
assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufB_inslen;
|
460 |
|
|
assign fetchbuf0_v = (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufB_v ;
|
461 |
|
|
assign fetchbuf0_pc = (fetchbuf == 1'b0) ? fetchbufA_pc : fetchbufB_pc ;
|
462 |
|
|
assign fetchbuf0_thrd = 1'b0;
|
463 |
|
|
assign fetchbuf0_pbyte = (fetchbuf == 1'b0) ? fetchbufA_pbyte : fetchbufB_pbyte;
|
464 |
|
|
|
465 |
|
|
reg [2:0] insln0;
|
466 |
|
|
always @*
|
467 |
|
|
begin
|
468 |
|
|
`ifdef SUPPORT_DCI
|
469 |
|
|
if (insn0[5:0]==`CMPRSSD)
|
470 |
|
|
insln0 <= 3'd2 | pred_on;
|
471 |
|
|
else
|
472 |
|
|
`endif
|
473 |
|
|
if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
|
474 |
|
|
insln0 <= fnInsLength(codebuf0);
|
475 |
|
|
else
|
476 |
|
|
insln0 <= fnInsLength(insn0);
|
477 |
|
|
end
|
478 |
|
|
|
479 |
|
|
|
480 |
|
|
always @*
|
481 |
|
|
begin
|
482 |
|
|
`ifdef SUPPORT_DCI
|
483 |
|
|
if (insn0[13:8]==`CMPRSSD && pred_on)
|
484 |
|
|
cinsn0 <= expand0;
|
485 |
|
|
else if (insn0[5:0]==`CMPRSSD && !pred_on)
|
486 |
|
|
cinsn0 <= expand0;
|
487 |
|
|
else
|
488 |
|
|
`endif
|
489 |
|
|
if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC && !pred_on)
|
490 |
|
|
cinsn0 <= codebuf0;
|
491 |
|
|
else if (insn0[15:14]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC && pred_on)
|
492 |
|
|
cinsn0 <= codebuf0;
|
493 |
|
|
else if (insn0[15] & pred_on)
|
494 |
|
|
cinsn0 <= {xinsn0,insn0[7:0]};
|
495 |
|
|
else if (insn0[7] & ~pred_on)
|
496 |
|
|
cinsn0 <= xinsn0;
|
497 |
|
|
else
|
498 |
|
|
cinsn0 <= insn0;
|
499 |
|
|
end
|
500 |
|
|
|
501 |
|
|
task FetchA;
|
502 |
|
|
begin
|
503 |
|
|
fetchbufA_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
|
504 |
|
|
fetchbufA_pbyte = cinsn0[7:0];
|
505 |
|
|
fetchbufA_v <= `VAL;
|
506 |
|
|
fetchbufA_pc <= pc0;
|
507 |
|
|
if (phit && ~freezePC)
|
508 |
|
|
pc0 <= pc0 + insln0;
|
509 |
|
|
else
|
510 |
|
|
pc0 <= pc0;
|
511 |
|
|
end
|
512 |
|
|
endtask
|
513 |
|
|
|
514 |
|
|
task FetchB;
|
515 |
|
|
begin
|
516 |
|
|
fetchbufB_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
|
517 |
|
|
fetchbufB_pbyte = cinsn0[7:0];
|
518 |
|
|
fetchbufB_v <= `VAL;
|
519 |
|
|
fetchbufB_pc <= pc0;
|
520 |
|
|
if (phit && ~freezePC)
|
521 |
|
|
pc0 <= pc0 + insln0;
|
522 |
|
|
else
|
523 |
|
|
pc0 <= pc0;
|
524 |
|
|
end
|
525 |
|
|
endtask
|
526 |
|
|
|
527 |
|
|
endmodule
|