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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2012-2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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module bootrom(rst_i, clk_i, cti_i, cyc_i, stb_i, ack_o, adr_i, dat_o, perr);
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parameter DBW=64;
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parameter MAGIC1=32'hAAAAAAAA;
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parameter MAGIC2=32'h55555555;
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input rst_i;
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input clk_i;
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input [2:0] cti_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input [31:0] adr_i;
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output [DBW-1:0] dat_o;
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reg [DBW-1:0] dat_o;
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output perr;
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reg perr;
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wire ne_cs;
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wire cs;
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reg ack0,ack1,ack2,ack3;
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always @(posedge clk_i)
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begin
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if (ne_cs)
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ack0 <= cs;
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else if (!cs)
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ack0 <= 1'b0;
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ack1 <= ack0 & cs;
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ack2 <= ack1 & cs;
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ack3 <= ack2 & cs;
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end
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assign cs = cyc_i && stb_i && adr_i[31:16]==16'hFFFF;
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assign ack_o = cs & ack0;
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reg [DBW:0] rommem0 [0:8191];
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reg [DBW:0] rommem1 [0:8191];
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reg [DBW:0] rommem2 [0:8191];
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initial begin
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if (DBW==32) begin
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`include "..\..\software\A64\bin\boot.ve0"
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`include "..\..\software\A64\bin\boot.ve1"
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`include "..\..\software\A64\bin\boot.ve2"
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end
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else begin
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`include "..\..\software\a64\bin\boot.ve0"
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`include "..\..\software\A64\bin\boot.ve1"
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`include "..\..\software\A64\bin\boot.ve2"
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end
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end
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wire pe_cs;
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edge_det u1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee());
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edge_det u2 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(pe_cs), .pe(), .ne(ne_cs), .ee());
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reg [14:2] radr;
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reg [14:2] ctr;
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always @(posedge clk_i)
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if (pe_cs) begin
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if (DBW==32)
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ctr <= adr_i[14:2] + 13'd1;
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else
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ctr <= adr_i[14:3] + 13'd1;
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end
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else if (cs)
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ctr <= ctr + 13'd1;
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always @(posedge clk_i)
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if (DBW==32)
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radr <= pe_cs ? adr_i[14:2] : ctr;
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else
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radr <= pe_cs ? adr_i[14:3] : ctr;
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wire [31:0] d0 = rommem0[radr][DBW-1:0];
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wire [31:0] d1 = rommem1[radr][DBW-1:0]^MAGIC1;
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wire [31:0] d2 = rommem2[radr][DBW-1:0]^MAGIC2;
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wire [31:0] d4 = (d0&d1)|(d0&d2)|(d1&d2);
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always @(posedge clk_i)
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if (cs) begin
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dat_o <= d4;
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$display("br read: %h %h", radr,d4);
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end
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else
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dat_o <= {DBW{1'b0}};
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always @(posedge clk_i)
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if (cs)
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perr <= ^rommem0[radr][DBW-1:0]!=rommem0[radr][DBW];
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else
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perr <= 1'd0;
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endmodule
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