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[/] [thor/] [trunk/] [bench/] [scratchmem.v] - Blame information for rev 2

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1 2 robfinch 
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2012-2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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module scratchmem(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o);
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parameter DBW=64;
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input rst_i;
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input clk_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input we_i;
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input [DBW/8-1:0] sel_i;
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input [DBW-1:0] adr_i;
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input [DBW-1:0] dat_i;
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output [DBW-1:0] dat_o;
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reg [DBW-1:0] dat_o;
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integer n;
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reg [7:0] smemA [2047:0];
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reg [7:0] smemB [2047:0];
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reg [7:0] smemC [2047:0];
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reg [7:0] smemD [2047:0];
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generate
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begin
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if (DBW==64) begin
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        reg [7:0] smemE [2047:0];
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        reg [7:0] smemF [2047:0];
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        reg [7:0] smemG [2047:0];
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        reg [7:0] smemH [2047:0];
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        initial begin
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        for (n = 0; n < 2048; n = n + 1)
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        begin
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                smemA[n] = 0;
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                smemB[n] = 0;
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                smemC[n] = 0;
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                smemD[n] = 0;
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                smemE[n] = 0;
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                smemF[n] = 0;
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                smemG[n] = 0;
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                smemH[n] = 0;
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        end
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        end
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end
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else begin
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        initial begin
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        for (n = 0; n < 2048; n = n + 1)
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        begin
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                smemA[n] = 0;
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                smemB[n] = 0;
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                smemC[n] = 0;
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                smemD[n] = 0;
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        end
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        end
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end
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end
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endgenerate
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reg [13:3] radr;
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wire cs = cyc_i && stb_i && adr_i[59:16]==44'h0000;
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reg rdy,rdy1;
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always @(posedge clk_i)
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begin
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        rdy1 <= cs;
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        rdy <= rdy1 & cs;
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end
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assign ack_o = cs ? (we_i ? 1'b1 : rdy) : 1'b0;
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always @(posedge clk_i)
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        if (cs & we_i)
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                $display ("wrote to scratchmem: %h=%h", adr_i, dat_i);
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generate
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begin
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if (DBW==64) begin
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[0])
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                smemA[adr_i[13:3]] <= dat_i[7:0];
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[1])
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                smemB[adr_i[13:3]] <= dat_i[15:8];
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[2])
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                smemC[adr_i[13:3]] <= dat_i[23:16];
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[3])
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                smemD[adr_i[13:3]] <= dat_i[31:24];
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//always @(posedge clk_i)
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//      if (cs & we_i & sel_i[4])
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//              smemE[adr_i[13:3]] <= dat_i[39:32];
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//always @(posedge clk_i)
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//      if (cs & we_i & sel_i[5])
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//              smemF[adr_i[13:3]] <= dat_i[47:40];
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//always @(posedge clk_i)
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//      if (cs & we_i & sel_i[6])
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//              smemG[adr_i[13:3]] <= dat_i[55:48];
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//always @(posedge clk_i)
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//      if (cs & we_i & sel_i[7])
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//              smemH[adr_i[13:3]] <= dat_i[63:56];
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end
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else begin
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[0])
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                smemA[adr_i[12:2]] <= dat_i[7:0];
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[1])
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                smemB[adr_i[12:2]] <= dat_i[15:8];
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[2])
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                smemC[adr_i[12:2]] <= dat_i[23:16];
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always @(posedge clk_i)
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        if (cs & we_i & sel_i[3])
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                smemD[adr_i[12:2]] <= dat_i[31:24];
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end
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end
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endgenerate
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wire pe_cs;
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edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee() );
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reg [13:3] ctr;
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always @(posedge clk_i)
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        if (pe_cs) begin
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                if (DBW==64)
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                        ctr <= adr_i[13:3] + 12'd1;
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                else
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                        ctr <= adr_i[12:2] + 12'd1;
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        end
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        else if (cs)
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                ctr <= ctr + 12'd1;
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always @(posedge clk_i)
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        if (DBW==64)
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                radr <= pe_cs ? adr_i[13:3] : ctr;
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        else
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                radr <= pe_cs ? adr_i[12:2] : ctr;
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//assign dat_o = cs ? {smemH[radr],smemG[radr],smemF[radr],smemE[radr],
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//                              smemD[radr],smemC[radr],smemB[radr],smemA[radr]} : 64'd0;
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always @(posedge clk_i)
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if (cs) begin
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//      if (DBW==64)
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//              dat_o <= {smemH[radr],smemG[radr],smemF[radr],smemE[radr],
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//                                      smemD[radr],smemC[radr],smemB[radr],smemA[radr]};
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//      else
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                dat_o <= {smemD[radr],smemC[radr],smemB[radr],smemA[radr]};
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//      if (!we_i)
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//              $display("read from scratchmem: %h=%h", radr, {smemH[radr],smemG[radr],smemF[radr],smemE[radr],
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//                              smemD[radr],smemC[radr],smemB[radr],smemA[radr]});
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end
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else
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        dat_o <= {DBW{1'd0}};
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endmodule

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