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//

//      COPYRIGHT 2000 by Bruce L. Jacob

//      (contact info: http://www.ece.umd.edu/~blj/)

//

//      You are welcome to use, modify, copy, and/or redistribute this implementation, provided:

//        1. you share with the author (Bruce Jacob) any changes you make;

//        2. you properly credit the author (Bruce Jacob) if used within a larger work; and

//        3. you do not modify, delete, or in any way obscure the implementation's copyright 

//           notice or following comments (i.e. the first 3-4 dozen lines of this file).

//

//      RiSC-16

//

//      This is an out-of-order implementation of the RiSC-16, a teaching instruction-set used by

//      the author at the University of Maryland, and which is a blatant (but sanctioned) rip-off

//      of the Little Computer (LC-896) developed by Peter Chen at the University of Michigan.

//      The primary differences include the following:

//        1. a move from 17-bit to 16-bit instructions; and

//        2. the replacement of the NOP and HALT opcodes by ADDI and LUI ... HALT and NOP are

//           now simply special instances of other instructions: NOP is a do-nothing ADD, and

//           HALT is a subset of JALR.

//

//      RiSC stands for Ridiculously Simple Computer, which makes sense in the context in which

//      the instruction-set is normally used -- to teach simple organization and architecture to

//      undergraduates who do not yet know how computers work.  This implementation was targetted

//      towards more advanced undergraduates doing design & implementation and was intended to 

//      demonstrate some high-performance concepts on a small scale -- an 8-entry reorder buffer,

//      eight opcodes, two ALUs, two-way issue, two-way commit, etc.  However, the out-of-order 

//      core is much more complex than I anticipated, and I hope that its complexity does not 

//      obscure its underlying structure.  We'll see how well it flies in class ...

//

//      CAVEAT FREELOADER: This Verilog implementation was developed and debugged in a (somewhat

//      frantic) 2-week period before the start of the Fall 2000 semester.  Not surprisingly, it

//      still contains many bugs and some horrible, horrible logic.  The logic is also written so

//      as to be debuggable and/or explain its function, rather than to be efficient -- e.g. in

//      several places, signals are over-constrained so that they are easy to read in the debug

//      output ... also, you will see statements like

//

//          if (xyz[`INSTRUCTION_OP] == `BEQ || xyz[`INSTRUCTION_OP] == `SW)

//

//      instead of and/nand combinations of bits ... sorry; can't be helped.  Use at your own risk.

//

//      DOCUMENTATION: Documents describing the RiSC-16 in all its forms (sequential, pipelined,

//      as well as out-of-order) can be found on the author's website at the following URL:

//

//          http://www.ece.umd.edu/~blj/RiSC/

//

//      If you do not find what you are looking for, please feel free to email me with suggestions

//      for more/different/modified documents.  Same goes for bug fixes.

//

//

//      KNOWN PROBLEMS (i.e., bugs I haven't got around to fixing yet)

//

//      - If the target of a backwards branch is a backwards branch, the fetchbuf steering logic

//        will get confused.  This can be fixed by having a separate did_branchback status register

//        for each of the fetch buffers.

//

// ============================================================================

//        __

//   \\__/ o\    (C) 2013,2015  Robert Finch, Stratford

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@finitron.ca

//       ||

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//

//

// Thor Superscaler

//

// This work is starting with the RiSC-16 as noted in the copyright statement

// above. Hopefully it will be possible to run this processor in real hardware

// (FPGA) as opposed to just simulation. To the RiSC-16 are added:

//

//      64/32 bit datapath rather than 16 bit

//   64 general purpose registers

//   16 code address registers

//   16 predicate registers / predicated instruction execution

//    8 segment registers

//      A branch history table, and a (2,2) correlating branch predictor added

//      variable length instruction encodings (code density)

//      support for interrupts

//      The instruction set is changed completely with many new instructions.

//      An instruction and data cache were added.

//      A WISHBONE bus interface was added,

//

// 52,635 (84,500 LC's)

// with segmentation

// no bitfield, stack or FP ops

//

// ============================================================================

//

`include "Thor_defines.v"

module Thor(corenum, rst_i, clk_i, clk_o, km, nmi_i, irq_i, vec_i, bte_o, cti_o, bl_o, lock_o, resv_o, resv_i, cres_o,

    cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);

parameter DBW = 32;         // databus width

parameter ABW = 32;         // address bus width

parameter RSTADDR = 64'hFFFFFFFFFFFFEFF0;

localparam AMSB = ABW-1;

parameter QENTRIES = 8;

parameter ALU1BIG = 0;

parameter RESET1 = 4'd0;

parameter RESET2 = 4'd1;

parameter IDLE = 4'd2;

parameter ICACHE1 = 4'd3;

parameter DCACHE1 = 4'd4;

parameter IBUF1 = 4'd5;

parameter IBUF2 = 4'd6;

parameter IBUF3 = 4'd7;

parameter IBUF4 = 4'd8;

parameter IBUF5 = 4'd9;

parameter NREGS = 127;

parameter PF = 4'd0;

parameter PT = 4'd1;

parameter PEQ = 4'd2;

parameter PNE = 4'd3;

parameter PLE = 4'd4;

parameter PGT = 4'd5;

parameter PGE = 4'd6;

parameter PLT = 4'd7;

parameter PLEU = 4'd8;

parameter PGTU = 4'd9;

parameter PGEU = 4'd10;

parameter PLTU = 4'd11;

input [63:0] corenum;

input rst_i;

input clk_i;

output clk_o;

output km;

input nmi_i;

input irq_i;

input [7:0] vec_i;

output reg [1:0] bte_o;

output reg [2:0] cti_o;

output reg [4:0] bl_o;

output reg lock_o;

output reg resv_o;

input resv_i;

output reg cres_o;

output reg cyc_o;

output reg stb_o;

input ack_i;

input err_i;

output reg we_o;

output reg [DBW/8-1:0] sel_o;

output reg [ABW-1:0] adr_o;

input [DBW-1:0] dat_i;

output reg [DBW-1:0] dat_o;

integer n,i;

reg [DBW/8-1:0] rsel;

reg [3:0] cstate;

reg [ABW+3:0] pc;                                // program counter (virtual)

wire [DBW-1:0] ppc;                              // physical pc address

reg [ABW-1:0] interrupt_pc;     // working register for interrupt pc

reg [DBW-1:0] vadr;                              // data virtual address

reg [3:0] panic;         // indexes the message structure

reg [128:0] message [0:15];       // indexed by panic

reg [DBW-1:0] cregs [0:15];               // code address registers

reg [ 3:0] pregs [0:15];          // predicate registers

`ifdef SEGMENTATION

reg [DBW-1:12] sregs [0:7];              // segment registers

reg [DBW-1:12] sregs_lmt [0:7];

`endif

reg [2:0] rrmapno;                               // register rename map number

wire ITLBMiss;

wire DTLBMiss;

wire uncached;

wire [DBW-1:0] cdat;

reg pwe;

wire [DBW-1:0] pea;

reg [DBW-1:0] tick;

reg [DBW-1:0] lc;                                // loop counter

reg [DBW-1:0] rfoa0,rfoa1;

reg [DBW-1:0] rfob0,rfob1;

reg [DBW-1:0] rfoc0,rfoc1;

reg [DBW-1:0] rfot0,rfot1;

reg ic_invalidate,dc_invalidate;

reg ic_invalidate_line,dc_invalidate_line;

reg [ABW-1:0] ic_lineno,dc_lineno;

reg ierr,derr;                                  // err_i during icache load

wire insnerr;                                   // err_i during icache load

wire [127:0] insn;

wire iuncached;

reg [NREGS:0] rf_v;

//reg [15:0] pf_v;

reg im,imb;

reg fxe;

reg nmi1,nmi_edge;

reg StatusHWI;

reg [7:0] StatusEXL;

assign km = StatusHWI | |StatusEXL;

reg [7:0] GM;            // register group mask

reg [7:0] GMB;

wire [63:0] sr = {32'd0,imb,7'b0,GMB,im,1'b0,km,fxe,4'b0,GM};

wire int_commit;

wire int_pending;

wire sys_commit;

`ifdef SEGMENTATION

wire [DBW-1:0] spc = (pc[ABW+3:ABW]==4'hF) ? pc[ABW-1:0] :

                     (pc[ABW-1:ABW-4]==4'hF) ? pc[ABW-1:0] : {sregs[7],12'h000} + pc[ABW-1:0];

`else

wire [DBW-1:0] spc = pc;

`endif

wire [DBW-1:0] ppcp16 = ppc + 64'd16;

reg [DBW-1:0] string_pc;

reg stmv_flag;

reg [7:0] asid;

wire clk;

// Operand registers

wire take_branch;

wire take_branch0;

wire take_branch1;

reg [3:0] rf_source [0:NREGS];

//reg [3:0] pf_source [15:0];

// instruction queue (ROB)

reg iq_cmt[0:7];

reg [7:0]  iqentry_v;                    // entry valid?  -- this should be the first bit

reg        iqentry_out  [0:7];   // instruction has been issued to an ALU ... 

reg        iqentry_done [0:7];   // instruction result valid

reg [7:0]  iqentry_cmt;                  // commit result to machine state

reg        iqentry_bt   [0:7];   // branch-taken (used only for branches)

reg        iqentry_agen [0:7];  // memory address is generated

reg        iqentry_mem  [0:7];   // touches memory: 1 if LW/SW

reg        iqentry_jmp  [0:7];   // changes control flow: 1 if BEQ/JALR

reg        iqentry_fp   [0:7];  // is an floating point operation

reg        iqentry_rfw  [0:7];   // writes to register file

reg [DBW-1:0] iqentry_res        [0:7];   // instruction result

reg  [3:0] iqentry_insnsz [0:7];  // the size of the instruction

reg  [3:0] iqentry_cond [0:7];    // predicating condition

reg  [3:0] iqentry_pred [0:7];    // predicate value

reg        iqentry_p_v  [0:7];   // predicate is valid

reg  [3:0] iqentry_p_s  [0:7];    // predicate source

reg  [7:0] iqentry_op    [0:7];   // instruction opcode

reg  [5:0] iqentry_fn   [0:7];  // instruction function

reg  [2:0] iqentry_renmapno [0:7];        // register rename map number

reg  [6:0] iqentry_tgt   [0:7];   // Rt field or ZERO -- this is the instruction's target (if any)

reg [DBW-1:0] iqentry_a0 [0:7];   // argument 0 (immediate)

reg [DBW-1:0] iqentry_a1 [0:7];   // argument 1

reg        iqentry_a1_v [0:7];   // arg1 valid

reg  [3:0] iqentry_a1_s  [0:7];   // arg1 source (iq entry # with top bit representing ALU/DRAM bus)

reg [DBW-1:0] iqentry_a2 [0:7];   // argument 2

reg        iqentry_a2_v [0:7];   // arg2 valid

reg  [3:0] iqentry_a2_s  [0:7];   // arg2 source (iq entry # with top bit representing ALU/DRAM bus)

reg [DBW-1:0] iqentry_a3 [0:7];   // argument 3

reg        iqentry_a3_v [0:7];   // arg3 valid

reg  [3:0] iqentry_a3_s  [0:7];   // arg3 source (iq entry # with top bit representing ALU/DRAM bus)

reg [DBW-1:0] iqentry_T [0:7];

reg        iqentry_T_v [0:7];

reg  [3:0] iqentry_T_s [0:7];

reg [DBW-1:0] iqentry_pc [0:7];   // program counter for this instruction

wire  iqentry_source [0:7];

wire  iqentry_imm [0:7];

wire  iqentry_memready [0:7];

wire  iqentry_memopsvalid [0:7];

reg qstomp;

wire stomp_all;

reg  [7:0] iqentry_fpissue;

reg  [7:0] iqentry_memissue;

wire iqentry_memissue_head0;

wire iqentry_memissue_head1;

wire iqentry_memissue_head2;

wire iqentry_memissue_head3;

wire iqentry_memissue_head4;

wire iqentry_memissue_head5;

wire iqentry_memissue_head6;

wire iqentry_memissue_head7;

wire  [7:0] iqentry_stomp;

reg  [7:0] iqentry_issue;

wire  [1:0] iqentry_0_islot;

wire  [1:0] iqentry_1_islot;

wire  [1:0] iqentry_2_islot;

wire  [1:0] iqentry_3_islot;

wire  [1:0] iqentry_4_islot;

wire  [1:0] iqentry_5_islot;

wire  [1:0] iqentry_6_islot;

wire  [1:0] iqentry_7_islot;

reg  [1:0] iqentry_islot[0:7];

reg [1:0] iqentry_fpislot[0:7];

reg queued1,queued2;

reg queued3;    // for three-way config

reg allowq;

wire  [NREGS:1] livetarget;

wire  [NREGS:1] iqentry_0_livetarget;

wire  [NREGS:1] iqentry_1_livetarget;

wire  [NREGS:1] iqentry_2_livetarget;

wire  [NREGS:1] iqentry_3_livetarget;

wire  [NREGS:1] iqentry_4_livetarget;

wire  [NREGS:1] iqentry_5_livetarget;

wire  [NREGS:1] iqentry_6_livetarget;

wire  [NREGS:1] iqentry_7_livetarget;

wire  [NREGS:1] iqentry_0_latestID;

wire  [NREGS:1] iqentry_1_latestID;

wire  [NREGS:1] iqentry_2_latestID;

wire  [NREGS:1] iqentry_3_latestID;

wire  [NREGS:1] iqentry_4_latestID;

wire  [NREGS:1] iqentry_5_latestID;

wire  [NREGS:1] iqentry_6_latestID;

wire  [NREGS:1] iqentry_7_latestID;

wire  [NREGS:1] iqentry_0_cumulative;

wire  [NREGS:1] iqentry_1_cumulative;

wire  [NREGS:1] iqentry_2_cumulative;

wire  [NREGS:1] iqentry_3_cumulative;

wire  [NREGS:1] iqentry_4_cumulative;

wire  [NREGS:1] iqentry_5_cumulative;

wire  [NREGS:1] iqentry_6_cumulative;

wire  [NREGS:1] iqentry_7_cumulative;

reg  [2:0] tail0;

reg  [2:0] tail1;

reg  [2:0] tail2;   // used only for three-way config

reg  [2:0] head0;

reg  [2:0] head1;

reg  [2:0] head2;        // used only to determine memory-access ordering

reg  [2:0] head3;        // used only to determine memory-access ordering

reg  [2:0] head4;        // used only to determine memory-access ordering

reg  [2:0] head5;        // used only to determine memory-access ordering

reg  [2:0] head6;        // used only to determine memory-access ordering

reg  [2:0] head7;        // used only to determine memory-access ordering

reg  [2:0] headinc;

wire  [2:0] missid;

reg   fetchbuf;         // determines which pair to read from & write to

reg  [63:0] fetchbuf0_instr;

reg  [DBW-1:0] fetchbuf0_pc;

reg         fetchbuf0_v;

wire        fetchbuf0_mem;

wire        fetchbuf0_jmp;

wire            fetchbuf0_fp;

wire        fetchbuf0_rfw;

wire        fetchbuf0_pfw;

reg  [63:0] fetchbuf1_instr;

reg  [DBW-1:0] fetchbuf1_pc;

reg        fetchbuf1_v;

wire        fetchbuf1_mem;

wire        fetchbuf1_jmp;

wire            fetchbuf1_fp;

wire        fetchbuf1_rfw;

wire        fetchbuf1_pfw;

wire        fetchbuf1_bfw;

reg  [63:0] fetchbuf2_instr;

reg  [DBW-1:0] fetchbuf2_pc;

reg        fetchbuf2_v;

wire        fetchbuf2_mem;

wire        fetchbuf2_jmp;

wire            fetchbuf2_fp;

wire        fetchbuf2_rfw;

wire        fetchbuf2_pfw;

wire        fetchbuf2_bfw;

reg [63:0] fetchbufA_instr;

reg [DBW-1:0] fetchbufA_pc;

reg        fetchbufA_v;

reg [63:0] fetchbufB_instr;

reg [DBW-1:0] fetchbufB_pc;

reg        fetchbufB_v;

reg [63:0] fetchbufC_instr;

reg [DBW-1:0] fetchbufC_pc;

reg        fetchbufC_v;

reg [63:0] fetchbufD_instr;

reg [DBW-1:0] fetchbufD_pc;

reg        fetchbufD_v;

reg        did_branchback;

reg             did_branchback0;

reg                     did_branchback1;

reg        alu0_ld;

reg        alu0_available;

reg        alu0_dataready;

reg  [3:0] alu0_sourceid;

reg  [3:0] alu0_insnsz;

reg  [7:0] alu0_op;

reg  [5:0] alu0_fn;

reg  [3:0] alu0_cond;

reg        alu0_bt;

reg        alu0_cmt;

reg [DBW-1:0] alu0_argA;

reg [DBW-1:0] alu0_argB;

reg [DBW-1:0] alu0_argC;

reg [DBW-1:0] alu0_argT;

reg [DBW-1:0] alu0_argI;

reg  [3:0] alu0_pred;

reg [DBW-1:0] alu0_pc;

reg [DBW-1:0] alu0_bus;

reg  [3:0] alu0_id;

wire  [3:0] alu0_exc;

reg        alu0_v;

wire        alu0_branchmiss;

reg [ABW+3:0] alu0_misspc;

reg        alu1_ld;

reg        alu1_available;

reg        alu1_dataready;

reg  [3:0] alu1_sourceid;

reg  [3:0] alu1_insnsz;

reg  [7:0] alu1_op;

reg  [5:0] alu1_fn;

reg  [3:0] alu1_cond;

reg        alu1_bt;

reg        alu1_cmt;

reg [DBW-1:0] alu1_argA;

reg [DBW-1:0] alu1_argB;

reg [DBW-1:0] alu1_argC;

reg [DBW-1:0] alu1_argT;

reg [DBW-1:0] alu1_argI;

reg  [3:0] alu1_pred;

reg [DBW-1:0] alu1_pc;

reg [DBW-1:0] alu1_bus;

reg  [3:0] alu1_id;

wire  [3:0] alu1_exc;

reg        alu1_v;

wire        alu1_branchmiss;

reg [ABW+3:0] alu1_misspc;

wire mem_stringmiss;

wire        branchmiss;

wire [ABW+3:0] misspc;

`ifdef FLOATING_POINT

reg        fp0_ld;

reg        fp0_available;

reg        fp0_dataready;

reg  [3:0] fp0_sourceid;

reg  [7:0] fp0_op;

reg  [5:0] fp0_fn;

reg  [3:0] fp0_cond;

wire        fp0_cmt;

reg             fp0_done;

reg [DBW-1:0] fp0_argA;

reg [DBW-1:0] fp0_argB;

reg [DBW-1:0] fp0_argC;

reg [DBW-1:0] fp0_argI;

reg  [3:0] fp0_pred;

reg [DBW-1:0] fp0_pc;

wire [DBW-1:0] fp0_bus;

wire  [3:0] fp0_id;

wire  [7:0] fp0_exc;

wire        fp0_v;

`endif

wire        dram_avail;

reg      [2:0] dram0;    // state of the DRAM request (latency = 4; can have three in pipeline)

reg      [2:0] dram1;    // state of the DRAM request (latency = 4; can have three in pipeline)

reg      [2:0] dram2;    // state of the DRAM request (latency = 4; can have three in pipeline)

reg  [2:0] tlb_state;

reg [3:0] tlb_id;

reg [3:0] tlb_op;

reg [3:0] tlb_regno;

reg [8:0] tlb_tgt;

reg [DBW-1:0] tlb_data;

wire [DBW-1:0] tlb_dato;

reg dram0_owns_bus;

reg [DBW-1:0] dram0_data;

reg [DBW-1:0] dram0_datacmp;

reg [DBW-1:0] dram0_addr;

reg [DBW-1:0] dram0_seg;        // value of segment register associated with memory operation

reg [ABW-1:12] dram0_lmt;       // value of segment limit associated with memory operation

reg  [7:0] dram0_op;

reg  [5:0] dram0_fn;

reg  [8:0] dram0_tgt;

reg  [3:0] dram0_id;

reg  [3:0] dram0_exc;

reg dram1_owns_bus;

reg [DBW-1:0] dram1_data;

reg [DBW-1:0] dram1_datacmp;

reg [DBW-1:0] dram1_addr;

reg  [7:0] dram1_op;

reg  [5:0] dram1_fn;

reg  [6:0] dram1_tgt;

reg  [3:0] dram1_id;

reg  [3:0] dram1_exc;

reg [DBW-1:0] dram2_data;

reg [DBW-1:0] dram2_datacmp;

reg [DBW-1:0] dram2_addr;

reg  [7:0] dram2_op;

reg  [5:0] dram2_fn;

reg  [6:0] dram2_tgt;

reg  [3:0] dram2_id;

reg  [3:0] dram2_exc;

reg [DBW-1:0] dram_bus;

reg  [6:0] dram_tgt;

reg  [3:0] dram_id;

reg  [3:0] dram_exc;

reg        dram_v;

reg [DBW-1:0] index;

reg [DBW-1:0] src_addr,dst_addr;

wire mem_issue;

wire        outstanding_stores;

reg [DBW-1:0] I; // instruction count

wire        commit0_v;

wire  [3:0] commit0_id;

wire  [6:0] commit0_tgt;

wire [DBW-1:0] commit0_bus;

wire        commit1_v;

wire  [3:0] commit1_id;

wire  [6:0] commit1_tgt;

wire [DBW-1:0] commit1_bus;

wire limit_cmt;

wire committing2;

wire [63:0] alu0_divq;

wire [63:0] alu0_rem;

wire alu0_div_done;

wire [63:0] alu1_divq;

wire [63:0] alu1_rem;

wire alu1_div_done;

wire [127:0] alu0_prod;

wire alu0_mult_done;

wire [127:0] alu1_prod;

wire alu1_mult_done;

//-----------------------------------------------------------------------------

// Debug

//-----------------------------------------------------------------------------

wire [DBW-1:0] dbg_stat;

reg [DBW-1:0] dbg_ctrl;

reg [ABW-1:0] dbg_adr0;

reg [ABW-1:0] dbg_adr1;

reg [ABW-1:0] dbg_adr2;

reg [ABW-1:0] dbg_adr3;

reg dbg_imatchA0,dbg_imatchA1,dbg_imatchA2,dbg_imatchA3,dbg_imatchA;

reg dbg_imatchB0,dbg_imatchB1,dbg_imatchB2,dbg_imatchB3,dbg_imatchB;

wire dbg_lmatch0 =

                        dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram0_addr[AMSB:3]==dbg_adr0[AMSB:3] &&