| 1 |
3 |
robfinch |
//=============================================================================
|
| 2 |
|
|
// __
|
| 3 |
9 |
robfinch |
// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
|
| 4 |
3 |
robfinch |
// \ __ / All rights reserved.
|
| 5 |
|
|
// \/_// robfinch<remove>@finitron.ca
|
| 6 |
|
|
// ||
|
| 7 |
|
|
//
|
| 8 |
|
|
// Thor_BranchHistory.v
|
| 9 |
|
|
//
|
| 10 |
|
|
//
|
| 11 |
|
|
// This source file is free software: you can redistribute it and/or modify
|
| 12 |
|
|
// it under the terms of the GNU Lesser General Public License as published
|
| 13 |
|
|
// by the Free Software Foundation, either version 3 of the License, or
|
| 14 |
|
|
// (at your option) any later version.
|
| 15 |
|
|
//
|
| 16 |
|
|
// This source file is distributed in the hope that it will be useful,
|
| 17 |
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 18 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 19 |
|
|
// GNU General Public License for more details.
|
| 20 |
|
|
//
|
| 21 |
|
|
// You should have received a copy of the GNU General Public License
|
| 22 |
|
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
| 23 |
|
|
//
|
| 24 |
|
|
//
|
| 25 |
|
|
//=============================================================================
|
| 26 |
|
|
//
|
| 27 |
|
|
module Thor_BranchHistory(rst, clk, advanceX, xisBranch, pc, xpc, takb, predict_taken);
|
| 28 |
|
|
parameter DBW=64;
|
| 29 |
|
|
input rst;
|
| 30 |
|
|
input clk;
|
| 31 |
|
|
input advanceX;
|
| 32 |
|
|
input xisBranch;
|
| 33 |
|
|
input [DBW-1:0] pc;
|
| 34 |
|
|
input [DBW-1:0] xpc;
|
| 35 |
|
|
input takb;
|
| 36 |
|
|
output predict_taken;
|
| 37 |
|
|
|
| 38 |
|
|
integer n;
|
| 39 |
|
|
reg [2:0] gbl_branch_hist;
|
| 40 |
|
|
reg [1:0] branch_history_table [255:0];
|
| 41 |
|
|
// For simulation only, initialize the history table to zeros.
|
| 42 |
|
|
// In the real world we don't care.
|
| 43 |
|
|
initial begin
|
| 44 |
9 |
robfinch |
gbl_branch_hist = 0;
|
| 45 |
3 |
robfinch |
for (n = 0; n < 256; n = n + 1)
|
| 46 |
|
|
branch_history_table[n] = 0;
|
| 47 |
|
|
end
|
| 48 |
|
|
wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]}; // write address
|
| 49 |
|
|
wire [7:0] bht_ra = {pc[7:2],gbl_branch_hist[2:1]}; // read address (IF stage)
|
| 50 |
|
|
wire [1:0] bht_xbits = branch_history_table[bht_wa];
|
| 51 |
|
|
wire [1:0] bht_ibits = branch_history_table[bht_ra];
|
| 52 |
|
|
assign predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
| 53 |
|
|
|
| 54 |
|
|
// Two bit saturating counter
|
| 55 |
|
|
reg [1:0] xbits_new;
|
| 56 |
|
|
always @(takb or bht_xbits)
|
| 57 |
|
|
if (takb) begin
|
| 58 |
|
|
if (bht_xbits != 2'd1)
|
| 59 |
|
|
xbits_new <= bht_xbits + 2'd1;
|
| 60 |
|
|
else
|
| 61 |
|
|
xbits_new <= bht_xbits;
|
| 62 |
|
|
end
|
| 63 |
|
|
else begin
|
| 64 |
|
|
if (bht_xbits != 2'd2)
|
| 65 |
|
|
xbits_new <= bht_xbits - 2'd1;
|
| 66 |
|
|
else
|
| 67 |
|
|
xbits_new <= bht_xbits;
|
| 68 |
|
|
end
|
| 69 |
|
|
|
| 70 |
|
|
always @(posedge clk)
|
| 71 |
|
|
if (rst)
|
| 72 |
|
|
gbl_branch_hist <= 3'b000;
|
| 73 |
|
|
else begin
|
| 74 |
|
|
if (advanceX) begin
|
| 75 |
|
|
if (xisBranch) begin
|
| 76 |
|
|
gbl_branch_hist <= {gbl_branch_hist[1:0],takb};
|
| 77 |
|
|
branch_history_table[bht_wa] <= xbits_new;
|
| 78 |
|
|
end
|
| 79 |
|
|
end
|
| 80 |
|
|
end
|
| 81 |
|
|
|
| 82 |
|
|
endmodule
|
| 83 |
|
|
|
