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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Establish the source queue id for a target register after a branch.
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// Makes use of the fact that in Verilog later instructions override
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// earlier ones. So if there are two queue entries that use the same
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// target register, the later queue entry will become the valid source
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// as it's written after the earlier queue entry.
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//
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// This code uses a tree approach rather than loop logic which races to the
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// the right value. The timing from the toolset is a little more reliable
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// that way.
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//
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// ============================================================================
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//
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if (branchmiss) begin
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// Default the entire register file as valid, then invalidate target
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// registers as they are found in the queue.
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for (n = 1; n < NREGS; n = n + 1)
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rf_v[n] = `VAL;
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// Missed at head0, one instruction (current one) to worry about.
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if (missid==head0) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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end
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else if (missid==head1) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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rf_source[iqentry_tgt[head1]] <= { iqentry_mem[head1], head1};
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rf_v[iqentry_tgt[head1]] = `INV;
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end
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else if (missid==head2) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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rf_source[iqentry_tgt[head1]] <= { iqentry_mem[head1], head1};
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rf_v[iqentry_tgt[head1]] = `INV;
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rf_source[iqentry_tgt[head2]] <= { iqentry_mem[head2], head2};
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rf_v[iqentry_tgt[head2]] = `INV;
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end
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else if (missid==head3) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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rf_source[iqentry_tgt[head1]] <= { iqentry_mem[head1], head1};
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rf_v[iqentry_tgt[head1]] = `INV;
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rf_source[iqentry_tgt[head2]] <= { iqentry_mem[head2], head2};
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rf_v[iqentry_tgt[head2]] = `INV;
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rf_source[iqentry_tgt[head3]] <= { iqentry_mem[head3], head3};
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rf_v[iqentry_tgt[head3]] = `INV;
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end
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else if (missid==head4) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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rf_source[iqentry_tgt[head1]] <= { iqentry_mem[head1], head1};
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rf_v[iqentry_tgt[head1]] = `INV;
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rf_source[iqentry_tgt[head2]] <= { iqentry_mem[head2], head2};
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rf_v[iqentry_tgt[head2]] = `INV;
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rf_source[iqentry_tgt[head3]] <= { iqentry_mem[head3], head3};
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rf_v[iqentry_tgt[head3]] = `INV;
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rf_source[iqentry_tgt[head4]] <= { iqentry_mem[head4], head4};
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rf_v[iqentry_tgt[head4]] = `INV;
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end
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else if (missid==head5) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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rf_source[iqentry_tgt[head1]] <= { iqentry_mem[head1], head1};
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rf_v[iqentry_tgt[head1]] = `INV;
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rf_source[iqentry_tgt[head2]] <= { iqentry_mem[head2], head2};
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rf_v[iqentry_tgt[head2]] = `INV;
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rf_source[iqentry_tgt[head3]] <= { iqentry_mem[head3], head3};
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rf_v[iqentry_tgt[head3]] = `INV;
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rf_source[iqentry_tgt[head4]] <= { iqentry_mem[head4], head4};
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rf_v[iqentry_tgt[head4]] = `INV;
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rf_source[iqentry_tgt[head5]] <= { iqentry_mem[head5], head5};
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rf_v[iqentry_tgt[head5]] = `INV;
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end
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else if (missid==head6) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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rf_source[iqentry_tgt[head1]] <= { iqentry_mem[head1], head1};
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rf_v[iqentry_tgt[head1]] = `INV;
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rf_source[iqentry_tgt[head2]] <= { iqentry_mem[head2], head2};
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rf_v[iqentry_tgt[head2]] = `INV;
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rf_source[iqentry_tgt[head3]] <= { iqentry_mem[head3], head3};
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rf_v[iqentry_tgt[head3]] = `INV;
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rf_source[iqentry_tgt[head4]] <= { iqentry_mem[head4], head4};
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rf_v[iqentry_tgt[head4]] = `INV;
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rf_source[iqentry_tgt[head5]] <= { iqentry_mem[head5], head5};
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rf_v[iqentry_tgt[head5]] = `INV;
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rf_source[iqentry_tgt[head6]] <= { iqentry_mem[head6], head6};
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rf_v[iqentry_tgt[head6]] = `INV;
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end
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else if (missid==head7) begin
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rf_source[iqentry_tgt[head0]] <= { iqentry_mem[head0], head0};
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rf_v[iqentry_tgt[head0]] = `INV;
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rf_source[iqentry_tgt[head1]] <= { iqentry_mem[head1], head1};
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rf_v[iqentry_tgt[head1]] = `INV;
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rf_source[iqentry_tgt[head2]] <= { iqentry_mem[head2], head2};
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rf_v[iqentry_tgt[head2]] = `INV;
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rf_source[iqentry_tgt[head3]] <= { iqentry_mem[head3], head3};
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rf_v[iqentry_tgt[head3]] = `INV;
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rf_source[iqentry_tgt[head4]] <= { iqentry_mem[head4], head4};
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rf_v[iqentry_tgt[head4]] = `INV;
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rf_source[iqentry_tgt[head5]] <= { iqentry_mem[head5], head5};
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rf_v[iqentry_tgt[head5]] = `INV;
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rf_source[iqentry_tgt[head6]] <= { iqentry_mem[head6], head6};
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rf_v[iqentry_tgt[head6]] = `INV;
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rf_source[iqentry_tgt[head7]] <= { iqentry_mem[head7], head7};
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rf_v[iqentry_tgt[head7]] = `INV;
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end
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// The following registers are always valid
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rf_v[7'h00] = `VAL;
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rf_v[7'h50] = `VAL; // C0
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rf_v[7'h5F] = `VAL; // C15 (PC)
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rf_v[7'h72] = `VAL; // tick
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end
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