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`include "Thor_defines.v"
//=============================================================================
//        __
//   \\__/ o\    (C) 2011,2012,2013  Robert Finch
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//  
//      Thor_TLB.v
//
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
// TLB
// The TLB contains 64 entries, that are 8 way set associative.
// The TLB is dual ported and shared between the instruction and data streams.
//
//=============================================================================
//
`define TLBMissPage             {DBW-12{1'b1}}
 
module Thor_TLB(rst, clk, km, pc, ea, ppc, pea,
        iuncached, uncached,
        m1IsStore, ASID, state, op, regno, dati, dato,
        ITLBMiss, DTLBMiss, HTLBVirtPageo);
parameter DBW=64;
input rst;
input clk;
input km;                                       // kernel mode
input [DBW-1:0] pc;
input [DBW-1:0] ea;
output reg [DBW-1:0] ppc;
output reg [DBW-1:0] pea;
output iuncached;
output uncached;
input m1IsStore;
input [7:0] ASID;
input [2:0] state;
input [3:0] op;
input [3:0] regno;
input [DBW-1:0] dati;
output [DBW-1:0] dato;
reg [DBW-1:0] dato;
output ITLBMiss;
output DTLBMiss;
output [DBW-1:0] HTLBVirtPageo;
 
integer n;
 
// Holding registers
// These allow the TLB to updated in a single cycle
reg [DBW-1:0] HTLBVirtPage;
assign HTLBVirtPageo = {HTLBVirtPage,12'b0};
reg [DBW-1:0] HTLBPhysPage;
reg [7:0] HTLBASID;
reg HTLBG;
reg HTLBD;
reg [2:0] HTLBC;
reg HTLBValid;
 
reg TLBenabled;
reg [5:0] i;
reg [DBW-1:0] Index;
reg [2:0] Random;
reg [2:0] Wired;
reg [2:0] PageSize;
reg [7:0] IMatch,DMatch;
 
reg [3:0] m;
reg [3:0] q;
wire doddpage;
reg [DBW-1:0] TLBVirtPage [63:0];
reg [DBW-1:0] TLBPhysPage [63:0];
reg [63:0] TLBG;
reg [63:0] TLBD;
reg [2:0] TLBC [63:0];
reg [7:0] TLBASID [63:0];
reg [63:0] TLBValid;
reg [DBW-1:0] imiss_addr;
reg [DBW-1:0] dmiss_addr;
reg [DBW-1:0] PageTblAddr;
reg [DBW-1:0] PageTblCtrl;
 
initial begin
        for (n = 0; n < 64; n = n + 1)
        begin
                TLBVirtPage[n] = 0;
                TLBPhysPage[n] = 0;
                TLBG[n] = 0;
                TLBASID[n] = 0;
                TLBD[n] = 0;
                TLBC[n] = 0;
                TLBValid[n] = 0;
        end
end
 
// Assume the instruction doesn't overlap between a mapped and unmapped area.
wire unmappedArea = pc[DBW-1:DBW-4]==4'hF || !TLBenabled;
wire unmappedDataArea = ea[DBW-1:DBW-4]==4'hF || !TLBenabled;
wire m1UnmappedDataArea = pea[DBW-1:DBW-4]==4'hF || !TLBenabled;
wire hitIOPage = ea[DBW-1:DBW-12]==12'hFFD;
 
always @(posedge clk)
if (rst) begin
        TLBenabled <= 1'b0;
        Random <= 3'h7;
        Wired <= 3'd0;
        PageSize <= 3'd0;
        PageTblAddr <= {DBW{1'b0}};
        PageTblCtrl <= {DBW{1'b0}};
end
else begin
        if (dmiss_addr == {DBW{1'b0}} && DTLBMiss)
                dmiss_addr <= ea;
        if (imiss_addr == {DBW{1'b0}} && ITLBMiss)
                imiss_addr <= pc;
 
        if (Random==Wired)
                Random <= 3'd7;
        else
                Random <= Random - 3'd1;
 
        if (state==3'd1) begin
                case(op)
                `TLB_RD,`TLB_WI:
                        i <= {Index[5:3],(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};
                `TLB_WR:
                        i <= {Random,(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};
                `TLB_WRREG:
                        begin
                        case(regno)
                        `TLBWired:              Wired <= dati[2:0];
                        `TLBIndex:              Index <= dati[5:0];
                        `TLBRandom:             Random <= dati[2:0];
                        `TLBPageSize:   PageSize <= dati[2:0];
                        `TLBVirtPage:   HTLBVirtPage <= dati;
                        `TLBPhysPage:   HTLBPhysPage <= dati;
                        `TLBASID:       begin
                                                HTLBValid <= dati[0];
                                                HTLBD <= dati[1];
                                                HTLBC <= dati[4:2];
                                                HTLBASID <= dati[23:16];
                                                HTLBG <= dati[31];
                                                end
                        `TLBDMissAdr:   dmiss_addr <= dati;
                        `TLBIMissAdr:   imiss_addr <= dati;
                        `TLBPageTblAddr:        PageTblAddr <= dati;
                        `TLBPageTblCtrl:        PageTblCtrl <= dati;
                        endcase
                        end
                `TLB_EN:
                        TLBenabled <= 1'b1;
                `TLB_DIS:
                        TLBenabled <= 1'b0;
                `TLB_INVALL:
                        TLBValid <= 64'd0;
                endcase
        end
        else if (state==3'd2) begin
                case(op)
                `TLB_P:
                        begin
                                Index[DBW-1] <= ~|DMatch;
                        end
                `TLB_RD:
                        begin
                                HTLBVirtPage <= TLBVirtPage[i];
                                HTLBPhysPage <= TLBPhysPage[i];
                                HTLBASID <= TLBASID[i];
                                HTLBG <= TLBG[i];
                                HTLBD <= TLBD[i];
                                HTLBC <= TLBC[i];
                                HTLBValid <= TLBValid[i];
                        end
                `TLB_WR,`TLB_WI:
                        begin
                                TLBVirtPage[i] <= HTLBVirtPage;
                                TLBPhysPage[i] <= HTLBPhysPage;
                                TLBASID[i] <= HTLBASID;
                                TLBG[i] <= HTLBG;
                                TLBD[i] <= HTLBD;
                                TLBC[i] <= HTLBC;
                                TLBValid[i] <= HTLBValid;
                        end
                default:  ;
                endcase
        end
 
        // Set the dirty bit on a store
        if (m1IsStore)
                if (!m1UnmappedDataArea & !q[3]) begin
                        TLBD[{q[2:0],(pea[DBW-1:12]>>{PageSize,1'b0})&3'd7}] <= 1'b1;
                end
end
 
always @*
        case(regno)
        `TLBWired:              dato = Wired;
        `TLBIndex:              dato = Index;
        `TLBRandom:             dato = Random;
        `TLBPhysPage:   dato = HTLBPhysPage;
        `TLBVirtPage:   dato = HTLBVirtPage;
        `TLBPageSize:   dato = PageSize;
        `TLBASID:       begin
                                dato = {DBW{1'b0}};
                                dato[0] = HTLBValid;
                                dato[1] = HTLBD;
                                dato[4:2] = HTLBC;
                                dato[23:16] = HTLBASID;
                                dato[31] = HTLBG;
                                end
        `TLBDMissAdr:   dato = dmiss_addr;
        `TLBIMissAdr:   dato = imiss_addr;
        `TLBPageTblAddr:        dato = PageTblAddr;
        `TLBPageTblCtrl:        dato = PageTblCtrl;
        default:        dato = {DBW{1'b0}};
        endcase
 
wire [DBW-1:0] pcs = pc[DBW-1:12] >> {PageSize,1'b0};
always @*
for (n = 0; n < 8; n = n + 1)
begin
        IMatch[n[2:0]] = (pcs[DBW-1:3]==TLBVirtPage[{n[2:0],pcs[2:0]}][DBW-1:3]) &&
                                ((TLBASID[{n,pcs[2:0]}]==ASID) || TLBG[{n,pcs[2:0]}]) &&
                                TLBValid[{n[2:0],pcs[2:0]}];
end
 
always @(IMatch)
if (IMatch[0]) m <= 4'd0;
else if (IMatch[1]) m <= 4'd1;
else if (IMatch[2]) m <= 4'd2;
else if (IMatch[3]) m <= 4'd3;
else if (IMatch[4]) m <= 4'd4;
else if (IMatch[5]) m <= 4'd5;
else if (IMatch[6]) m <= 4'd6;
else if (IMatch[7]) m <= 4'd7;
else m <= 4'd15;
 
 
wire [DBW-1:0] IPFN = TLBPhysPage[{m[2:0],pcs[2:0]}];
assign iuncached = TLBC[{m[2:0],pcs[2:0]}]==3'd1;
 
assign ITLBMiss = TLBenabled & (!unmappedArea & (m[3] | ~TLBValid[{m[2:0],pcs[2:0]}]));
 
always @*
begin
        ppc[11:0] = pc[11:0];
        case(PageSize)
        3'd0:   ppc[DBW-1:12] = unmappedArea ? pc[DBW-1:12] : ITLBMiss ? `TLBMissPage: IPFN;                            // 4KiB
        3'd1:   ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:14] : ITLBMiss ? `TLBMissPage: IPFN,pc[13:12]};        // 16KiB
        3'd2:   ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:16] : ITLBMiss ? `TLBMissPage: IPFN,pc[15:12]};        // 64KiB
        3'd3:   ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:18] : ITLBMiss ? `TLBMissPage: IPFN,pc[17:12]};        // 256 KiB
        3'd4:   ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:20] : ITLBMiss ? `TLBMissPage: IPFN,pc[19:12]};        // 1 MiB
        default:        ppc[DBW-1:12] = pc[DBW-1:12];
        endcase
end
 
wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};
always @(ea)
for (n = 0; n < 8; n = n + 1)
        DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&
                                ((TLBASID[{n,eas[2:0]}]==ASID) || TLBG[{n,eas[2:0]}]) &&
                                TLBValid[{q[2:0],eas[2:0]}];
always @(DMatch)
if (DMatch[0]) q <= 4'd0;
else if (DMatch[1]) q <= 4'd1;
else if (DMatch[2]) q <= 4'd2;
else if (DMatch[3]) q <= 4'd3;
else if (DMatch[4]) q <= 4'd4;
else if (DMatch[5]) q <= 4'd5;
else if (DMatch[6]) q <= 4'd6;
else if (DMatch[7]) q <= 4'd7;
else q <= 4'd15;
 
wire [DBW-1:0] DPFN = TLBPhysPage[{q[2:0],eas[2:0]}];
assign uncached = TLBC[{q[2:0],eas[2:0]}]==3'd1;// || unmappedDataArea;
 
assign DTLBMiss = TLBenabled & (!unmappedDataArea & (q[3] | ~TLBValid[{q[2:0],eas[2:0]}]) ||
                                        (!km && hitIOPage));
 
always @*
begin
        case(PageSize)
        3'd0:   pea[DBW-1:12] = unmappedDataArea ? ea[DBW-1:12] : DTLBMiss ? `TLBMissPage: DPFN;
        3'd1:   pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:14] : DTLBMiss ? `TLBMissPage: DPFN,ea[13:12]};
        3'd2:   pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:16] : DTLBMiss ? `TLBMissPage: DPFN,ea[15:12]};
        3'd3:   pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:18] : DTLBMiss ? `TLBMissPage: DPFN,ea[17:12]};
        3'd4:   pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:20] : DTLBMiss ? `TLBMissPage: DPFN,ea[19:12]};
        default:        pea[DBW-1:12] = ea[DBW-1:12];
        endcase
        pea[11:0] = ea[11:0];
end
 
endmodule
 

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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_TLB.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	robfinch	`include "Thor_defines.v"
2			`//=============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2011,2012,2013 Robert Finch`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@finitron.ca`
7			`// \|\|`
8			`//`
9			`// Thor_TLB.v`
10			`//`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26			`// TLB`
27			`// The TLB contains 64 entries, that are 8 way set associative.`
28			`// The TLB is dual ported and shared between the instruction and data streams.`
29			`//`
30			`//=============================================================================`
31			`//`
32			`define TLBMissPage {DBW-12{1'b1}}
33
34			`module Thor_TLB(rst, clk, km, pc, ea, ppc, pea,`
35			`iuncached, uncached,`
36			`m1IsStore, ASID, state, op, regno, dati, dato,`
37			`ITLBMiss, DTLBMiss, HTLBVirtPageo);`
38			`parameter DBW=64;`
39			`input rst;`
40			`input clk;`
41			`input km; // kernel mode`
42			`input [DBW-1:0] pc;`
43			`input [DBW-1:0] ea;`
44			`output reg [DBW-1:0] ppc;`
45			`output reg [DBW-1:0] pea;`
46			`output iuncached;`
47			`output uncached;`
48			`input m1IsStore;`
49			`input [7:0] ASID;`
50			`input [2:0] state;`
51			`input [3:0] op;`
52			`input [3:0] regno;`
53			`input [DBW-1:0] dati;`
54			`output [DBW-1:0] dato;`
55			`reg [DBW-1:0] dato;`
56			`output ITLBMiss;`
57			`output DTLBMiss;`
58			`output [DBW-1:0] HTLBVirtPageo;`
59
60			`integer n;`
61
62			`// Holding registers`
63			`// These allow the TLB to updated in a single cycle`
64			`reg [DBW-1:0] HTLBVirtPage;`
65			`assign HTLBVirtPageo = {HTLBVirtPage,12'b0};`
66			`reg [DBW-1:0] HTLBPhysPage;`
67			`reg [7:0] HTLBASID;`
68			`reg HTLBG;`
69			`reg HTLBD;`
70			`reg [2:0] HTLBC;`
71			`reg HTLBValid;`
72
73			`reg TLBenabled;`
74			`reg [5:0] i;`
75			`reg [DBW-1:0] Index;`
76			`reg [2:0] Random;`
77			`reg [2:0] Wired;`
78			`reg [2:0] PageSize;`
79			`reg [7:0] IMatch,DMatch;`
80
81			`reg [3:0] m;`
82			`reg [3:0] q;`
83			`wire doddpage;`
84			`reg [DBW-1:0] TLBVirtPage [63:0];`
85			`reg [DBW-1:0] TLBPhysPage [63:0];`
86			`reg [63:0] TLBG;`
87			`reg [63:0] TLBD;`
88			`reg [2:0] TLBC [63:0];`
89			`reg [7:0] TLBASID [63:0];`
90			`reg [63:0] TLBValid;`
91			`reg [DBW-1:0] imiss_addr;`
92			`reg [DBW-1:0] dmiss_addr;`
93			`reg [DBW-1:0] PageTblAddr;`
94			`reg [DBW-1:0] PageTblCtrl;`
95
96			`initial begin`
97			`for (n = 0; n < 64; n = n + 1)`
98			`begin`
99			`TLBVirtPage[n] = 0;`
100			`TLBPhysPage[n] = 0;`
101			`TLBG[n] = 0;`
102			`TLBASID[n] = 0;`
103			`TLBD[n] = 0;`
104			`TLBC[n] = 0;`
105			`TLBValid[n] = 0;`
106			`end`
107			`end`
108
109			`// Assume the instruction doesn't overlap between a mapped and unmapped area.`
110			`wire unmappedArea = pc[DBW-1:DBW-4]==4'hF \|\| !TLBenabled;`
111			`wire unmappedDataArea = ea[DBW-1:DBW-4]==4'hF \|\| !TLBenabled;`
112			`wire m1UnmappedDataArea = pea[DBW-1:DBW-4]==4'hF \|\| !TLBenabled;`
113			`wire hitIOPage = ea[DBW-1:DBW-12]==12'hFFD;`
114
115			`always @(posedge clk)`
116			`if (rst) begin`
117			`TLBenabled <= 1'b0;`
118			`Random <= 3'h7;`
119			`Wired <= 3'd0;`
120			`PageSize <= 3'd0;`
121			`PageTblAddr <= {DBW{1'b0}};`
122			`PageTblCtrl <= {DBW{1'b0}};`
123			`end`
124			`else begin`
125			`if (dmiss_addr == {DBW{1'b0}} && DTLBMiss)`
126			`dmiss_addr <= ea;`
127			`if (imiss_addr == {DBW{1'b0}} && ITLBMiss)`
128			`imiss_addr <= pc;`
129
130			`if (Random==Wired)`
131			`Random <= 3'd7;`
132			`else`
133			`Random <= Random - 3'd1;`
134
135			`if (state==3'd1) begin`
136			`case(op)`
137			`TLB_RD,`TLB_WI:
138			`i <= {Index[5:3],(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};`
139			`TLB_WR:
140			`i <= {Random,(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};`
141			`TLB_WRREG:
142			`begin`
143			`case(regno)`
144			`TLBWired: Wired <= dati[2:0];
145			`TLBIndex: Index <= dati[5:0];
146			`TLBRandom: Random <= dati[2:0];
147			`TLBPageSize: PageSize <= dati[2:0];
148			`TLBVirtPage: HTLBVirtPage <= dati;
149			`TLBPhysPage: HTLBPhysPage <= dati;
150			`TLBASID: begin
151			`HTLBValid <= dati[0];`
152			`HTLBD <= dati[1];`
153			`HTLBC <= dati[4:2];`
154			`HTLBASID <= dati[23:16];`
155			`HTLBG <= dati[31];`
156			`end`
157			`TLBDMissAdr: dmiss_addr <= dati;
158			`TLBIMissAdr: imiss_addr <= dati;
159			`TLBPageTblAddr: PageTblAddr <= dati;
160			`TLBPageTblCtrl: PageTblCtrl <= dati;
161			`endcase`
162			`end`
163			`TLB_EN:
164			`TLBenabled <= 1'b1;`
165			`TLB_DIS:
166			`TLBenabled <= 1'b0;`
167			`TLB_INVALL:
168			`TLBValid <= 64'd0;`
169			`endcase`
170			`end`
171			`else if (state==3'd2) begin`
172			`case(op)`
173			`TLB_P:
174			`begin`
175			`Index[DBW-1] <= ~\|DMatch;`
176			`end`
177			`TLB_RD:
178			`begin`
179			`HTLBVirtPage <= TLBVirtPage[i];`
180			`HTLBPhysPage <= TLBPhysPage[i];`
181			`HTLBASID <= TLBASID[i];`
182			`HTLBG <= TLBG[i];`
183			`HTLBD <= TLBD[i];`
184			`HTLBC <= TLBC[i];`
185			`HTLBValid <= TLBValid[i];`
186			`end`
187			`TLB_WR,`TLB_WI:
188			`begin`
189			`TLBVirtPage[i] <= HTLBVirtPage;`
190			`TLBPhysPage[i] <= HTLBPhysPage;`
191			`TLBASID[i] <= HTLBASID;`
192			`TLBG[i] <= HTLBG;`
193			`TLBD[i] <= HTLBD;`
194			`TLBC[i] <= HTLBC;`
195			`TLBValid[i] <= HTLBValid;`
196			`end`
197			`default: ;`
198			`endcase`
199			`end`
200
201			`// Set the dirty bit on a store`
202			`if (m1IsStore)`
203			`if (!m1UnmappedDataArea & !q[3]) begin`
204			`TLBD[{q[2:0],(pea[DBW-1:12]>>{PageSize,1'b0})&3'd7}] <= 1'b1;`
205			`end`
206			`end`
207
208			`always @*`
209			`case(regno)`
210			`TLBWired: dato = Wired;
211			`TLBIndex: dato = Index;
212			`TLBRandom: dato = Random;
213			`TLBPhysPage: dato = HTLBPhysPage;
214			`TLBVirtPage: dato = HTLBVirtPage;
215			`TLBPageSize: dato = PageSize;
216			`TLBASID: begin
217			`dato = {DBW{1'b0}};`
218			`dato[0] = HTLBValid;`
219			`dato[1] = HTLBD;`
220			`dato[4:2] = HTLBC;`
221			`dato[23:16] = HTLBASID;`
222			`dato[31] = HTLBG;`
223			`end`
224			`TLBDMissAdr: dato = dmiss_addr;
225			`TLBIMissAdr: dato = imiss_addr;
226			`TLBPageTblAddr: dato = PageTblAddr;
227			`TLBPageTblCtrl: dato = PageTblCtrl;
228			`default: dato = {DBW{1'b0}};`
229			`endcase`
230
231			`wire [DBW-1:0] pcs = pc[DBW-1:12] >> {PageSize,1'b0};`
232			`always @*`
233			`for (n = 0; n < 8; n = n + 1)`
234			`begin`
235			`IMatch[n[2:0]] = (pcs[DBW-1:3]==TLBVirtPage[{n[2:0],pcs[2:0]}][DBW-1:3]) &&`
236			`((TLBASID[{n,pcs[2:0]}]==ASID) \|\| TLBG[{n,pcs[2:0]}]) &&`
237			`TLBValid[{n[2:0],pcs[2:0]}];`
238			`end`
239
240			`always @(IMatch)`
241			`if (IMatch[0]) m <= 4'd0;`
242			`else if (IMatch[1]) m <= 4'd1;`
243			`else if (IMatch[2]) m <= 4'd2;`
244			`else if (IMatch[3]) m <= 4'd3;`
245			`else if (IMatch[4]) m <= 4'd4;`
246			`else if (IMatch[5]) m <= 4'd5;`
247			`else if (IMatch[6]) m <= 4'd6;`
248			`else if (IMatch[7]) m <= 4'd7;`
249			`else m <= 4'd15;`
250
251
252			`wire [DBW-1:0] IPFN = TLBPhysPage[{m[2:0],pcs[2:0]}];`
253			`assign iuncached = TLBC[{m[2:0],pcs[2:0]}]==3'd1;`
254
255			`assign ITLBMiss = TLBenabled & (!unmappedArea & (m[3] \| ~TLBValid[{m[2:0],pcs[2:0]}]));`
256
257			`always @*`
258			`begin`
259			`ppc[11:0] = pc[11:0];`
260			`case(PageSize)`
261			3'd0: ppc[DBW-1:12] = unmappedArea ? pc[DBW-1:12] : ITLBMiss ? `TLBMissPage: IPFN; // 4KiB
262			3'd1: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:14] : ITLBMiss ? `TLBMissPage: IPFN,pc[13:12]}; // 16KiB
263			3'd2: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:16] : ITLBMiss ? `TLBMissPage: IPFN,pc[15:12]}; // 64KiB
264			3'd3: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:18] : ITLBMiss ? `TLBMissPage: IPFN,pc[17:12]}; // 256 KiB
265			3'd4: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:20] : ITLBMiss ? `TLBMissPage: IPFN,pc[19:12]}; // 1 MiB
266			`default: ppc[DBW-1:12] = pc[DBW-1:12];`
267			`endcase`
268			`end`
269
270			`wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};`
271			`always @(ea)`
272			`for (n = 0; n < 8; n = n + 1)`
273			`DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&`
274			`((TLBASID[{n,eas[2:0]}]==ASID) \|\| TLBG[{n,eas[2:0]}]) &&`
275			`TLBValid[{q[2:0],eas[2:0]}];`
276			`always @(DMatch)`
277			`if (DMatch[0]) q <= 4'd0;`
278			`else if (DMatch[1]) q <= 4'd1;`
279			`else if (DMatch[2]) q <= 4'd2;`
280			`else if (DMatch[3]) q <= 4'd3;`
281			`else if (DMatch[4]) q <= 4'd4;`
282			`else if (DMatch[5]) q <= 4'd5;`
283			`else if (DMatch[6]) q <= 4'd6;`
284			`else if (DMatch[7]) q <= 4'd7;`
285			`else q <= 4'd15;`
286
287			`wire [DBW-1:0] DPFN = TLBPhysPage[{q[2:0],eas[2:0]}];`
288			`assign uncached = TLBC[{q[2:0],eas[2:0]}]==3'd1;// \|\| unmappedDataArea;`
289
290			`assign DTLBMiss = TLBenabled & (!unmappedDataArea & (q[3] \| ~TLBValid[{q[2:0],eas[2:0]}]) \|\|`
291			`(!km && hitIOPage));`
292
293			`always @*`
294			`begin`
295			`case(PageSize)`
296			3'd0: pea[DBW-1:12] = unmappedDataArea ? ea[DBW-1:12] : DTLBMiss ? `TLBMissPage: DPFN;
297			3'd1: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:14] : DTLBMiss ? `TLBMissPage: DPFN,ea[13:12]};
298			3'd2: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:16] : DTLBMiss ? `TLBMissPage: DPFN,ea[15:12]};
299			3'd3: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:18] : DTLBMiss ? `TLBMissPage: DPFN,ea[17:12]};
300			3'd4: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:20] : DTLBMiss ? `TLBMissPage: DPFN,ea[19:12]};
301			`default: pea[DBW-1:12] = ea[DBW-1:12];`
302			`endcase`
303			`pea[11:0] = ea[11:0];`
304			`end`
305
306			`endmodule`
307