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// ============================================================================
//        __
//   \\__/ o\    (C) 2013-2016  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
// Thor SuperScaler
// ALU
//
// ============================================================================
//
`include "Thor_defines.v"
 
module Thor_alu(corenum, rst, clk, alu_ld, alu_abort, alu_op, alu_fn, alu_argA, alu_argB, alu_argC, alu_argI, alu_pc, insnsz, o, alu_done, alu_idle, alu_divByZero);
parameter DBW=64;
parameter BIG=1;
parameter FEATURES = 0;
input [63:0] corenum;
input rst;
input clk;
input alu_ld;
input alu_abort;
input [7:0] alu_op;
input [5:0] alu_fn;
input [DBW-1:0] alu_argA;
input [DBW-1:0] alu_argB;
input [DBW-1:0] alu_argC;
input [DBW-1:0] alu_argI;
input [DBW-1:0] alu_pc;
input [3:0] insnsz;
output reg [DBW-1:0] o;
output reg alu_done;
output reg alu_idle;
output alu_divByZero;
 
wire signed [DBW-1:0] alu_argAs = alu_argA;
wire signed [DBW-1:0] alu_argBs = alu_argB;
wire signed [DBW-1:0] alu_argIs = alu_argI;
wire [DBW-1:0] andi_res = alu_argA & alu_argI;
wire [127:0] alu_prod;
wire [63:0] alu_divq;
wire [63:0] alu_rem;
wire [7:0] bcdao,bcdso;
wire [15:0] bcdmo;
wire [DBW-1:0] bf_out;
wire [DBW-1:0] shfto;
wire alu_mult_done,alu_div_done;
wire alu_mult_idle,alu_div_idle;
wire [DBW-1:0] p_out;
reg [3:0] o1;
 
integer n;
 
Thor_multiplier #(DBW) umult1
(
        .rst(rst),
        .clk(clk),
        .ld(alu_ld && ((alu_op==`RR && (alu_fn==`MUL || alu_fn==`MULU)) || alu_op==`MULI || alu_op==`MULUI)),
        .abort(alu_abort),
        .sgn((alu_op==`RR && alu_op==`MUL) || alu_op==`MULI),
        .isMuli(alu_op==`MULI || alu_op==`MULUI),
        .a(alu_argA),
        .b(alu_argB),
        .imm(alu_argI),
        .o(alu_prod),
        .done(alu_mult_done),
        .idle(alu_mult_idle)
);
 
Thor_divider #(DBW) udiv1
(
        .rst(rst),
        .clk(clk),
        .ld(alu_ld && ((alu_op==`RR && (alu_fn==`DIV || alu_fn==`DIVU || alu_fn==`MOD || alu_fn==`MODU))
           || alu_op==`DIVI || alu_op==`DIVUI || alu_op==`MODI || alu_op==`MODUI)),
        .abort(alu_abort),
        .sgn((alu_op==`RR && (alu_fn==`DIV || alu_fn==`MOD)) || alu_op==`DIVI || alu_op==`MODI),
        .isDivi(alu_op==`DIVI || alu_op==`DIVUI || alu_op==`MODI || alu_op==`MODUI),
        .a(alu_argA),
        .b(alu_argB),
        .imm(alu_argI),
        .qo(alu_divq),
        .ro(alu_rem),
        .dvByZr(alu_divByZero),
        .done(alu_div_done),
        .idle(alu_div_idle)
);
 
Thor_shifter #(DBW) ushft0
(
        .func(alu_fn),
        .a(alu_argA),
        .b(alu_argB),
        .o(shfto)
);
 
BCDAdd ubcda
(
        .ci(1'b0),
        .a(alu_argA[7:0]),
        .b(alu_argB[7:0]),
        .o(bcdao),
        .c()
);
 
BCDSub ubcds
(
        .ci(1'b0),
        .a(alu_argA[7:0]),
        .b(alu_argB[7:0]),
        .o(bcdso),
        .c()
);
 
BCDMul2 ubcdm
(
        .a(alu_argA),
        .b(alu_argB),
        .o(bcdmo)
);
 
Thor_bitfield #(DBW) ubf1
(
        .op(alu_fn),
        .a(alu_argA),
        .b(alu_argB),
        .m(alu_argI[11:0]),
        .o(bf_out),
        .masko()
);
 
Thor_P #(DBW) upr1
(
    .fn(alu_fn),
    .ra(alu_argI[5:0]),
    .rb(alu_argI[11:6]),
    .rt(alu_argI[17:12]),
    .pregs_i(alu_argA),
    .pregs_o(p_out)
);
 
wire [DBW-1:0] cntlzo;
wire [DBW-1:0] cntloo;
wire [DBW-1:0] cntpopo;
 
generate
begin : clzg
if (DBW==64) begin
cntlz64 u12 ( .i(alu_argA),  .o(cntlzo) );
cntlo64 u13 ( .i(alu_argA),  .o(cntloo) );
cntpop64 u14 ( .i(alu_argA), .o(cntpopo) );
end
else begin
cntlz32 u12 ( .i(alu_argA),  .o(cntlzo) );
cntlo32 u13 ( .i(alu_argA),  .o(cntloo) );
cntpop32 u14 ( .i(alu_argA), .o(cntpopo) );
end
end
endgenerate
 
wire faz = alu_argA[DBW-2:0]==63'd0;
wire fbz = alu_argB[DBW-2:0]==63'd0;
wire feq = (faz & fbz) || (alu_argA==alu_argB); // special test for zero
wire fgt1 = alu_argA[DBW-2:0] > alu_argB[DBW-2:0];
wire flt1 = alu_argA[DBW-2:0] < alu_argB[DBW-2:0];
wire flt = alu_argA[DBW-1] ^ alu_argB[DBW-1] ? alu_argA[DBW-1] & !(faz & fbz): alu_argA[DBW-1] ? fgt1 : flt1;
wire nanA = DBW==32 ? alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0) : alu_argA[62:52]==11'h7FF && (alu_argA[51:0]!=52'd0);
wire nanB = DBW==32 ? alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0) : alu_argB[62:52]==11'h7FF && (alu_argB[51:0]!=52'd0);
 
wire fsaz = alu_argA[30:0]==31'd0;
wire fsbz = alu_argB[30:0]==31'd0;
wire fseq = (fsaz & fsbz) || (alu_argA[31:0]==alu_argB[31:0]);    // special test for zero
wire fsgt1 = alu_argA[30:0] > alu_argB[30:0];
wire fslt1 = alu_argA[30:0] < alu_argB[30:0];
wire fslt = alu_argA[31] ^ alu_argB[31] ? alu_argA[31] & !(fsaz & fsbz): alu_argA[31] ? fsgt1 : fslt1;
wire snanA = alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0);
wire snanB = alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0);
 
always @*
begin
case(alu_op)
`LDI,`LDIS:                     o <= alu_argI;
`RR:
        case(alu_fn)
        `ADD,`ADDU:             o <= alu_argA + alu_argB;
        `SUB,`SUBU:             o <= alu_argA - alu_argB;
        `_2ADDU:                o <= {alu_argA[DBW-2:0],1'b0} + alu_argB;
        `_4ADDU:                o <= {alu_argA[DBW-3:0],2'b0} + alu_argB;
        `_8ADDU:                o <= {alu_argA[DBW-4:0],3'b0} + alu_argB;
        `_16ADDU:               o <= {alu_argA[DBW-5:0],4'b0} + alu_argB;
        `MIN:           o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
        `MAX:           o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
        `MUL,`MULU:     o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
        `DIV,`DIVU:     o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
    `MOD,`MODU:     o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
    `CHK:           o <= ($signed(alu_argC) >= $signed(alu_argA)) && ($signed(alu_argC) < $signed(alu_argB));
        default:   o <= 64'hDEADDEADDEADDEAD;
        endcase
`MULI,`MULUI:   o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
`DIVI,`DIVUI:   o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
`MODI,`MODUI:   o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
`_2ADDUI:               o <= {alu_argA[DBW-2:0],1'b0} + alu_argI;
`_4ADDUI:               o <= {alu_argA[DBW-3:0],2'b0} + alu_argI;
`_8ADDUI:               o <= {alu_argA[DBW-4:0],3'b0} + alu_argI;
`_16ADDUI:              o <= {alu_argA[DBW-5:0],4'b0} + alu_argI;
`R:
    case(alu_fn[3:0])
    `MOV:       o <= alu_argA;
    `NEG:               o <= -alu_argA;
    `NOT:       o <= |alu_argA ? 64'd0 : 64'd1;
    `ABS:       o <= BIG ? (alu_argA[DBW-1] ? -alu_argA : alu_argA) : 64'hDEADDEADDEADDEAD;
    `SGN:       o <= BIG ? (alu_argA[DBW-1] ? 64'hFFFFFFFFFFFFFFFF : alu_argA==64'd0 ? 64'd0 : 64'd1) : 64'hDEADDEADDEADDEAD;
    `CNTLZ:     o <= BIG ? cntlzo : 64'hDEADDEADDEADDEAD;
    `CNTLO:     o <= BIG ? cntloo : 64'hDEADDEADDEADDEAD;
    `CNTPOP:    o <= BIG ? cntpopo : 64'hDEADDEADDEADDEAD;
    `ZXB:       o <= BIG ? {56'd0,alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
    `ZXC:       o <= BIG ? {48'd0,alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
    `ZXH:       o <= BIG ? {32'd0,alu_argA[31:0]} : 64'hDEADDEADDEADDEAD;
    `COM:       o <= ~alu_argA;
    `SXB:       o <= BIG ? {{56{alu_argA[7]}},alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
    `SXC:       o <= BIG ? {{48{alu_argA[15]}},alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
    `SXH:       o <= BIG ? {{32{alu_argA[31]}},alu_argA[31:0]} : 64'hDEADDEADDEADDEAD;
    default:    o <= 64'hDEADDEADDEADDEAD;
    endcase
`R2:
    case(alu_fn)
    `CPUID:
        if (BIG)
        case(alu_argA[4:0])
        5'd0:       o <= corenum;
        5'd2:       o <= "Finitron";
        5'd3:       o <= "";        // vendor ID
        5'd4:       o <= "64BitSS"; // class
        5'd6:       o <= "Thor";    // Name
        5'd8:       o <= "M1";      // model 
        5'd9:       o <= "1234";    // serial num
        5'd10:      o <= FEATURES;
        5'd11:      o <= {32'd16384,32'd32768}; // Cache D,I
        default:    o <= 64'hDEADDEADDEADDEAD;
        endcase
        else    o <= 64'hDEADDEADDEADDEAD;
    `REDOR:     o <= BIG ? |alu_argA : 64'hDEADDEADDEADDEAD;
    `REDAND:    o <= BIG ? &alu_argA : 64'hDEADDEADDEADDEAD;
    `PAR:       o <= BIG ? ^alu_argA : 64'hDEADDEADDEADDEAD;
    default:    o <= 64'hDEADDEADDEADDEAD;
    endcase
`P: o <= p_out;
/*
`DOUBLE:
    if (BIG) begin
        if (alu_fn[5:4]==2'b00)
            case (alu_fn)
            `FMOV:      o <= alu_argA;
            `FNEG:              o <= {~alu_argA[DBW-1],alu_argA[DBW-2:0]};
            `FABS:              o <= {1'b0,alu_argA[DBW-2:0]};
            `FSIGN:                     if (DBW==64)
                                o <= alu_argA[DBW-2:0]==0 ? {DBW{1'b0}} : {alu_argA[DBW-1],1'b0,{10{1'b1}},{52{1'b0}}};
                            else
                                o <= alu_argA[DBW-2:0]==0 ? {DBW{1'b0}} : {alu_argA[DBW-1],1'b0,{7{1'b1}},{23{1'b0}}};
            `FMAN:      o <= alu_argA[(DBW==64?51:22):0];
            default:    o <= 64'hDEADDEADDEADDEAD;
            endcase
        else
            case (alu_fn)
            `FMOV:      o <= alu_argA;
            `FSNEG:     o <= {~alu_argA[31],alu_argA[30:0]};
            `FSABS:     o <= {1'b0,alu_argA[30:0]};
            `FSSIGN:    o <= alu_argA[30:0]==0 ? {DBW{1'b0}} : {alu_argA[31],1'b0,{7{1'b1}},{23{1'b0}}};
            `FSMAN:     o <= alu_argA[22:0];
            default:    o <= 64'hDEADDEADDEADDEAD;
            endcase
    end
    else
        o <= 64'hDEADDEADDEADDEAD;
 */
 
`ADDI,`ADDUI,`ADDUIS:
                o <= alu_argA + alu_argI;
`SUBI,`SUBUI:
                o <= alu_argA - alu_argI;
`ANDI:                  o <= alu_argA & alu_argI;
`ORI:                   o <= alu_argA | alu_argI;
`EORI:                  o <= alu_argA ^ alu_argI;
`LOGIC,`MLO:
        case(alu_fn)
        `AND:                   o <= alu_argA & alu_argB;
        `ANDC:                  o <= alu_argA & ~alu_argB;
        `OR:                    o <= alu_argA | alu_argB;
        `ORC:                   o <= alu_argA | ~alu_argB;
        `EOR:                   o <= alu_argA ^ alu_argB;
        `NAND:                  o <= ~(alu_argA & alu_argB);
        `NOR:                   o <= ~(alu_argA | alu_argB);
        `ENOR:                  o <= ~(alu_argA ^ alu_argB);
        default:       o <= 64'd0;
        endcase
`BITI:
    begin
        o1[0] = andi_res==64'd0;
        o1[1] = andi_res[DBW-1];
        o1[2] = andi_res[0];
        o1[3] = 1'b0;
        o <= {16{o1}};
    end
// TST
8'h00,8'h01,8'h02,8'h03,8'h04,8'h05,8'h06,8'h07,8'h08,8'h09,8'h0A,8'h0B,8'h0C,8'h0D,8'h0E,8'h0f:
        case(alu_fn)
        6'd0:   // TST - integer
                begin
                        o1[0] = alu_argA == 64'd0;
                        o1[1] = alu_argA[DBW-1];
                        o1[2] = 1'b0;
                        o1[3] = 1'b0;
                        o <= {16{o1}};
                end
`ifdef FLOATING_POINT
        6'd1:   // FSTST - float single
                begin
                        o1[0] = alu_argA[30:0]==31'd0;    // + or - zero
                        o1[1] = alu_argA[31];                   // signed less than
                        o1[2] = alu_argA[31];
                        // unordered
                        o1[3] = alu_argA[30:23]==8'hFF && alu_argA[22:0]!=23'd0; // NaN
                        o <= {16{o1}};
                end
        6'd2:   // FTST - float double
                begin
                        o1[0] = alu_argA[DBW-2:0]==63'd0; // + or - zero
                        o1[1] = alu_argA[DBW-1];                        // signed less than
                        o1[2] = alu_argA[DBW-1];
                        // unordered
                        if (DBW==64)
                                o1[3] = alu_argA[62:52]==11'h7FF && alu_argA[51:0]!=52'd0;       // NaN
                        else
                                o1[3] = 1'b0;
                        o <= {16{o1}};
                end
`endif
        default:        o <= 64'd0;
        endcase
// CMP
8'h10,8'h11,8'h12,8'h13,8'h14,8'h15,8'h16,8'h17,8'h18,8'h19,8'h1A,8'h1B,8'h1C,8'h1D,8'h1E,8'h1f:
    begin
            case(alu_fn)
            2'd0: begin     // ICMP
                o1[0] = alu_argA == alu_argB;
                o1[1] = ($signed(alu_argA) < $signed(alu_argB));
                o1[2] = alu_argA < alu_argB;
                o1[3] = 1'b0;
                        o <= {16{o1}};
                end
`ifdef FLOATING_POINT
            2'd1: begin     // FSCMP
                o1[0] = fseq;
                o1[1] = fslt;
                o1[2] = fslt1;
                o1[3] = snanA | snanB;
                        o <= {16{o1}};
                end
            2'd2: begin     // FCMP
                o1[0] = feq;
                o1[1] = flt;
                o1[2] = flt1;
                o1[3] = nanA | nanB;
                        o <= {16{o1}};
                end
`endif
            default: o <= 64'hDEADDEADDEADDEAD;
            endcase
                end
// CMPI
8'h20,8'h21,8'h22,8'h23,8'h24,8'h25,8'h26,8'h27,8'h28,8'h29,8'h2A,8'h2B,8'h2C,8'h2D,8'h2E,8'h2f:
        begin
                        o1[0] = alu_argA == alu_argI;
                        o1[1] = ($signed(alu_argA) < $signed(alu_argI));
                        o1[2] = alu_argA < alu_argI;
                        o1[3] = 1'b0;
                        o <= {16{o1}};
                end
`LLA,
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`SB,`SC,`SH,`SW,`CAS,`LVB,`LVC,`LVH,`LVW,`STI,
`LWS,`SWS,`STS,`STFND,`STCMP,`PUSH:
            begin
                                o <= alu_argA + alu_argC + alu_argI;
                    end
`JMPI:      o <= {alu_argA << alu_fn[1:0]} + alu_argC + alu_argI;
`LBX,`LBUX,`SBX,
`LCX,`LCUX,`SCX,
`LHX,`LHUX,`SHX,
`LWX,`SWX,`LLAX,
`JMPIX:
            case(alu_fn[1:0])
            2'd0:   o <= alu_argA + alu_argC + alu_argB;
            2'd1:   o <= alu_argA + alu_argC + {alu_argB,1'b0};
            2'd2:   o <= alu_argA + alu_argC + {alu_argB,2'b0};
            2'd3:   o <= alu_argA + alu_argC + {alu_argB,3'b0};
            endcase
`ifdef STACKOPS
`PEA,`LINK: o <= alu_argA + alu_argC - 64'd8;
`UNLINK:    o <= alu_argA + alu_argC + 64'd8;
`POP:       o <= alu_argA + alu_argC;
`endif
`JSR,`JSRS,`JSRZ,`SYS:  o <= alu_pc + insnsz;
`INT:           o <= alu_pc;
`MFSPR,`MTSPR:  begin
                o <= alu_argA;
                end
`MUX:   begin
                        for (n = 0; n < DBW; n = n + 1)
                                o[n] <= alu_argA[n] ? alu_argB[n] : alu_argC[n];
                end
`BCD:
        if (BIG)
            case(alu_fn)
            `BCDADD:    o <= bcdao;
            `BCDSUB:    o <= bcdso;
            `BCDMUL:    o <= bcdmo;
            default:    o <= 64'hDEADDEADDEADDEAD;
            endcase
        else
            o <= 64'hDEADDEADDEADDEAD;
`SHIFT:     o <= BIG ? shfto : 64'hDEADDEADDEADDEAD;
`ifdef BITFIELDOPS
`BITFIELD:      o <= BIG ? bf_out : 64'hDEADDEADDEADDEAD;
`endif
`LOOP:      o <= alu_argA > 0 ? alu_argA - 64'd1 : alu_argA;
`CHKI:      o <= ($signed(alu_argB) >= $signed(alu_argA)) && ($signed(alu_argB) < $signed(alu_argI));
default:        o <= 64'hDEADDEADDEADDEAD;
endcase
end
 
// Generate done signal
always @*
case(alu_op)
`RR:
    case(alu_fn)
    `MUL,`MULU: alu_done <= alu_mult_done;
    `DIV,`DIVU,`MOD,`MODU: alu_done <= alu_div_done;
    default:    alu_done <= `TRUE;
    endcase
`MULI,`MULUI:   alu_done <= alu_mult_done;
`DIVI,`DIVUI,`MODI,`MODUI:   alu_done <= alu_div_done;
default:    alu_done <= `TRUE;
endcase
 
// Generate idle signal
always @*
case(alu_op)
`RR:
    case(alu_fn)
    `MUL,`MULU: alu_idle <= alu_mult_idle;
    `DIV,`DIVU,`MOD,`MODU: alu_idle <= alu_div_idle;
    default:    alu_idle <= `TRUE;
    endcase
`MULI,`MULUI:   alu_idle <= alu_mult_idle;
`DIVI,`DIVUI,`MODI,`MODUI:   alu_idle <= alu_div_idle;
default:    alu_idle <= `TRUE;
endcase
 
endmodule

Line No.	Rev	Author	Line
1	3	robfinch	`// ============================================================================`
2			`// __`
3	37	robfinch	`// \\__/ o\ (C) 2013-2016 Robert Finch, Stratford`
4	3	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`//`
22			`// Thor SuperScaler`
23			`// ALU`
24			`//`
25			`// ============================================================================`
26			`//`
27			`include "Thor_defines.v"
28
29	13	robfinch	`module Thor_alu(corenum, rst, clk, alu_ld, alu_abort, alu_op, alu_fn, alu_argA, alu_argB, alu_argC, alu_argI, alu_pc, insnsz, o, alu_done, alu_idle, alu_divByZero);`
30	3	robfinch	`parameter DBW=64;`
31			`parameter BIG=1;`
32			`parameter FEATURES = 0;`
33			`input [63:0] corenum;`
34			`input rst;`
35			`input clk;`
36			`input alu_ld;`
37	13	robfinch	`input alu_abort;`
38	3	robfinch	`input [7:0] alu_op;`
39			`input [5:0] alu_fn;`
40			`input [DBW-1:0] alu_argA;`
41			`input [DBW-1:0] alu_argB;`
42			`input [DBW-1:0] alu_argC;`
43			`input [DBW-1:0] alu_argI;`
44			`input [DBW-1:0] alu_pc;`
45			`input [3:0] insnsz;`
46			`output reg [DBW-1:0] o;`
47			`output reg alu_done;`
48	13	robfinch	`output reg alu_idle;`
49	3	robfinch	`output alu_divByZero;`
50
51			`wire signed [DBW-1:0] alu_argAs = alu_argA;`
52			`wire signed [DBW-1:0] alu_argBs = alu_argB;`
53			`wire signed [DBW-1:0] alu_argIs = alu_argI;`
54			`wire [DBW-1:0] andi_res = alu_argA & alu_argI;`
55			`wire [127:0] alu_prod;`
56			`wire [63:0] alu_divq;`
57			`wire [63:0] alu_rem;`
58			`wire [7:0] bcdao,bcdso;`
59			`wire [15:0] bcdmo;`
60			`wire [DBW-1:0] bf_out;`
61			`wire [DBW-1:0] shfto;`
62			`wire alu_mult_done,alu_div_done;`
63	13	robfinch	`wire alu_mult_idle,alu_div_idle;`
64	3	robfinch	`wire [DBW-1:0] p_out;`
65	9	robfinch	`reg [3:0] o1;`
66	3	robfinch
67			`integer n;`
68
69			`Thor_multiplier #(DBW) umult1`
70			`(`
71			`.rst(rst),`
72			`.clk(clk),`
73			.ld(alu_ld && ((alu_op==`RR && (alu_fn==`MUL \|\| alu_fn==`MULU)) \|\| alu_op==`MULI \|\| alu_op==`MULUI)),
74	13	robfinch	`.abort(alu_abort),`
75	3	robfinch	.sgn((alu_op==`RR && alu_op==`MUL) \|\| alu_op==`MULI),
76			.isMuli(alu_op==`MULI \|\| alu_op==`MULUI),
77			`.a(alu_argA),`
78			`.b(alu_argB),`
79			`.imm(alu_argI),`
80			`.o(alu_prod),`
81	13	robfinch	`.done(alu_mult_done),`
82			`.idle(alu_mult_idle)`
83	3	robfinch	`);`
84
85			`Thor_divider #(DBW) udiv1`
86			`(`
87			`.rst(rst),`
88			`.clk(clk),`
89	13	robfinch	.ld(alu_ld && ((alu_op==`RR && (alu_fn==`DIV \|\| alu_fn==`DIVU \|\| alu_fn==`MOD \|\| alu_fn==`MODU))
90			\|\| alu_op==`DIVI \|\| alu_op==`DIVUI \|\| alu_op==`MODI \|\| alu_op==`MODUI)),
91			`.abort(alu_abort),`
92			.sgn((alu_op==`RR && (alu_fn==`DIV \|\| alu_fn==`MOD)) \|\| alu_op==`DIVI \|\| alu_op==`MODI),
93			.isDivi(alu_op==`DIVI \|\| alu_op==`DIVUI \|\| alu_op==`MODI \|\| alu_op==`MODUI),
94	3	robfinch	`.a(alu_argA),`
95			`.b(alu_argB),`
96			`.imm(alu_argI),`
97			`.qo(alu_divq),`
98			`.ro(alu_rem),`
99			`.dvByZr(alu_divByZero),`
100	13	robfinch	`.done(alu_div_done),`
101			`.idle(alu_div_idle)`
102	3	robfinch	`);`
103
104			`Thor_shifter #(DBW) ushft0`
105			`(`
106			`.func(alu_fn),`
107			`.a(alu_argA),`
108			`.b(alu_argB),`
109			`.o(shfto)`
110			`);`
111
112			`BCDAdd ubcda`
113			`(`
114			`.ci(1'b0),`
115			`.a(alu_argA[7:0]),`
116			`.b(alu_argB[7:0]),`
117			`.o(bcdao),`
118			`.c()`
119			`);`
120
121			`BCDSub ubcds`
122			`(`
123			`.ci(1'b0),`
124			`.a(alu_argA[7:0]),`
125			`.b(alu_argB[7:0]),`
126			`.o(bcdso),`
127			`.c()`
128			`);`
129
130			`BCDMul2 ubcdm`
131			`(`
132			`.a(alu_argA),`
133			`.b(alu_argB),`
134			`.o(bcdmo)`
135			`);`
136
137			`Thor_bitfield #(DBW) ubf1`
138			`(`
139			`.op(alu_fn),`
140			`.a(alu_argA),`
141			`.b(alu_argB),`
142			`.m(alu_argI[11:0]),`
143			`.o(bf_out),`
144			`.masko()`
145			`);`
146
147			`Thor_P #(DBW) upr1`
148			`(`
149			`.fn(alu_fn),`
150			`.ra(alu_argI[5:0]),`
151			`.rb(alu_argI[11:6]),`
152			`.rt(alu_argI[17:12]),`
153			`.pregs_i(alu_argA),`
154			`.pregs_o(p_out)`
155			`);`
156
157			`wire [DBW-1:0] cntlzo;`
158			`wire [DBW-1:0] cntloo;`
159			`wire [DBW-1:0] cntpopo;`
160
161			`generate`
162			`begin : clzg`
163			`if (DBW==64) begin`
164			`cntlz64 u12 ( .i(alu_argA), .o(cntlzo) );`
165			`cntlo64 u13 ( .i(alu_argA), .o(cntloo) );`
166			`cntpop64 u14 ( .i(alu_argA), .o(cntpopo) );`
167			`end`
168			`else begin`
169			`cntlz32 u12 ( .i(alu_argA), .o(cntlzo) );`
170			`cntlo32 u13 ( .i(alu_argA), .o(cntloo) );`
171			`cntpop32 u14 ( .i(alu_argA), .o(cntpopo) );`
172			`end`
173			`end`
174			`endgenerate`
175
176			`wire faz = alu_argA[DBW-2:0]==63'd0;`
177			`wire fbz = alu_argB[DBW-2:0]==63'd0;`
178			`wire feq = (faz & fbz) \|\| (alu_argA==alu_argB); // special test for zero`
179			`wire fgt1 = alu_argA[DBW-2:0] > alu_argB[DBW-2:0];`
180			`wire flt1 = alu_argA[DBW-2:0] < alu_argB[DBW-2:0];`
181	37	robfinch	`wire flt = alu_argA[DBW-1] ^ alu_argB[DBW-1] ? alu_argA[DBW-1] & !(faz & fbz): alu_argA[DBW-1] ? fgt1 : flt1;`
182	3	robfinch	`wire nanA = DBW==32 ? alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0) : alu_argA[62:52]==11'h7FF && (alu_argA[51:0]!=52'd0);`
183			`wire nanB = DBW==32 ? alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0) : alu_argB[62:52]==11'h7FF && (alu_argB[51:0]!=52'd0);`
184
185			`wire fsaz = alu_argA[30:0]==31'd0;`
186			`wire fsbz = alu_argB[30:0]==31'd0;`
187			`wire fseq = (fsaz & fsbz) \|\| (alu_argA[31:0]==alu_argB[31:0]); // special test for zero`
188			`wire fsgt1 = alu_argA[30:0] > alu_argB[30:0];`
189			`wire fslt1 = alu_argA[30:0] < alu_argB[30:0];`
190			`wire fslt = alu_argA[31] ^ alu_argB[31] ? alu_argA[31] & !(fsaz & fsbz): alu_argA[31] ? fsgt1 : fslt1;`
191			`wire snanA = alu_argA[30:23]==8'hFF && (alu_argA[22:0]!=23'd0);`
192			`wire snanB = alu_argB[30:23]==8'hFF && (alu_argB[22:0]!=23'd0);`
193
194			`always @*`
195			`begin`
196	9	robfinch	`case(alu_op)`
197	3	robfinch	`LDI,`LDIS: o <= alu_argI;
198			`RR:
199			`case(alu_fn)`
200			`ADD,`ADDU: o <= alu_argA + alu_argB;
201			`SUB,`SUBU: o <= alu_argA - alu_argB;
202			`_2ADDU: o <= {alu_argA[DBW-2:0],1'b0} + alu_argB;
203			`_4ADDU: o <= {alu_argA[DBW-3:0],2'b0} + alu_argB;
204			`_8ADDU: o <= {alu_argA[DBW-4:0],3'b0} + alu_argB;
205			`_16ADDU: o <= {alu_argA[DBW-5:0],4'b0} + alu_argB;
206			`MIN: o <= BIG ? (alu_argA < alu_argB ? alu_argA : alu_argB) : 64'hDEADDEADDEADDEAD;
207			`MAX: o <= BIG ? (alu_argA < alu_argB ? alu_argB : alu_argA) : 64'hDEADDEADDEADDEAD;
208			`MUL,`MULU: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
209			`DIV,`DIVU: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
210	13	robfinch	`MOD,`MODU: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
211	37	robfinch	`CHK: o <= ($signed(alu_argC) >= $signed(alu_argA)) && ($signed(alu_argC) < $signed(alu_argB));
212	3	robfinch	`default: o <= 64'hDEADDEADDEADDEAD;`
213			`endcase`
214			`MULI,`MULUI: o <= BIG ? alu_prod[63:0] : 64'hDEADDEADDEADDEAD;
215			`DIVI,`DIVUI: o <= BIG ? alu_divq : 64'hDEADDEADDEADDEAD;
216	13	robfinch	`MODI,`MODUI: o <= BIG ? alu_rem : 64'hDEADDEADDEADDEAD;
217	3	robfinch	`_2ADDUI: o <= {alu_argA[DBW-2:0],1'b0} + alu_argI;
218			`_4ADDUI: o <= {alu_argA[DBW-3:0],2'b0} + alu_argI;
219			`_8ADDUI: o <= {alu_argA[DBW-4:0],3'b0} + alu_argI;
220			`_16ADDUI: o <= {alu_argA[DBW-5:0],4'b0} + alu_argI;
221			`R:
222			`case(alu_fn[3:0])`
223			`MOV: o <= alu_argA;
224			`NEG: o <= -alu_argA;
225			`NOT: o <= \|alu_argA ? 64'd0 : 64'd1;
226	37	robfinch	`ABS: o <= BIG ? (alu_argA[DBW-1] ? -alu_argA : alu_argA) : 64'hDEADDEADDEADDEAD;
227			`SGN: o <= BIG ? (alu_argA[DBW-1] ? 64'hFFFFFFFFFFFFFFFF : alu_argA==64'd0 ? 64'd0 : 64'd1) : 64'hDEADDEADDEADDEAD;
228	3	robfinch	`CNTLZ: o <= BIG ? cntlzo : 64'hDEADDEADDEADDEAD;
229			`CNTLO: o <= BIG ? cntloo : 64'hDEADDEADDEADDEAD;
230			`CNTPOP: o <= BIG ? cntpopo : 64'hDEADDEADDEADDEAD;
231			`ZXB: o <= BIG ? {56'd0,alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
232			`ZXC: o <= BIG ? {48'd0,alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
233			`ZXH: o <= BIG ? {32'd0,alu_argA[31:0]} : 64'hDEADDEADDEADDEAD;
234			`COM: o <= ~alu_argA;
235			`SXB: o <= BIG ? {{56{alu_argA[7]}},alu_argA[7:0]} : 64'hDEADDEADDEADDEAD;
236			`SXC: o <= BIG ? {{48{alu_argA[15]}},alu_argA[15:0]} : 64'hDEADDEADDEADDEAD;
237			`SXH: o <= BIG ? {{32{alu_argA[31]}},alu_argA[31:0]} : 64'hDEADDEADDEADDEAD;
238			`default: o <= 64'hDEADDEADDEADDEAD;`
239			`endcase`
240			`R2:
241			`case(alu_fn)`
242			`CPUID:
243			`if (BIG)`
244			`case(alu_argA[4:0])`
245			`5'd0: o <= corenum;`
246			`5'd2: o <= "Finitron";`
247			`5'd3: o <= ""; // vendor ID`
248			`5'd4: o <= "64BitSS"; // class`
249			`5'd6: o <= "Thor"; // Name`
250			`5'd8: o <= "M1"; // model`
251			`5'd9: o <= "1234"; // serial num`
252			`5'd10: o <= FEATURES;`
253			`5'd11: o <= {32'd16384,32'd32768}; // Cache D,I`
254			`default: o <= 64'hDEADDEADDEADDEAD;`
255			`endcase`
256			`else o <= 64'hDEADDEADDEADDEAD;`
257			`REDOR: o <= BIG ? \|alu_argA : 64'hDEADDEADDEADDEAD;
258			`REDAND: o <= BIG ? &alu_argA : 64'hDEADDEADDEADDEAD;
259			`PAR: o <= BIG ? ^alu_argA : 64'hDEADDEADDEADDEAD;
260			`default: o <= 64'hDEADDEADDEADDEAD;`
261			`endcase`
262			`P: o <= p_out;
263			`/*`
264			`DOUBLE:
265			`if (BIG) begin`
266			`if (alu_fn[5:4]==2'b00)`
267			`case (alu_fn)`
268			`FMOV: o <= alu_argA;
269			`FNEG: o <= {~alu_argA[DBW-1],alu_argA[DBW-2:0]};
270			`FABS: o <= {1'b0,alu_argA[DBW-2:0]};
271			`FSIGN: if (DBW==64)
272			`o <= alu_argA[DBW-2:0]==0 ? {DBW{1'b0}} : {alu_argA[DBW-1],1'b0,{10{1'b1}},{52{1'b0}}};`
273			`else`
274			`o <= alu_argA[DBW-2:0]==0 ? {DBW{1'b0}} : {alu_argA[DBW-1],1'b0,{7{1'b1}},{23{1'b0}}};`
275			`FMAN: o <= alu_argA[(DBW==64?51:22):0];
276			`default: o <= 64'hDEADDEADDEADDEAD;`
277			`endcase`
278			`else`
279			`case (alu_fn)`
280			`FMOV: o <= alu_argA;
281			`FSNEG: o <= {~alu_argA[31],alu_argA[30:0]};
282			`FSABS: o <= {1'b0,alu_argA[30:0]};
283			`FSSIGN: o <= alu_argA[30:0]==0 ? {DBW{1'b0}} : {alu_argA[31],1'b0,{7{1'b1}},{23{1'b0}}};
284			`FSMAN: o <= alu_argA[22:0];
285			`default: o <= 64'hDEADDEADDEADDEAD;`
286			`endcase`
287			`end`
288			`else`
289			`o <= 64'hDEADDEADDEADDEAD;`
290			`*/`
291
292	37	robfinch	`ADDI,`ADDUI,`ADDUIS:
293	3	robfinch	`o <= alu_argA + alu_argI;`
294			`SUBI,`SUBUI:
295			`o <= alu_argA - alu_argI;`
296			`ANDI: o <= alu_argA & alu_argI;
297			`ORI: o <= alu_argA \| alu_argI;
298			`EORI: o <= alu_argA ^ alu_argI;
299			`LOGIC,`MLO:
300			`case(alu_fn)`
301			`AND: o <= alu_argA & alu_argB;
302			`ANDC: o <= alu_argA & ~alu_argB;
303			`OR: o <= alu_argA \| alu_argB;
304			`ORC: o <= alu_argA \| ~alu_argB;
305			`EOR: o <= alu_argA ^ alu_argB;
306			`NAND: o <= ~(alu_argA & alu_argB);
307			`NOR: o <= ~(alu_argA \| alu_argB);
308			`ENOR: o <= ~(alu_argA ^ alu_argB);
309			`default: o <= 64'd0;`
310			`endcase`
311			`BITI:
312			`begin`
313	9	robfinch	`o1[0] = andi_res==64'd0;`
314			`o1[1] = andi_res[DBW-1];`
315			`o1[2] = andi_res[0];`
316			`o1[3] = 1'b0;`
317			`o <= {16{o1}};`
318	3	robfinch	`end`
319	9	robfinch	`// TST`
320			`8'h00,8'h01,8'h02,8'h03,8'h04,8'h05,8'h06,8'h07,8'h08,8'h09,8'h0A,8'h0B,8'h0C,8'h0D,8'h0E,8'h0f:`
321	3	robfinch	`case(alu_fn)`
322			`6'd0: // TST - integer`
323			`begin`
324	9	robfinch	`o1[0] = alu_argA == 64'd0;`
325			`o1[1] = alu_argA[DBW-1];`
326			`o1[2] = 1'b0;`
327			`o1[3] = 1'b0;`
328			`o <= {16{o1}};`
329	3	robfinch	`end`
330			`ifdef FLOATING_POINT
331			`6'd1: // FSTST - float single`
332			`begin`
333	9	robfinch	`o1[0] = alu_argA[30:0]==31'd0; // + or - zero`
334			`o1[1] = alu_argA[31]; // signed less than`
335			`o1[2] = alu_argA[31];`
336	3	robfinch	`// unordered`
337	9	robfinch	`o1[3] = alu_argA[30:23]==8'hFF && alu_argA[22:0]!=23'd0; // NaN`
338			`o <= {16{o1}};`
339	3	robfinch	`end`
340			`6'd2: // FTST - float double`
341			`begin`
342	9	robfinch	`o1[0] = alu_argA[DBW-2:0]==63'd0; // + or - zero`
343			`o1[1] = alu_argA[DBW-1]; // signed less than`
344			`o1[2] = alu_argA[DBW-1];`
345	3	robfinch	`// unordered`
346			`if (DBW==64)`
347	9	robfinch	`o1[3] = alu_argA[62:52]==11'h7FF && alu_argA[51:0]!=52'd0; // NaN`
348	3	robfinch	`else`
349	9	robfinch	`o1[3] = 1'b0;`
350			`o <= {16{o1}};`
351	3	robfinch	`end`
352			`endif
353			`default: o <= 64'd0;`
354			`endcase`
355	9	robfinch	`// CMP`
356			`8'h10,8'h11,8'h12,8'h13,8'h14,8'h15,8'h16,8'h17,8'h18,8'h19,8'h1A,8'h1B,8'h1C,8'h1D,8'h1E,8'h1f:`
357			`begin`
358	3	robfinch	`case(alu_fn)`
359			`2'd0: begin // ICMP`
360	9	robfinch	`o1[0] = alu_argA == alu_argB;`
361	13	robfinch	`o1[1] = ($signed(alu_argA) < $signed(alu_argB));`
362	9	robfinch	`o1[2] = alu_argA < alu_argB;`
363			`o1[3] = 1'b0;`
364			`o <= {16{o1}};`
365	3	robfinch	`end`
366			`ifdef FLOATING_POINT
367			`2'd1: begin // FSCMP`
368	9	robfinch	`o1[0] = fseq;`
369			`o1[1] = fslt;`
370			`o1[2] = fslt1;`
371			`o1[3] = snanA \| snanB;`
372			`o <= {16{o1}};`
373	3	robfinch	`end`
374			`2'd2: begin // FCMP`
375	9	robfinch	`o1[0] = feq;`
376			`o1[1] = flt;`
377			`o1[2] = flt1;`
378			`o1[3] = nanA \| nanB;`
379			`o <= {16{o1}};`
380	3	robfinch	`end`
381			`endif
382			`default: o <= 64'hDEADDEADDEADDEAD;`
383			`endcase`
384			`end`
385	9	robfinch	`// CMPI`
386			`8'h20,8'h21,8'h22,8'h23,8'h24,8'h25,8'h26,8'h27,8'h28,8'h29,8'h2A,8'h2B,8'h2C,8'h2D,8'h2E,8'h2f:`
387			`begin`
388			`o1[0] = alu_argA == alu_argI;`
389	13	robfinch	`o1[1] = ($signed(alu_argA) < $signed(alu_argI));`
390	9	robfinch	`o1[2] = alu_argA < alu_argI;`
391			`o1[3] = 1'b0;`
392			`o <= {16{o1}};`
393	3	robfinch	`end`
394	13	robfinch	`LLA,
395	10	robfinch	`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`SB,`SC,`SH,`SW,`CAS,`LVB,`LVC,`LVH,`LVW,`STI,
396	13	robfinch	`LWS,`SWS,`STS,`STFND,`STCMP,`PUSH:
397	3	robfinch	`begin`
398			`o <= alu_argA + alu_argC + alu_argI;`
399			`end`
400	10	robfinch	`JMPI: o <= {alu_argA << alu_fn[1:0]} + alu_argC + alu_argI;
401	3	robfinch	`LBX,`LBUX,`SBX,
402			`LCX,`LCUX,`SCX,
403			`LHX,`LHUX,`SHX,
404	13	robfinch	`LWX,`SWX,`LLAX,
405	10	robfinch	`JMPIX:
406	3	robfinch	`case(alu_fn[1:0])`
407			`2'd0: o <= alu_argA + alu_argC + alu_argB;`
408			`2'd1: o <= alu_argA + alu_argC + {alu_argB,1'b0};`
409			`2'd2: o <= alu_argA + alu_argC + {alu_argB,2'b0};`
410			`2'd3: o <= alu_argA + alu_argC + {alu_argB,3'b0};`
411			`endcase`
412			`ifdef STACKOPS
413	10	robfinch	`PEA,`LINK: o <= alu_argA + alu_argC - 64'd8;
414	3	robfinch	`UNLINK: o <= alu_argA + alu_argC + 64'd8;
415			`POP: o <= alu_argA + alu_argC;
416			`endif
417			`JSR,`JSRS,`JSRZ,`SYS: o <= alu_pc + insnsz;
418			`INT: o <= alu_pc;
419			`MFSPR,`MTSPR: begin
420			`o <= alu_argA;`
421			`end`
422			`MUX: begin
423			`for (n = 0; n < DBW; n = n + 1)`
424			`o[n] <= alu_argA[n] ? alu_argB[n] : alu_argC[n];`
425			`end`
426			`BCD:
427			`if (BIG)`
428			`case(alu_fn)`
429			`BCDADD: o <= bcdao;
430			`BCDSUB: o <= bcdso;
431			`BCDMUL: o <= bcdmo;
432			`default: o <= 64'hDEADDEADDEADDEAD;`
433			`endcase`
434			`else`
435			`o <= 64'hDEADDEADDEADDEAD;`
436			`SHIFT: o <= BIG ? shfto : 64'hDEADDEADDEADDEAD;
437			`ifdef BITFIELDOPS
438			`BITFIELD: o <= BIG ? bf_out : 64'hDEADDEADDEADDEAD;
439			`endif
440	10	robfinch	`LOOP: o <= alu_argA > 0 ? alu_argA - 64'd1 : alu_argA;
441	37	robfinch	`CHKI: o <= ($signed(alu_argB) >= $signed(alu_argA)) && ($signed(alu_argB) < $signed(alu_argI));
442	3	robfinch	`default: o <= 64'hDEADDEADDEADDEAD;`
443			`endcase`
444			`end`
445
446			`// Generate done signal`
447			`always @*`
448			`case(alu_op)`
449			`RR:
450			`case(alu_fn)`
451			`MUL,`MULU: alu_done <= alu_mult_done;
452	13	robfinch	`DIV,`DIVU,`MOD,`MODU: alu_done <= alu_div_done;
453	3	robfinch	default: alu_done <= `TRUE;
454			`endcase`
455			`MULI,`MULUI: alu_done <= alu_mult_done;
456	13	robfinch	`DIVI,`DIVUI,`MODI,`MODUI: alu_done <= alu_div_done;
457	3	robfinch	default: alu_done <= `TRUE;
458			`endcase`
459
460	13	robfinch	`// Generate idle signal`
461			`always @*`
462			`case(alu_op)`
463			`RR:
464			`case(alu_fn)`
465			`MUL,`MULU: alu_idle <= alu_mult_idle;
466			`DIV,`DIVU,`MOD,`MODU: alu_idle <= alu_div_idle;
467			default: alu_idle <= `TRUE;
468			`endcase`
469			`MULI,`MULUI: alu_idle <= alu_mult_idle;
470			`DIVI,`DIVUI,`MODI,`MODUI: alu_idle <= alu_div_idle;
471			default: alu_idle <= `TRUE;
472			`endcase`
473
474	3	robfinch	`endmodule`

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