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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_dcachemem_1w1r.v] - Blame information for rev 45

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1 3 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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// Tri-ported data cache memory. (2 read, 1 write)
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//
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// ============================================================================
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//
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module Thor_dcachemem_1w1r(wclk, wce, wr, sel, wa, wd, rclk, rce, ra, o);
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parameter DBW=64;
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input wclk;
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input wce;
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input wr;
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input [DBW/8-1:0] sel;
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input [DBW-1:0] wa;
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input [DBW-1:0] wd;
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input rclk;
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input rce;
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input [DBW-1:0] ra;
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output [DBW-1:0] o;
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wire [DBW-1:0] o0, o1, o2;
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genvar n;
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generate
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for (n = 0; n < DBW/8; n = n + 1)
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begin : BRAMS
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        if (DBW==64)
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                syncRam2kx8_1rw1r uga (
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                        .wclk(wclk),
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                        .wce(wce),
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                        .wr(wr & sel[n]),
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                        .wa(wa[13:3]),
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                        .wd(wd[n*8+7:n*8]),
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                        .rclk(rclk),
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                        .rce(rce),
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                        .ra(ra[13:3]),
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                        .o(o[n*8+7:n*8])
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                );
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        else begin
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                syncRam2kx8_1rw1r uga (
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                        .wclk(wclk),
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                        .wce(wce),
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                        .wr(wr & sel[n]),
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                        .wa(wa[12:2]),
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                        .wd(wd[n*8+7:n*8]),
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                        .rclk(rclk),
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                        .rce(rce),
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                        .ra(ra[12:2]),
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                        .o(o0[n*8+7:n*8])
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                );
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    end
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end
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endgenerate
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assign o = o0;
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always @(posedge wclk)
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begin
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    if (wce & wr & |sel) begin
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        $display("*************************");
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        $display("*************************");
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        $display("Writing to DCACHE %h=%h", wa, wd);
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        $display("*************************");
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        $display("*************************");
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    end
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end
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endmodule
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module syncRam2kx8_1rw1r (wclk, wce, wr, wa, wd, rclk, rce, ra, o);
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input wclk;
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input wce;
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input wr;
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input [10:0] wa;
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input [7:0] wd;
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input rclk;
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input rce;
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input [10:0] ra;
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output [7:0] o;
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reg [7:0] mem [0:2047];
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reg [10:0] rra;
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integer n;
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initial begin
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    for (n = 0; n < 2048; n = n + 1)
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        mem[n] <= 0;
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end
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always @(posedge wclk)
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        if (wce & wr) mem[wa] <= wd;
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always @(posedge rclk)
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        if (rce) rra <= ra;
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assign o = mem[rra];
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endmodule

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