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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_defines.v] - Blame information for rev 21

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013,2015  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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// Thor Scaler
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//
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// ============================================================================
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//
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`ifndef THOR_DEFINES
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`define THOR_DEFINES    1'b1
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`define SIMULATION      1'b1
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`define SEGMENTATION    1'b1
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//`define SEGLIMITS       1'b1
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//`define STACKOPS        1'b1
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//`define UNLINKOP        1'b1
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//`define BITFIELDOPS     1'b1
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//`define FLOATING_POINT        1'b1
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`define STRINGOPS       1'b1
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//`define DEBUG_LOGIC     1'b1
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//`define THREEWAY    1'b1
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//`define TRAP_ILLEGALOPS 1'b1
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//`define PRIVCHKS        1'b1
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//`define PCHIST      1'b1      // Primarily for debugging the processor
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`define TRUE    1'b1
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`define FALSE   1'b0
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`define INV             1'b0
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`define VAL             1'b1
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`define ZERO            64'd0
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`define TST                     4'b0000
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`define CMP                     4'b0001
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`define CMPI            4'b0010
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`define BR                      4'b0011
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`define RR                      8'h40
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`define ADD                             6'h00
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`define SUB                             6'h01
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`define MUL                             6'h02
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`define DIV                             6'h03
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`define ADDU                    6'h04
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`define SUBU                    6'h05
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`define MULU                    6'h06
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`define DIVU                    6'h07
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`define _2ADDU                  6'h08
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`define _4ADDU                  6'h09
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`define _8ADDU                  6'h0A
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`define _16ADDU                 6'h0B
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`define MIN             6'h10
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`define MAX             6'h11
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`define MOD             6'h13
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`define MODU            6'h17
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`define R2          8'h41
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`define CPUID           4'h0
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`define REDOR           4'h1    // reduction or
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`define REDAND          4'h2    // reduction and
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`define PAR             4'h3    // parity
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`define P           8'h42
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`define PAND            6'd0
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`define POR             6'd1
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`define PEOR            6'd2
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`define PNAND           6'd3
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`define PNOR            6'd4
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`define PENOR           6'd5
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`define PANDC           6'd6
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`define PORC            6'd7
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`define BITI        8'h46
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`define ADDUIS      8'h47
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`define ADDI            8'h48
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`define SUBI            8'h49
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`define MULI            8'h4A
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`define DIVI            8'h4B
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`define ADDUI           8'h4C
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`define SUBUI           8'h4D
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`define MULUI           8'h4E
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`define DIVUI           8'h4F
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`define LOGIC           8'h50
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`define AND                             6'h0
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`define OR                              6'h1
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`define EOR                             6'h2
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`define NAND                    6'h3
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`define NOR                             6'h4
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`define ENOR                    6'h5
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`define ANDC                    6'h6
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`define ORC                             6'h7
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`define MLO         8'h51
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`define ANDI            8'h53
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`define ORI                     8'h54
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`define EORI            8'h55
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`define SHIFT           8'h58
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`define SHL                             6'h00
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`define SHR                             6'h01
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`define SHLU                    6'h02
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`define SHRU                    6'h03
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`define ROL                             6'h04
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`define ROR                             6'h05
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`define SHLI                    6'h10
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`define SHRI                    6'h11
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`define SHLUI                   6'h12
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`define SHRUI                   6'h13
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`define ROLI                    6'h14
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`define RORI                    6'h15
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`define MODI        8'h5B
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`define LEA         8'h5C
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`define MODUI       8'h5F
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`define LLA         8'h6A       // compute linear address
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`define _2ADDUI         8'h6B
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`define _4ADDUI         8'h6C
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`define _8ADDUI         8'h6D
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`define _16ADDUI        8'h6E
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`define LDI                     8'h6F
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`define MUX                     8'h72
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`define FSTAT           8'h73
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`define FRM                     8'h74
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`define FTX                     8'h75
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`define DOUBLE_R    8'h77
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`define FMOV            4'h00
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`define FTOI                4'h02
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`define ITOF                4'h03
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`define FNEG                    4'h04
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`define FABS                    4'h05
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`define FSIGN                   4'h06
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`define FMAN            4'h07
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`define FNABS           4'h08
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`define FSTAT           4'h0C
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`define FRM             4'h0D
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`define FLOAT           8'h78
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`define FCMP            6'h07
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`define FADD                    6'h08
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`define FSUB                    6'h09
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`define FMUL                    6'h0A
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`define FDIV                    6'h0B
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`define FCMPS           6'h17
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`define FADDS           6'h18
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`define FSUBS           6'h19
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`define FMULS           6'h1A
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`define FDIVS           6'h1B
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`define SINGLE_R    8'h79
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`define FMOVS           4'h00
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`define FTOIS               4'h02
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`define ITOFS               4'h03
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`define FNEGS                   4'h04
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`define FABSS                   4'h05
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`define FSIGNS                  4'h06
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`define FMANS           4'h07
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`define FNABSS          4'h08
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`define FTX             4'h0C
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`define FCX             4'h0D
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`define FEX             4'h0E
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`define FDX             4'h0F
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`define LB                      8'h80
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`define LBU                     8'h81
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`define LC                      8'h82
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`define LCU                     8'h83
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`define LH                      8'h84
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`define LHU                     8'h85
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`define LW                      8'h86
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`define LFS                     8'h87
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`define LFD                     8'h88
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`define LVWAR       8'h8B
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`define SWCR        8'h8C
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`define JMPI            8'h8D
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`define LWS                     8'h8E
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`define LCL                 8'h8F
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`define SB                      8'h90
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`define SC                      8'h91
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`define SH                      8'h92
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`define SW                      8'h93
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`define SFS                     8'h94
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`define SFD                     8'h95
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`define STI                     8'h96
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`define CAS                     8'h97
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`define STS             8'h98
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`define STMV        8'h99
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`define STCMP       8'h9A
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`define STFND       8'h9B
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`define LDIT10          8'h9C
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`define LDIS            8'h9D
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`define SWS                     8'h9E
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`define CACHE           8'h9F
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// Flow control Opcodes
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`define JSRZ        8'hA0
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`define JSRS        8'hA1
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`define JSR                     8'hA2
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`define RTS                     8'hA3
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`define LOOP            8'hA4
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`define SYS                     8'hA5
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`define INT                     8'hA6
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`define R           8'hA7
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`define MOV                         4'h0
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`define NEG                         4'h1
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`define NOT                         4'h2
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`define ABS             4'h3
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`define SGN             4'h4
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`define CNTLZ           4'h5
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`define CNTLO           4'h6
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`define CNTPOP          4'h7
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`define SXB             4'h8
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`define SXC             4'h9
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`define SXH             4'hA
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`define COM             4'hB
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`define ZXB             4'hC
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`define ZXC             4'hD
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`define ZXH             4'hE
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`define MFSPR           8'hA8
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`define MTSPR           8'hA9
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`define BITFIELD        8'hAA
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`define BFINS                   4'h0
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`define BFSET                   4'h1
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`define BFCLR                   4'h2
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`define BFCHG                   4'h3
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`define BFEXTU                  4'h4
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`define BFEXT                   4'h5
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`define BFINSI          4'd6
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`define MOVS            8'hAB
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// Uncached access instructions
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`define LVB                     8'hAC
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`define LVC                     8'hAD
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`define LVH                     8'hAE
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`define LVW                     8'hAF
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`define LBX                     8'hB0
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`define LBUX            8'hB1
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`define LCX                     8'hB2
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`define LCUX            8'hB3
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`define LHX                     8'hB4
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`define LHUX            8'hB5
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`define LWX                     8'hB6
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`define JMPIX       8'hB7
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`define LLAX        8'hB8
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`define SBX                     8'hC0
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`define SCX                     8'hC1
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`define SHX                     8'hC2
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`define SWX                     8'hC3
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`define STIX        8'hC6
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`define INC         8'hC7
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`define PUSH        8'hC8
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`define PEA         8'hC9
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`define POP         8'hCA
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`define LINK        8'hCB
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`define UNLINK      8'hCC
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`define TLB                     8'hF0
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`define TLB_NOP                 4'd0
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`define TLB_P                   4'd1
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`define TLB_RD                  4'd2
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`define TLB_WR                  4'd3
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`define TLB_WI                  4'd4
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`define TLB_EN                  4'd5
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`define TLB_DIS                 4'd6
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`define TLB_RDREG               4'd7
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`define TLB_WRREG               4'd8
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`define TLB_INVALL              4'd9
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`define NOP                     8'hF1
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`define TLBWired                4'h0
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`define TLBIndex                4'h1
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`define TLBRandom               4'h2
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`define TLBPageSize             4'h3
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`define TLBVirtPage             4'h4
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`define TLBPhysPage             4'h5
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`define TLBASID                 4'h7
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`define TLBDMissAdr             4'd8
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`define TLBIMissAdr             4'd9
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`define TLBPageTblAddr  4'd10
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`define TLBPageTblCtrl  4'd11
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`define RTS2        8'hF2
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`define RTE                     8'hF3
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`define RTI                     8'hF4
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`define BCD                     8'hF5
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`define BCDADD                  8'h00
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`define BCDSUB                  8'h01
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`define BCDMUL                  8'h02
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`define STP         8'hF6
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`define SYNC        8'hF7
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`define MEMSB           8'hF8   // synchronization barrier
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`define MEMDB           8'hF9   // data barrier
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`define CLI                     8'hFA
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`define SEI                     8'hFB
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`define RTD         8'hFC
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`define IMM                     8'hFF
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`define PREDC   3:0
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`define PREDR   7:4
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`define OPCODE  15:8
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`define RA              21:16
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`define RB              27:22
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`define INSTRUCTION_RA  21:16
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`define INSTRUCTION_RB  27:22
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`define INSTRUCTION_RC  33:28
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`define XTBL    4'd12
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`define EPC             4'd13
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`define IPC             4'd14
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// Special Registers
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`define PREGS           6'h0x
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`define CREGS                   6'h1x
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`define SREGS                   6'h2x
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`define PREGS_ALL               6'h30
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`define TICK                    6'h32
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`define LCTR                    6'h33
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`define ASID                    6'h36
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`define SR                              6'h37
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`define FPSCR           6'h38
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`define CLK_THROTTLE    6'h3F
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// exception types:
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`define EXC_NONE        4'd0
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`define EXC_HALT        4'd1
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`define EXC_TLBMISS     4'd2
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`define EXC_SEGV        4'd3
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`define EXC_INVALID     4'd4
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`define EXC_SYS         4'd5
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`define EXC_INT         4'd6
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`define EXC_OFL         4'd7
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`define EXC_DBE         4'd8            // databus error
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`define EXC_DBZ         4'd9            // divide by zero
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`define EXC_FLT     4'd10       // floating point exception
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`define EXC_DBG     4'd11
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`define EXC_PRIV    4'd12
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//
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// define PANIC types
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//
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`define PANIC_NONE              4'd0
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`define PANIC_FETCHBUFBEQ       4'd1
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`define PANIC_INVALIDISLOT      4'd2
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`define PANIC_MEMORYRACE        4'd3
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`define PANIC_IDENTICALDRAMS    4'd4
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`define PANIC_OVERRUN           4'd5
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`define PANIC_HALTINSTRUCTION   4'd6
363
`define PANIC_INVALIDMEMOP      4'd7
364
`define PANIC_INVALIDFBSTATE    4'd9
365
`define PANIC_INVALIDIQSTATE    4'd10
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`define PANIC_BRANCHBACK        4'd11
367
`define PANIC_BADTARGETID       4'd12
368
 
369
`define DRAMSLOT_AVAIL  2'b00
370
`define DRAMREQ_READY   2'b11
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372
`endif

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