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// ============================================================================
//        __
//   \\__/ o\    (C) 2013,2015  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
// Thor SuperScalar
// Execute combinational logic
//
// ============================================================================
//
wire [DBW-1:0] alu0_out, alu1_out;
wire alu0_done,alu1_done;
wire alu0_divByZero, alu1_divByZero;
 
Thor_alu #(.DBW(DBW),.BIG(1)) ualu0
(
    .corenum(corenum),
    .rst(rst),
    .clk(clk),
    .alu_ld(alu0_ld),
        .alu_op(alu0_op),
        .alu_fn(alu0_fn),
        .alu_argA(alu0_argA),
        .alu_argB(alu0_argB),
        .alu_argC(alu0_argC),
        .alu_argI(alu0_argI),
        .alu_pc(alu0_pc),
        .insnsz(alu0_insnsz),
        .o(alu0_out),
        .alu_done(alu0_done),
        .alu_divByZero(alu0_divByZero)
);
 
Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1
(
    .corenum(corenum),
    .rst(rst),
    .clk(clk),
    .alu_ld(alu1_ld),
        .alu_op(alu1_op),
        .alu_fn(alu1_fn),
        .alu_argA(alu1_argA),
        .alu_argB(alu1_argB),
        .alu_argC(alu1_argC),
        .alu_argI(alu1_argI),
        .alu_pc(alu1_pc),
        .insnsz(alu1_insnsz),
        .o(alu1_out),
        .alu_done(alu1_done),
    .alu_divByZero(alu1_divByZero)
);
 
function fnPredicate;
input [3:0] pr;
input [3:0] cond;
 
case(cond)
PF:             fnPredicate = 1'b0;
PT:             fnPredicate = 1'b1;
PEQ:    fnPredicate =  pr[0];
PNE:    fnPredicate = !pr[0];
PLE:    fnPredicate =  pr[0]|pr[1];
PGT:    fnPredicate = !(pr[0]|pr[1]);
PLT:    fnPredicate =  pr[1];
PGE:    fnPredicate = !pr[1];
PLEU:   fnPredicate =  pr[0]|pr[2];
PGTU:   fnPredicate = !(pr[0]|pr[2]);
PLTU:   fnPredicate =  pr[2];
PGEU:   fnPredicate = !pr[2];
default:        fnPredicate = 1'b1;
endcase
 
endfunction
 
wire alu0_cmtw = fnPredicate(alu0_pred, alu0_cond);
wire alu1_cmtw = fnPredicate(alu1_pred, alu1_cond);
 
always @*
begin
    alu0_cmt <= alu0_cmtw;
    alu1_cmt <= alu1_cmtw;
 
    alu0_bus <= alu0_cmtw ? alu0_out : alu0_argT;
    alu1_bus <= alu1_cmtw ? alu1_out : alu1_argT;
 
    alu0_v <= alu0_dataready;
        alu1_v <= alu1_dataready;
 
    alu0_id <= alu0_sourceid;
        alu1_id <= alu1_sourceid;
end
 
// Special flag nybble is used for INT and SYS instructions in order to turn off
// segmentation while the vector jump is taking place.
 
always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
    case(alu0_op)
    `JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
        alu0_misspc <= alu0_argA + alu0_argI;
    `LOOP,`SYNC:
        alu0_misspc <= alu0_pc + alu0_insnsz;
    `RTS,`RTS2:
        alu0_misspc <= alu0_argA + alu0_fn[3:0];
    `SYS,`INT:
        alu0_misspc <= {4'hF,alu0_argA + {alu0_argI[DBW-5:0],4'b0}};
    default:
        alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);
    endcase
 
always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)
    case(alu1_op)
    `JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
        alu1_misspc <= alu1_argA + alu1_argI;
    `LOOP,`SYNC:
        alu1_misspc <= alu1_pc + alu1_insnsz;
    `RTS,`RTS2:
        alu1_misspc <= alu1_argA + alu1_fn[3:0];
    `SYS,`INT:
        alu1_misspc <= {4'hF,alu1_argA + {alu1_argI[DBW-5:0],4'b0}};
    default:
        alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
    endcase
 
always @(dram0_fn or dram0_misspc or dram_bus)
    case (dram0_fn[1:0])
    2'd1:   jmpi_misspc <= {dram0_misspc[DBW-1:16],dram_bus[15:0]};
    2'd2:   jmpi_misspc <= (DBW==32) ? dram_bus[31:0] : {dram0_misspc[63:32],dram_bus[31:0]};
    2'd3:   jmpi_misspc <= dram_bus[DBW-1:0];
    default:    jmpi_misspc <= 32'h00000FA0;    // unimplemented instruction vector 
    endcase
/*
assign  alu0_misspc = (alu0_op == `JSR || alu0_op==`JSRS || alu0_op==`JSRZ ||
                       alu0_op==`RTS || alu0_op==`RTS2 || alu0_op == `RTE || alu0_op==`RTI || alu0_op==`LOOP) ? alu0_argA + alu0_argI :
                                          (alu0_op == `SYS || alu0_op==`INT) ? alu0_argA + {alu0_argI[DBW-5:0],4'b0} :
                                          (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI),
                alu1_misspc = (alu1_op == `JSR || alu1_op==`JSRS || alu1_op==`JSRZ ||
                               alu1_op==`RTS || alu1_op == `RTE || alu1_op==`RTI || alu1_op==`LOOP) ? alu1_argA + alu1_argI :
                                          (alu1_op == `SYS || alu1_op==`INT) ? alu1_argA + {alu1_argI[DBW-5:0],4'b0} :
                                          (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
*/
assign  alu0_exc =  (fnIsKMOnly(alu0_op) && !km) ? `EXC_PRIV :
                    (alu0_done && alu0_divByZero) ? `EXC_DBZ : `EXC_NONE;
 
//                      ? `EXC_NONE
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_NONE)     ? `EXC_NONE
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_CALL)     ? alu0_argB[`INSTRUCTION_S2]
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_MFSR)     ? `EXC_NONE
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_MTSR)     ? `EXC_NONE
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU1)     ? `EXC_INVALID
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU2)     ? `EXC_INVALID
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU3)     ? `EXC_INVALID
//                      : (alu0_argB[`INSTRUCTION_S1] == `SYS_EXC)      ? alu0_argB[`INSTRUCTION_S2]
//                      : `EXC_INVALID;
 
assign  alu1_exc =  (fnIsKMOnly(alu1_op) && !km) ? `EXC_PRIV :
                    (alu1_done && alu1_divByZero) ? `EXC_DBZ : `EXC_NONE;
 
//                      ? `EXC_NONE
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_NONE)     ? `EXC_NONE
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_CALL)     ? alu1_argB[`INSTRUCTION_S2]
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_MFSR)     ? `EXC_NONE
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_MTSR)     ? `EXC_NONE
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU1)     ? `EXC_INVALID
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU2)     ? `EXC_INVALID
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU3)     ? `EXC_INVALID
//                      : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC)      ? alu1_argB[`INSTRUCTION_S2]
//                      : `EXC_INVALID;
 
assign alu0_branchmiss = alu0_dataready &&
                   ((fnIsBranch(alu0_op))  ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
                  : (alu0_cmtw && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
                     alu0_op==`SYS || alu0_op==`INT ||
                  alu0_op==`RTS || alu0_op==`RTS2 || alu0_op==`RTD || alu0_op == `RTE || alu0_op==`RTI || ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
 
assign alu1_branchmiss = alu1_dataready &&
                   ((fnIsBranch(alu1_op))  ? ((alu1_cmt && !alu1_bt) || (!alu1_cmt && alu1_bt))
                  : (alu1_cmtw && (alu1_op==`SYNC || alu1_op == `JSR || alu1_op == `JSRS || alu1_op == `JSRZ ||
                     alu1_op==`SYS || alu1_op==`INT ||
                  alu1_op==`RTS || alu1_op==`RTS2 || alu1_op==`RTD || alu1_op == `RTE || alu1_op==`RTI || ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
 
assign  branchmiss = (alu0_branchmiss | alu1_branchmiss | mem_stringmiss | jmpi_miss),
        misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),
        missid = (jmpi_miss ? dram0_id : mem_stringmiss ? dram0_id : alu0_branchmiss ? alu0_sourceid : alu1_sourceid);
 
`ifdef FLOATING_POINT
 wire fp0_exception;
 
fpUnit ufp0
(
        .rst(rst_i),
        .clk(clk),
        .ce(1'b1),
        .op(fp0_op),
        .fn(fp0_fn),
        .ld(fp0_ld),
        .a(fp0_argA),
        .b(fp0_argB),
        .o(fp0_bus),
        .exception(fp0_exception)
);
 
reg [7:0] cnt;
always @(posedge clk)
if (rst_i)
    cnt <= 8'h00;
else begin
    if (fp0_ld)
           cnt <= 8'h00;
    else begin
           if (cnt < 8'hff)
                  cnt <= cnt + 8'd1;
    end
end
 
always @*
begin
        case(fp0_op)
        `FLOAT:
        case(fp0_fn)
        `FCMP,`FCMPS:    fp0_done = 1'b1;        // These ops are done right away
        `FADD,`FSUB,`FMUL,`FADDS,`FSUBS,`FMULS:
                               fp0_done = cnt > 8'd4;
        `FDIV:                fp0_done = cnt > 8'h70;
        `FDIVS:                fp0_done = cnt > 8'h37;
        default:       fp0_done = 1'b1;
        endcase
        `SINGLE_R:
        case(fp0_fn)
        `FNEGS,`FABSS,`FSIGNS,`FMOVS,
        `FNABSS,`FMANS:
                                    fp0_done = 1'b1;        // These ops are done right away
        `FTOIS,`ITOFS:    fp0_done = cnt > 8'd1;
        default:       fp0_done = 1'b1;
        endcase
        `DOUBLE_R:
        case(fp0_fn)
        `FMOV,`FNEG,`FABS,`FNABS,`FSIGN,`FMAN:
                                    fp0_done = 1'b1;        // These ops are done right away
        `FTOI,`ITOF:    fp0_done = cnt > 8'd1;
        default:       fp0_done = 1'b1;
        endcase
        default:       fp0_done = 1'b1;
        endcase
end
 
assign fp0_cmt = fnPredicate(fp0_pred, fp0_cond);
assign fp0_exc = fp0_exception ? 8'd242 : 8'd0;
 
assign  fp0_v = fp0_dataready;
assign  fp0_id = fp0_sourceid;
`endif
 

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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_execute_combo.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	3	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`//`
22			`// Thor SuperScalar`
23			`// Execute combinational logic`
24			`//`
25			`// ============================================================================`
26			`//`
27			`wire [DBW-1:0] alu0_out, alu1_out;`
28			`wire alu0_done,alu1_done;`
29			`wire alu0_divByZero, alu1_divByZero;`
30
31			`Thor_alu #(.DBW(DBW),.BIG(1)) ualu0`
32			`(`
33			`.corenum(corenum),`
34			`.rst(rst),`
35			`.clk(clk),`
36			`.alu_ld(alu0_ld),`
37			`.alu_op(alu0_op),`
38			`.alu_fn(alu0_fn),`
39			`.alu_argA(alu0_argA),`
40			`.alu_argB(alu0_argB),`
41			`.alu_argC(alu0_argC),`
42			`.alu_argI(alu0_argI),`
43			`.alu_pc(alu0_pc),`
44			`.insnsz(alu0_insnsz),`
45			`.o(alu0_out),`
46			`.alu_done(alu0_done),`
47			`.alu_divByZero(alu0_divByZero)`
48			`);`
49
50			`Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1`
51			`(`
52			`.corenum(corenum),`
53			`.rst(rst),`
54			`.clk(clk),`
55			`.alu_ld(alu1_ld),`
56			`.alu_op(alu1_op),`
57			`.alu_fn(alu1_fn),`
58			`.alu_argA(alu1_argA),`
59			`.alu_argB(alu1_argB),`
60			`.alu_argC(alu1_argC),`
61			`.alu_argI(alu1_argI),`
62			`.alu_pc(alu1_pc),`
63			`.insnsz(alu1_insnsz),`
64			`.o(alu1_out),`
65			`.alu_done(alu1_done),`
66			`.alu_divByZero(alu1_divByZero)`
67			`);`
68
69			`function fnPredicate;`
70			`input [3:0] pr;`
71			`input [3:0] cond;`
72
73			`case(cond)`
74			`PF: fnPredicate = 1'b0;`
75			`PT: fnPredicate = 1'b1;`
76			`PEQ: fnPredicate = pr[0];`
77			`PNE: fnPredicate = !pr[0];`
78			`PLE: fnPredicate = pr[0]\|pr[1];`
79			`PGT: fnPredicate = !(pr[0]\|pr[1]);`
80			`PLT: fnPredicate = pr[1];`
81			`PGE: fnPredicate = !pr[1];`
82			`PLEU: fnPredicate = pr[0]\|pr[2];`
83			`PGTU: fnPredicate = !(pr[0]\|pr[2]);`
84			`PLTU: fnPredicate = pr[2];`
85			`PGEU: fnPredicate = !pr[2];`
86			`default: fnPredicate = 1'b1;`
87			`endcase`
88
89			`endfunction`
90
91			`wire alu0_cmtw = fnPredicate(alu0_pred, alu0_cond);`
92			`wire alu1_cmtw = fnPredicate(alu1_pred, alu1_cond);`
93
94			`always @*`
95			`begin`
96			`alu0_cmt <= alu0_cmtw;`
97			`alu1_cmt <= alu1_cmtw;`
98
99			`alu0_bus <= alu0_cmtw ? alu0_out : alu0_argT;`
100			`alu1_bus <= alu1_cmtw ? alu1_out : alu1_argT;`
101
102			`alu0_v <= alu0_dataready;`
103			`alu1_v <= alu1_dataready;`
104
105			`alu0_id <= alu0_sourceid;`
106			`alu1_id <= alu1_sourceid;`
107			`end`
108
109			`// Special flag nybble is used for INT and SYS instructions in order to turn off`
110			`// segmentation while the vector jump is taking place.`
111
112			`always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)`
113			`case(alu0_op)`
114			`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
115			`alu0_misspc <= alu0_argA + alu0_argI;`
116			`LOOP,`SYNC:
117			`alu0_misspc <= alu0_pc + alu0_insnsz;`
118			`RTS,`RTS2:
119			`alu0_misspc <= alu0_argA + alu0_fn[3:0];`
120			`SYS,`INT:
121			`alu0_misspc <= {4'hF,alu0_argA + {alu0_argI[DBW-5:0],4'b0}};`
122			`default:`
123			`alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);`
124			`endcase`
125
126			`always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)`
127			`case(alu1_op)`
128			`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI:
129			`alu1_misspc <= alu1_argA + alu1_argI;`
130			`LOOP,`SYNC:
131			`alu1_misspc <= alu1_pc + alu1_insnsz;`
132			`RTS,`RTS2:
133			`alu1_misspc <= alu1_argA + alu1_fn[3:0];`
134			`SYS,`INT:
135			`alu1_misspc <= {4'hF,alu1_argA + {alu1_argI[DBW-5:0],4'b0}};`
136			`default:`
137			`alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);`
138			`endcase`
139	10	robfinch
140			`always @(dram0_fn or dram0_misspc or dram_bus)`
141			`case (dram0_fn[1:0])`
142			`2'd1: jmpi_misspc <= {dram0_misspc[DBW-1:16],dram_bus[15:0]};`
143			`2'd2: jmpi_misspc <= (DBW==32) ? dram_bus[31:0] : {dram0_misspc[63:32],dram_bus[31:0]};`
144			`2'd3: jmpi_misspc <= dram_bus[DBW-1:0];`
145			`default: jmpi_misspc <= 32'h00000FA0; // unimplemented instruction vector`
146			`endcase`
147	3	robfinch	`/*`
148			assign alu0_misspc = (alu0_op == `JSR \|\| alu0_op==`JSRS \|\| alu0_op==`JSRZ \|\|
149			alu0_op==`RTS \|\| alu0_op==`RTS2 \|\| alu0_op == `RTE \|\| alu0_op==`RTI \|\| alu0_op==`LOOP) ? alu0_argA + alu0_argI :
150			(alu0_op == `SYS \|\| alu0_op==`INT) ? alu0_argA + {alu0_argI[DBW-5:0],4'b0} :
151			`(alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI),`
152			alu1_misspc = (alu1_op == `JSR \|\| alu1_op==`JSRS \|\| alu1_op==`JSRZ \|\|
153			alu1_op==`RTS \|\| alu1_op == `RTE \|\| alu1_op==`RTI \|\| alu1_op==`LOOP) ? alu1_argA + alu1_argI :
154			(alu1_op == `SYS \|\| alu1_op==`INT) ? alu1_argA + {alu1_argI[DBW-5:0],4'b0} :
155			`(alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);`
156			`*/`
157			assign alu0_exc = (fnIsKMOnly(alu0_op) && !km) ? `EXC_PRIV :
158			(alu0_done && alu0_divByZero) ? `EXC_DBZ : `EXC_NONE;
159
160			// ? `EXC_NONE
161			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_NONE) ? `EXC_NONE
162			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_CALL) ? alu0_argB[`INSTRUCTION_S2]
163			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_MFSR) ? `EXC_NONE
164			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_MTSR) ? `EXC_NONE
165			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU1) ? `EXC_INVALID
166			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU2) ? `EXC_INVALID
167			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU3) ? `EXC_INVALID
168			// : (alu0_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu0_argB[`INSTRUCTION_S2]
169			// : `EXC_INVALID;
170
171			assign alu1_exc = (fnIsKMOnly(alu1_op) && !km) ? `EXC_PRIV :
172			(alu1_done && alu1_divByZero) ? `EXC_DBZ : `EXC_NONE;
173
174			// ? `EXC_NONE
175			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_NONE) ? `EXC_NONE
176			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_CALL) ? alu1_argB[`INSTRUCTION_S2]
177			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_MFSR) ? `EXC_NONE
178			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_MTSR) ? `EXC_NONE
179			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU1) ? `EXC_INVALID
180			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU2) ? `EXC_INVALID
181			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU3) ? `EXC_INVALID
182			// : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu1_argB[`INSTRUCTION_S2]
183			// : `EXC_INVALID;
184
185			`assign alu0_branchmiss = alu0_dataready &&`
186			`((fnIsBranch(alu0_op)) ? ((alu0_cmt && !alu0_bt) \|\| (!alu0_cmt && alu0_bt))`
187			: (alu0_cmtw && (alu0_op==`SYNC \|\| alu0_op == `JSR \|\| alu0_op == `JSRS \|\| alu0_op == `JSRZ \|\|
188			alu0_op==`SYS \|\| alu0_op==`INT \|\|
189	10	robfinch	alu0_op==`RTS \|\| alu0_op==`RTS2 \|\| alu0_op==`RTD \|\| alu0_op == `RTE \|\| alu0_op==`RTI \|\| ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
190	3	robfinch
191			`assign alu1_branchmiss = alu1_dataready &&`
192			`((fnIsBranch(alu1_op)) ? ((alu1_cmt && !alu1_bt) \|\| (!alu1_cmt && alu1_bt))`
193			: (alu1_cmtw && (alu1_op==`SYNC \|\| alu1_op == `JSR \|\| alu1_op == `JSRS \|\| alu1_op == `JSRZ \|\|
194			alu1_op==`SYS \|\| alu1_op==`INT \|\|
195	10	robfinch	alu1_op==`RTS \|\| alu1_op==`RTS2 \|\| alu1_op==`RTD \|\| alu1_op == `RTE \|\| alu1_op==`RTI \|\| ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
196	3	robfinch
197	10	robfinch	`assign branchmiss = (alu0_branchmiss \| alu1_branchmiss \| mem_stringmiss \| jmpi_miss),`
198			`misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),`
199			`missid = (jmpi_miss ? dram0_id : mem_stringmiss ? dram0_id : alu0_branchmiss ? alu0_sourceid : alu1_sourceid);`
200	3	robfinch
201			`ifdef FLOATING_POINT
202			`wire fp0_exception;`
203
204			`fpUnit ufp0`
205			`(`
206			`.rst(rst_i),`
207			`.clk(clk),`
208			`.ce(1'b1),`
209			`.op(fp0_op),`
210			`.fn(fp0_fn),`
211			`.ld(fp0_ld),`
212			`.a(fp0_argA),`
213			`.b(fp0_argB),`
214			`.o(fp0_bus),`
215			`.exception(fp0_exception)`
216			`);`
217
218			`reg [7:0] cnt;`
219			`always @(posedge clk)`
220			`if (rst_i)`
221			`cnt <= 8'h00;`
222			`else begin`
223			`if (fp0_ld)`
224			`cnt <= 8'h00;`
225			`else begin`
226			`if (cnt < 8'hff)`
227			`cnt <= cnt + 8'd1;`
228			`end`
229			`end`
230
231			`always @*`
232			`begin`
233			`case(fp0_op)`
234			`FLOAT:
235			`case(fp0_fn)`
236			`FCMP,`FCMPS: fp0_done = 1'b1; // These ops are done right away
237			`FADD,`FSUB,`FMUL,`FADDS,`FSUBS,`FMULS:
238			`fp0_done = cnt > 8'd4;`
239			`FDIV: fp0_done = cnt > 8'h70;
240			`FDIVS: fp0_done = cnt > 8'h37;
241			`default: fp0_done = 1'b1;`
242			`endcase`
243			`SINGLE_R:
244			`case(fp0_fn)`
245			`FNEGS,`FABSS,`FSIGNS,`FMOVS,
246			`FNABSS,`FMANS:
247			`fp0_done = 1'b1; // These ops are done right away`
248			`FTOIS,`ITOFS: fp0_done = cnt > 8'd1;
249			`default: fp0_done = 1'b1;`
250			`endcase`
251			`DOUBLE_R:
252			`case(fp0_fn)`
253			`FMOV,`FNEG,`FABS,`FNABS,`FSIGN,`FMAN:
254			`fp0_done = 1'b1; // These ops are done right away`
255			`FTOI,`ITOF: fp0_done = cnt > 8'd1;
256			`default: fp0_done = 1'b1;`
257			`endcase`
258			`default: fp0_done = 1'b1;`
259			`endcase`
260			`end`
261
262			`assign fp0_cmt = fnPredicate(fp0_pred, fp0_cond);`
263			`assign fp0_exc = fp0_exception ? 8'd242 : 8'd0;`
264
265			`assign fp0_v = fp0_dataready;`
266			`assign fp0_id = fp0_sourceid;`
267			`endif
268