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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_icachemem.v] - Blame information for rev 12

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1 3 robfinch 
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013,2015  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Thor SuperScalar
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//
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// ============================================================================
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//
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module Thor_icachemem(wclk, wce, wr, wa, wd, rclk, pc, insn);
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parameter DBW=64;
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input wclk;
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input wce;
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input wr;
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input [DBW-1:0] wa;
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input [DBW-1:0] wd;
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input rclk;
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input [DBW-1:0] pc;
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output reg [127:0] insn;
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wire [127:0] mem0a;
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wire [127:0] mem1a;
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reg [14:0] pcp16;
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generate
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begin : gen1
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        if (DBW==32) begin
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        syncRam2kx32_1w1r uicm0a0 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b00),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pc[14:4]),
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            .o(mem0a[31:0])
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        );
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        syncRam2kx32_1w1r uicm0a1 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b01),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pc[14:4]),
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            .o(mem0a[63:32])
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        );
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        syncRam2kx32_1w1r uicm0a2 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b10),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pc[14:4]),
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            .o(mem0a[95:64])
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        );
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        syncRam2kx32_1w1r uicm0a3 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b11),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pc[14:4]),
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            .o(mem0a[127:96])
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        );
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        syncRam2kx32_1w1r uicm1a0 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b00),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pcp16[14:4]),
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            .o(mem1a[31:0])
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        );
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        syncRam2kx32_1w1r uicm1a1 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b01),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pcp16[14:4]),
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            .o(mem1a[63:32])
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        );
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        syncRam2kx32_1w1r uicm1a2 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b10),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pcp16[14:4]),
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            .o(mem1a[95:64])
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        );
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        syncRam2kx32_1w1r uicm1a3 (
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            .wclk(wclk),
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            .wce(wce && wa[3:2]==2'b11),
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            .wr({4{wr}}),
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            .wa(wa[14:4]),
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            .wd(wd),
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            .rclk(rclk),
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            .rce(1'b1),
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            .ra(pcp16[14:4]),
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            .o(mem1a[127:96])
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        );
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    end
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end
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endgenerate
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always @(pc)
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        pcp16 <= pc[14:0] + 15'd16;
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wire [127:0] insn0 = mem0a;
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wire [127:0] insn1 = mem1a;
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always @(pc or insn0 or insn1)
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case(pc[3:0])
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4'd0:   insn <= insn0;
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4'd1:   insn <= {insn1[7:0],insn0[127:8]};
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4'd2:   insn <= {insn1[15:0],insn0[127:16]};
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4'd3:   insn <= {insn1[23:0],insn0[127:24]};
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4'd4:   insn <= {insn1[31:0],insn0[127:32]};
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4'd5:   insn <= {insn1[39:0],insn0[127:40]};
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4'd6:   insn <= {insn1[47:0],insn0[127:48]};
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4'd7:   insn <= {insn1[55:0],insn0[127:56]};
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4'd8:   insn <= {insn1[63:0],insn0[127:64]};
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4'd9:   insn <= {insn1[71:0],insn0[127:72]};
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4'd10:  insn <= {insn1[79:0],insn0[127:80]};
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4'd11:  insn <= {insn1[87:0],insn0[127:88]};
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4'd12:  insn <= {insn1[95:0],insn0[127:96]};
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4'd13:  insn <= {insn1[103:0],insn0[127:104]};
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4'd14:  insn <= {insn1[111:0],insn0[127:112]};
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4'd15:  insn <= {insn1[119:0],insn0[127:120]};
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endcase
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endmodule

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