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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2007,2014,2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// fpZLUnit.v
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// - zero latency floating point unit
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// - instructions can execute in a single cycle without
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// a clock
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// - parameterized width
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// - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// fabs - get absolute value of number
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// fnabs - get negative absolute value of number
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// fneg - negate number
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// fmov - copy input to output
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// fsign - get sign of number (set number to +1,0, or -1)
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// fman - get mantissa (set exponent to zero)
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// fcmp
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//
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// ============================================================================
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`include "..\Thor_defines.v"
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module fpZLUnit
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#(parameter WID=32)
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(
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input [7:0] op,
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input [5:0] fn,
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input [WID:1] a,
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input [WID:1] b, // for fcmp
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output reg [WID:1] o,
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output nanx
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);
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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wire nanxd,nanxs;
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wire single = op==`SINGLE_R;
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wire az = single ? a[31:1]==0 : WID==64 ? a[63:1]==0 : 0;
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wire [3:0] cmp_o,cmps_o;
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assign nanx = op==`FLOAT && fn==`FCMPS ? nanxs : nanxd;
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fp_cmp_unit #(64) u1 (.a(a), .b(b), .o(cmp_o), .nanx(nanxd) );
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fp_cmp_unit #(32) u2 (.a(a[32:1]), .b(b[32:1]), .o(cmps_o), .nanx(nanxs) );
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always @(op,a,cmp_o,az,cmps_o)
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case (op)
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`DOUBLE_R:
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if (WID==64)
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case(fn)
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`FABS: o <= {1'b0,a[63:1]}; // fabs
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`FNABS: o <= {1'b1,a[63:1]}; // fnabs
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`FNEG: o <= {~a[64],a[63:1]}; // fneg
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`FMOV: o <= a; // fmov
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`FSIGN: o <= az ? 0 : {a[64],1'b0,{10{1'b1}},{52{1'b0}}}; // fsign
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`FMAN: o <= {a[64],1'b0,{10{1'b1}},a[51:1]}; // fman
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default: o <= 0;
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endcase
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`SINGLE_R:
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case(fn)
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`FABSS: o <= {1'b0,a[31:1]}; // fabs
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`FNABSS: o <= {1'b1,a[31:1]}; // fnabs
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`FNEGS: o <= {~a[32],a[31:1]}; // fneg
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`FMOVS: o <= a; // fmov
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`FSIGNS: o <= az ? 0 : {a[32],1'b0,{7{1'b1}},{23{1'b0}}}; // fsign
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`FMANS: o <= {a[32],1'b0,{7{1'b1}},a[23:1]}; // fman
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default: o <= 0;
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endcase
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`FLOAT:
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case(fn)
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`FCMP: o <= cmp_o;
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`FCMPS: o <= cmps_o;
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default: o <= 0;
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endcase
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default: o <= 0;
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endcase
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endmodule
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