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[/] [thor/] [trunk/] [rtl/] [verilog/] [memory/] [syncRam2kx32_1w1r.v] - Blame information for rev 18

Line No.	Rev	Author	Line
1	8	robfinch	`module syncRam2kx32_1w1r (wclk, wce, wr, wa, wd, rclk, rce, ra, o);`
2			`input wclk;`
3			`input wce;`
4			`input [3:0] wr;`
5			`input [10:0] wa;`
6			`input [31:0] wd;`
7			`input rclk;`
8			`input rce;`
9			`input [10:0] ra;`
10			`output [31:0] o;`
11
12			`syncRam2kx8_1rw1r um0 (`
13			`.wclk(wclk),`
14			`.wce(wce),`
15			`.wr(wr[0]),`
16			`.wa(wa),`
17			`.wd(wd[7:0]),`
18			`.rclk(rclk),`
19			`.rce(1'b1),`
20			`.ra(ra),`
21			`.o(o[7:0])`
22			`);`
23			`syncRam2kx8_1rw1r um1 (`
24			`.wclk(wclk),`
25			`.wce(wce),`
26			`.wr(wr[1]),`
27			`.wa(wa),`
28			`.wd(wd[15:8]),`
29			`.rclk(rclk),`
30			`.rce(1'b1),`
31			`.ra(ra),`
32			`.o(o[15:8])`
33			`);`
34			`syncRam2kx8_1rw1r um2 (`
35			`.wclk(wclk),`
36			`.wce(wce),`
37			`.wr(wr[2]),`
38			`.wa(wa),`
39			`.wd(wd[23:16]),`
40			`.rclk(rclk),`
41			`.rce(1'b1),`
42			`.ra(ra),`
43			`.o(o[23:16])`
44			`);`
45			`syncRam2kx8_1rw1r um3 (`
46			`.wclk(wclk),`
47			`.wce(wce),`
48			`.wr(wr[3]),`
49			`.wa(wa),`
50			`.wd(wd[31:24]),`
51			`.rclk(rclk),`
52			`.rce(1'b1),`
53			`.ra(ra),`
54			`.o(o[31:24])`
55			`);`
56
57			`endmodule`