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[/] [thor/] [trunk/] [rtl/] [verilog/] [memory/] [syncRam2kx8_1rw2r.v] - Blame information for rev 41

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Line No. Rev Author Line
1 8 robfinch 
/* ===============================================================
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        (C) 2006  Robert Finch
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        All rights reserved.
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        rob@birdcomputer.ca
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        syncRam2kx8_1rw1r.v
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        This source code is free for use and modification for
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        non-commercial or evaluation purposes, provided this
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        copyright statement and disclaimer remains present in
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        the file.
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        If you do modify the code, please state the origin and
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        note that you have modified the code.
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        NO WARRANTY.
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        THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
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        ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
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        the entire risk of using the Work.
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        IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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        ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
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        WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
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        RELATIONSHIP WITH THE AUTHOR.
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        IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
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        TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
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        WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
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        TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
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        OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
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        AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
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        FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
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        USE.
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=============================================================== */
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`define SYNTHESIS
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`define VENDOR_XILINX
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`define SPARTAN3
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module syncRam2kx8_1rw2r(
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        input wrst,
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        input wclk,
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        input wce,
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        input we,
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        input [10:0] wadr,
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        input [7:0] i,
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        output [7:0] wo,
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        input rrst,
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        input rclk,
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        input rce,
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        input [10:0] radr0,
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        output [7:0] o0,
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        input [10:0] radr1,
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        output [7:0] o1
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);
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`ifdef SYNTHESIS
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`ifdef VENDOR_XILINX
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`ifdef SPARTAN3
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        RAMB16_S9_S9 ram0(
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                .CLKA(wclk), .ADDRA(wadr), .DIA(i), .DIPA(^i), .DOA(wo), .ENA(wce), .WEA(we), .SSRA(wrst),
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                .CLKB(rclk), .ADDRB(radr0), .DIB(8'hFF), .DIPB(1'b1), .DOB(o0), .ENB(rce), .WEB(1'b0), .SSRB(rrst)  );
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        RAMB16_S9_S9 ram0(
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                .CLKA(wclk), .ADDRA(wadr), .DIA(i), .DIPA(^i), .DOA(wo), .ENA(wce), .WEA(we), .SSRA(wrst),
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                .CLKB(rclk), .ADDRB(radr1), .DIB(8'hFF), .DIPB(1'b1), .DOB(o1), .ENB(rce), .WEB(1'b0), .SSRB(rrst)  );
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`endif
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`endif
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`endif
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endmodule

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