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[/] [thor/] [trunk/] [software/] [boot_tb/] [boot.asm] - Blame information for rev 12

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; ============================================================================
;        __
;   \\__/ o\    (C) 2015  Robert Finch, Stratford
;    \  __ /    All rights reserved.
;     \/_//     robfinch@finitron.ca
;       ||
;
;
; This source file is free software: you can redistribute it and/or modify
; it under the terms of the GNU Lesser General Public License as published
; by the Free Software Foundation, either version 3 of the License, or
; (at your option) any later version.
;
; This source file is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program.  If not, see .
;
; ============================================================================
;
 
SCRSZ   EQU     2604
CR      EQU     0x0D            ;ASCII equates
LF      EQU     0x0A
TAB     EQU     0x09
CTRLC   EQU     0x03
BS              EQU     0x07
CTRLH   EQU     0x08
CTRLI   EQU     0x09
CTRLJ   EQU     0x0A
CTRLK   EQU     0x0B
CTRLM   EQU 0x0D
CTRLS   EQU     0x13
CTRLX   EQU     0x18
XON             EQU     0x11
XOFF    EQU     0x13
ESC             EQU     0x1B
 
SC_LSHIFT       EQU             $12
SC_RSHIFT       EQU             $59
SC_KEYUP        EQU             $F0
SC_EXTEND       EQU             $E0
SC_CTRL         EQU             $14
SC_ALT          EQU             $11
SC_DEL          EQU             $71             ; extend
SC_LCTRL        EQU             $58
SC_NUMLOCK      EQU             $77
SC_SCROLLLOCK   EQU     $7E
SC_CAPSLOCK     EQU             $58
 
E_BadFuncno    EQU       1
BIOS_E_Timeout EQU       2
E_Unsupported  EQU       3
 
BIOS_STACKTOP           EQU             $3bf8
INT_STACK                       EQU             $37f8
VIDEO_BIOS_STACKTOP     EQU             $3ff8
 
IOBASE_ADDR     EQU             0xFFD00000
IOLMT           EQU             0x100000
LEDS            EQU             0xC0600
TEXTSCR         EQU             0x00000
TEXTSCR2        EQU             0x10000
TEXTREG         EQU             0xA0000
TEXTREG2        EQU             0xA0040
TEXT_COLS       EQU             0x0
TEXT_ROWS       EQU             0x2
TEXT_CURPOS     EQU             0x16
KEYBD           EQU             0xC0000
 
PIC_IE          EQU             0xC0FC8
PIC_ES          EQU             0xC0FE0
PIC_ESR         EQU             0xC0FE8         ; edge sense reset
 
KeyState1       EQU             $2008
KeyState2       EQU             $2009
KeybdLEDs       EQU             $200A
KeybdWaitFlag   EQU     $200B
 
CursorX         EQU             $2030
CursorY         EQU             $2032
VideoPos        EQU             $2034
NormAttr        EQU             $2036
Vidregs         EQU             $2040
Vidptr          EQU             $2044
EscState        EQU             $2048
Textrows        EQU             $204A
Textcols        EQU             $204C
 
                bss
                org             $4000
 
Milliseconds    dw              0
 
rxfull     EQU      1
Uart_ms         db      0
Uart_txxonoff   db      0
Uart_rxhead     dc      0
Uart_rxtail     dc      0
Uart_rxflow     db      0
Uart_rxrts      db      0
Uart_rxdtr      db      0
Uart_rxxon      db      0
Uart_foff       dc      0
Uart_fon        dc      0
Uart_txrts      db      0
Uart_txdtr      db      0
Uart_txxon      db      0
Uart_rxfifo     fill.b  512,0
 
NUMWKA          fill.b  64,0
 
        code 17 bits
        org             $FFFF8000
 
cold_start:
 
                ; Initialize segment registers for flat model
                mtspr   cs,r0
                ldis    cs.lmt,#-1              ; maximum
                mtspr   zs,r0
                ldis    zs.lmt,#-1
                mtspr   ds,r0
                ldis    ds.lmt,#-1
                mtspr   es,r0
                ldis    es.lmt,#-1
                mtspr   fs,r0
                ldis    fs.lmt,#-1
                mtspr   gs,r0
                ldis    gs.lmt,#-1
                ldis    hs,#IOBASE_ADDR
                ldis    hs.lmt,#IOLMT
 
                ; set SS:SP
                mtspr   ss,r0
                ldis    ss.lmt,#$4000
                ldi             r31,#$03ef8             ; initialize kernel SP
                ldi             r27,#$03bf8             ; initialize SP
 
                ; switch processor to full speed
                stp             #$FFFF
 
                ; set interrupt table at $0000
                ldis    c12,#0
 
                ; set all vectors to the uninitialized interrupt vector
;               mov             r4,r0
;               ldis    lc,#255         ; 256 vectors to set
;su1:
;               ldi             r1,#uii_jmp
;               mov             r2,r4
;               bsr             set_vector      ; trashes r2,r3
;               addui   r4,r4,#1
;               loop    su1
 
                ; setup break vector
                ldi             r1,#brk_jmp
                ldi             r2,#0
                bsr             set_vector
 
                ; setup Video BIOS vector
                ldi             r1,#vb_jmp
                ldi             r2,#10
                bsr             set_vector
 
                ; setup NMI vector
                ldi             r1,#nmi_jmp
                ldi             r2,#254
                bsr             set_vector
 
                ; setup MSI vector
                sh              r0,Milliseconds
                ldi             r1,#msi_jmp
                ldi             r2,#193
                bsr             set_vector
 
                ; setup IRQ vector
                ldi             r1,#tms_jmp
                ldi             r2,#194
                bsr             set_vector
 
                ; setup data bus error vector
                ldi             r1,#dbe_jmp
                ldi             r2,#251
                bsr             set_vector
 
                ; Initialize PIC
                ldi             r1,#%00111              ; time slice interrupt is edge sensitive
                sh              r1,hs:PIC_ES
                ldi             r1,#%00111              ; enable time slice interrupt, msi, nmi
                sh              r1,hs:PIC_IE
 
                mov             r1,r0
                mov             r2,r0
                mov             r3,r0
                mov             r4,r0
                mov             r5,r0
 
                ldi             r1,#1
                sc              r1,hs:LEDS
 
                tlbwrreg DMA,r0                         ; clear TLB miss registers
                tlbwrreg IMA,r0
                ldi                     r1,#2                   ; 2 wired registers
                tlbwrreg        Wired,r1
                ldi                     r1,#$2                  ; 64kiB page size
                tlbwrreg        PageSize,r1
 
                ; setup the first translation
                ; virtual page $FFFF0000 maps to physical page $FFFF0000
                ; This places the BIOS ROM at $FFFFxxxx in the memory map
                ldi                     r1,#$80000101   ; ASID=zero, G=1,valid=1
                tlbwrreg        ASID,r1
                ldi                     r1,#$0FFFF
                tlbwrreg        VirtPage,r1
                tlbwrreg        PhysPage,r1
                tlbwrreg        Index,r0                ; select way #0
                tlbwi                                           ; write to TLB entry group #0 with hold registers
 
                ; setup second translation
                ; virtual page 0 maps to physical page 0
                ldi                     r1,#$80000101   ; ASID=zero, G=1,valid=1
                tlbwrreg        ASID,r1
                tlbwrreg        VirtPage,r0
                tlbwrreg        PhysPage,r0
                ldi                     r1,#8                   ; select way#1
                tlbwrreg        Index,r1
                tlbwi                                           ; write to TLB entry group #0 with hold registers
 
                ; turn on the TLB
;               tlben
 
                ; enable maskable interrupts
                ; Interrupts also are not enabled until an RTI instruction is executed.
                ; there will likely be a timer interrupt outstanding so this
                ; should go to the timer IRQ.
                cli
 
                ; now globally enable interrupts using the RTI instruction, this will also
                ; switch to core to application/user mode.
                ldis    c14,#j1                 ; c14 contains RTI return address
                sync
;               rti
j1:
                ldi             r1,#2
                sc              r1,hs:LEDS
                sb              r0,EscState
                bsr             SerialInit
                bsr             Debugger
                ldi             r2,#msgStartup
                ldis    lc,#msgStartupEnd-msgStartup-1
j3:
;               lbu             r1,[r2]
;               addui   r2,r2,#1
;               tst             p0,r1
;p0.eq  br              j2
;               bsr             SerialPutChar
;               loop    j3
j2:
                bsr             VideoInit
                bsr             VBClearScreen
;               bsr             VBClearScreen2
                ldi             r1,#3
                sc              r1,hs:LEDS
                mov             r1,r0
                mov             r2,r0
                ldi             r6,#2           ; Set Cursor Pos
                sys             #10
                ldi             r1,#6
                sc              r1,hs:LEDS
                bsr             alphabet
                ldi             r1,#msgStartup
                ldi             r6,#$14
                sys             #10
;               bsr             VBDisplayString
                ldi             r5,#TEXTSCR
.0001:
.0002:
                bsr             KeybdGetCharWait
                bsr             VBDisplayChar
                cmpi    p0,r1,#CR
p0.ne   br              .0002
                bsr             VBAsciiToScreen
                ori             r1,r1,#%000000111_111111111_00_00000000
                sh              r1,hs:[r5]
                addui   r5,r5,#4
                br              .0001
 
msgStartup:
                byte    "Thor Test System Starting...",CR,LF,0
msgStartupEnd:
 
bad_ram:
                ldi             r1,#'B'
                bsr             VBAsciiToScreen
                ori             r1,r1,#%011000000_111111111_00_00000000
                sh              r1,hs:TEXTSCR+16
.bram1: br              .bram1
 
;------------------------------------------------------------------------------
; alphabet:
;
; Display the alphabet across the top of the screen.
;------------------------------------------------------------------------------
 
alphabet:
                addui   sp,sp,#-8
                sws             c1,[sp]                 ; store off return address
                ldi             r5,#'A'                 ; the first char
                ldi             r3,#TEXTSCR             ; screen address
                ldis    lc,#25                  ; 25 chars
.0001:
                mov             r1,r5                   ; r1 = ascii letter
                bsr             VBAsciiToScreen ; r1 = screen char
                lhu             r2,NormAttr             ; r2 = attribute
                or              r1,r1,r2                ; r1 = screen char + attribute
                sh              r1,hs:[r3]              ; store r1 to screen
                addui   r5,r5,#1                ; increment to next char
                addui   r3,r3,#4                ; increment to next screen loc
                loop    .0001                   ; loop back
                lws             c1,[sp]                 ; restore return address
                addui   sp,sp,#8
                rts
 
;------------------------------------------------------------------------------
; Set interrupt vector
;
; Parameters:
;       r1 = address of jump code
;       r2 = vector number to set
; Trashes: r2,r3
;------------------------------------------------------------------------------
 
set_vector:
                mfspr   r3,c12                  ; get base address of interrupt table
                _16addu r2,r2,r3
                lh              r3,cs:[r1]
                sh              r3,zs:[r2]
                lh              r3,cs:4[r1]
                sh              r3,zs:4[r2]
                lh              r3,cs:8[r1]
                sh              r3,zs:8[r2]
                lh              r3,cs:12[r1]
                sh              r3,zs:12[r2]
                rts
 
.include "video.asm"
.include "keyboard.asm"
.include "serial.asm"
.include "debugger.asm"
 
;------------------------------------------------------------------------------
; Uninitialized interrupt
;------------------------------------------------------------------------------
uii_rout:
                sync
                ldi             r31,#INT_STACK-16
                sw              r1,[r31]
                sws             hs,8[r31]
 
                ; set I/O segment
                ldis    hs,#$FFD00000
 
                ; update on-screen IRQ live indicator
                ldi             r1,#'U'|%011000000_111111111_00_00000000
                sh              r1,hs:TEXTSCR+320
 
                ; restore regs and return
                lw              r1,[r31]
                lws             hs,8[r31]
                sync
                rti
 
;------------------------------------------------------------------------------
; Non-maskable interrupt routine.
;
;------------------------------------------------------------------------------
;
nmi_rout:
                sync
                ldi             r31,#INT_STACK-16
                sw              r1,[r31]
                sws             hs,8[r31]
 
                ; set I/O segment
                ldis    hs,#$FFD00000
 
                ldi             r1,#16
                sc              r1,hs:LEDS
 
                ; reset the edge sense circuit to re-enable interrupts
                ldi             r1,#0
                sh              r1,hs:PIC_ESR
 
                ; update on-screen IRQ live indicator
                lh              r1,hs:TEXTSCR+324
                addui   r1,r1,#1
                sh              r1,hs:TEXTSCR+324
 
                ; restore regs and return
                lw              r1,[r31]
                lws             hs,8[r31]
                sync
                rti
 
;------------------------------------------------------------------------------
; Millisecond (1024 Hz) interrupt routine.
;
;------------------------------------------------------------------------------
;
msi_rout:
                sync
                ldi             r31,#INT_STACK-16
                sw              r1,[r31]
                sws             hs,8[r31]
 
                ; set I/O segment
                ldis    hs,#$FFD00000
 
                ldi             r1,#24
                sc              r1,hs:LEDS
 
                ; reset the edge sense circuit to re-enable interrupts
                ldi             r1,#1
                sh              r1,hs:PIC_ESR
 
                ; update milliseconds
                lh              r1,Milliseconds
                addui   r1,r1,#1
                sh              r1,Milliseconds
 
                ; restore regs and return
                lw              r1,[r31]
                lws             hs,8[r31]
                sync
                rti
 
;------------------------------------------------------------------------------
; Time Slice IRQ routine.
;
;
;------------------------------------------------------------------------------
;
tms_rout:
                sync
                ldi             r31,#INT_STACK-16
                sw              r1,[r31]
                sws             hs,8[r31]
 
                ; set I/O segment
                ldis    hs,#$FFD00000
 
                ldi             r1,#32
                sc              r1,hs:LEDS
 
                ; reset the edge sense circuit to re-enable interrupts
                ldi             r1,#2
                sh              r1,hs:PIC_ESR
 
                ; update on-screen IRQ live indicator
                lh              r1,hs:TEXTSCR+328
                addui   r1,r1,#1
                sh              r1,hs:TEXTSCR+328
 
                ; restore regs and return
                lw              r1,[r31]
                lws             hs,8[r31]
                sync
                rti
 
;------------------------------------------------------------------------------
; Time Slice IRQ routine.
;
;
;------------------------------------------------------------------------------
;
dbe_rout:
                sync
                ldi             r31,#INT_STACK-24
                sw              r1,[r31]
                sws             hs,8[r31]
                sw              r5,16[r31]
 
                ; set I/O segment
                ldis    hs,#$FFD00000
 
                ldi             r1,#64
                sc              r1,hs:LEDS
 
                ; reset the bus error circuit to re-enable interrupts
                sh              r0,hs:$CFFE0
 
                ; update on-screen DBE indicator
                ldi             r1,'D'|%011000000_000000110_0000000000
                sh              r1,hs:TEXTSCR+320
 
                ; Advance the program to the next address
                mfspr   r5,c14
                bsr             DBGGetInsnLength
                addu    r1,r5,r1
                mtspr   c14,r1
 
                ; restore regs and return
                lw              r1,[r31]
                lws             hs,8[r31]
                lw              r5,16[r31]
                sync
                rti
 
;------------------------------------------------------------------------------
; Break routine
;
; Currently uses only registers in case memory is bad, and sets an indicator
; on-screen.
;------------------------------------------------------------------------------
;
brk_rout:
                sync
                ldi             r1,#'B'
                bsr             VBAsciiToScreen
                ori             r1,r1,#|%011000000_111111111_00_00000000
                sh              r1,zs:$FFD10140
                ldi             r1,#'R'
                bsr             VBAsciiToScreen
                ori             r1,r1,#|%011000000_111111111_00_00000000
                sh              r1,zs:$FFD10144
                ldi             r1,#'K'
                bsr             VBAsciiToScreen
                ori             r1,r1,#|%011000000_111111111_00_00000000
                sh              r1,zs:$FFD10148
                ldi             r2,#10
                ldi             r6,#0
                mfspr   r5,c13
                bsr             DisplayAddr
brk_lockup:
                br              brk_lockup[c0]
 
; code snippet to jump to the break routine, copied to the break vector
;
; vector table jumps
;
                align   4
brk_jmp:        jmp             brk_rout[c0]
                align   4
tms_jmp:        jmp             tms_rout[c0]
                align   4
msi_jmp:        jmp             msi_rout[c0]
                align   4
nmi_jmp:        jmp             nmi_rout[c0]
                align   4
uii_jmp:        jmp             uii_rout[c0]
                align   4
vb_jmp:         jmp             VideoBIOSCall[c0]
                align   4
ser_jmp:        jmp             SerialIRQ[c0]
                align   4
dbe_jmp:        jmp             dbe_rout[c0]
 
;------------------------------------------------------------------------------
; Reset Point
;------------------------------------------------------------------------------
 
                org             $FFFFEFF0
                jmp             cold_start[C15]
 
extern my_main : 24
 

Line No.	Rev	Author	Line
1	5	robfinch
2			`; ============================================================================`
3			`; __`
4			`; \\__/ o\ (C) 2015 Robert Finch, Stratford`
5			`; \ __ / All rights reserved.`
6			`; \/_// robfinch@finitron.ca`
7			`; \|\|`
8			`;`
9			`;`
10			`; This source file is free software: you can redistribute it and/or modify`
11			`; it under the terms of the GNU Lesser General Public License as published`
12			`; by the Free Software Foundation, either version 3 of the License, or`
13			`; (at your option) any later version.`
14			`;`
15			`; This source file is distributed in the hope that it will be useful,`
16			`; but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`; GNU General Public License for more details.`
19			`;`
20			`; You should have received a copy of the GNU General Public License`
21			`; along with this program. If not, see .`
22			`;`
23			`; ============================================================================`
24			`;`
25	12	robfinch
26			`SCRSZ EQU 2604`
27	5	robfinch	`CR EQU 0x0D ;ASCII equates`
28			`LF EQU 0x0A`
29			`TAB EQU 0x09`
30			`CTRLC EQU 0x03`
31			`BS EQU 0x07`
32			`CTRLH EQU 0x08`
33			`CTRLI EQU 0x09`
34			`CTRLJ EQU 0x0A`
35			`CTRLK EQU 0x0B`
36			`CTRLM EQU 0x0D`
37			`CTRLS EQU 0x13`
38			`CTRLX EQU 0x18`
39			`XON EQU 0x11`
40			`XOFF EQU 0x13`
41			`ESC EQU 0x1B`
42
43			`SC_LSHIFT EQU $12`
44			`SC_RSHIFT EQU $59`
45			`SC_KEYUP EQU $F0`
46			`SC_EXTEND EQU $E0`
47			`SC_CTRL EQU $14`
48			`SC_ALT EQU $11`
49			`SC_DEL EQU $71 ; extend`
50			`SC_LCTRL EQU $58`
51			`SC_NUMLOCK EQU $77`
52			`SC_SCROLLLOCK EQU $7E`
53			`SC_CAPSLOCK EQU $58`
54
55	12	robfinch	`E_BadFuncno EQU 1`
56			`BIOS_E_Timeout EQU 2`
57			`E_Unsupported EQU 3`
58
59			`BIOS_STACKTOP EQU $3bf8`
60			`INT_STACK EQU $37f8`
61			`VIDEO_BIOS_STACKTOP EQU $3ff8`
62
63	5	robfinch	`IOBASE_ADDR EQU 0xFFD00000`
64			`IOLMT EQU 0x100000`
65			`LEDS EQU 0xC0600`
66			`TEXTSCR EQU 0x00000`
67			`TEXTSCR2 EQU 0x10000`
68			`TEXTREG EQU 0xA0000`
69	12	robfinch	`TEXTREG2 EQU 0xA0040`
70	5	robfinch	`TEXT_COLS EQU 0x0`
71			`TEXT_ROWS EQU 0x2`
72			`TEXT_CURPOS EQU 0x16`
73			`KEYBD EQU 0xC0000`
74
75			`PIC_IE EQU 0xC0FC8`
76			`PIC_ES EQU 0xC0FE0`
77			`PIC_ESR EQU 0xC0FE8 ; edge sense reset`
78
79			`KeyState1 EQU $2008`
80			`KeyState2 EQU $2009`
81			`KeybdLEDs EQU $200A`
82			`KeybdWaitFlag EQU $200B`
83
84			`CursorX EQU $2030`
85			`CursorY EQU $2032`
86			`VideoPos EQU $2034`
87			`NormAttr EQU $2036`
88			`Vidregs EQU $2040`
89			`Vidptr EQU $2044`
90			`EscState EQU $2048`
91			`Textrows EQU $204A`
92			`Textcols EQU $204C`
93
94	12	robfinch	`bss`
95			`org $4000`
96
97			`Milliseconds dw 0`
98
99			`rxfull EQU 1`
100			`Uart_ms db 0`
101			`Uart_txxonoff db 0`
102			`Uart_rxhead dc 0`
103			`Uart_rxtail dc 0`
104			`Uart_rxflow db 0`
105			`Uart_rxrts db 0`
106			`Uart_rxdtr db 0`
107			`Uart_rxxon db 0`
108			`Uart_foff dc 0`
109			`Uart_fon dc 0`
110			`Uart_txrts db 0`
111			`Uart_txdtr db 0`
112			`Uart_txxon db 0`
113			`Uart_rxfifo fill.b 512,0`
114
115			`NUMWKA fill.b 64,0`
116
117			`code 17 bits`
118	5	robfinch	`org $FFFF8000`
119
120			`cold_start:`
121
122			`; Initialize segment registers for flat model`
123			`mtspr cs,r0`
124			`ldis cs.lmt,#-1 ; maximum`
125			`mtspr zs,r0`
126			`ldis zs.lmt,#-1`
127			`mtspr ds,r0`
128			`ldis ds.lmt,#-1`
129			`mtspr es,r0`
130			`ldis es.lmt,#-1`
131			`mtspr fs,r0`
132			`ldis fs.lmt,#-1`
133			`mtspr gs,r0`
134			`ldis gs.lmt,#-1`
135			`ldis hs,#IOBASE_ADDR`
136			`ldis hs.lmt,#IOLMT`
137
138			`; set SS:SP`
139			`mtspr ss,r0`
140			`ldis ss.lmt,#$4000`
141	12	robfinch	`ldi r31,#$03ef8 ; initialize kernel SP`
142			`ldi r27,#$03bf8 ; initialize SP`
143	5	robfinch
144			`; switch processor to full speed`
145			`stp #$FFFF`
146
147			`; set interrupt table at $0000`
148			`ldis c12,#0`
149
150			`; set all vectors to the uninitialized interrupt vector`
151	12	robfinch	`; mov r4,r0`
152			`; ldis lc,#255 ; 256 vectors to set`
153			`;su1:`
154			`; ldi r1,#uii_jmp`
155			`; mov r2,r4`
156			`; bsr set_vector ; trashes r2,r3`
157			`; addui r4,r4,#1`
158			`; loop su1`
159	5	robfinch
160			`; setup break vector`
161			`ldi r1,#brk_jmp`
162			`ldi r2,#0`
163			`bsr set_vector`
164
165	12	robfinch	`; setup Video BIOS vector`
166			`ldi r1,#vb_jmp`
167			`ldi r2,#10`
168			`bsr set_vector`
169
170	5	robfinch	`; setup NMI vector`
171			`ldi r1,#nmi_jmp`
172			`ldi r2,#254`
173			`bsr set_vector`
174
175	12	robfinch	`; setup MSI vector`
176			`sh r0,Milliseconds`
177			`ldi r1,#msi_jmp`
178			`ldi r2,#193`
179			`bsr set_vector`
180
181	5	robfinch	`; setup IRQ vector`
182			`ldi r1,#tms_jmp`
183			`ldi r2,#194`
184			`bsr set_vector`
185
186	12	robfinch	`; setup data bus error vector`
187			`ldi r1,#dbe_jmp`
188			`ldi r2,#251`
189			`bsr set_vector`
190
191	5	robfinch	`; Initialize PIC`
192	12	robfinch	`ldi r1,#%00111 ; time slice interrupt is edge sensitive`
193	5	robfinch	`sh r1,hs:PIC_ES`
194	12	robfinch	`ldi r1,#%00111 ; enable time slice interrupt, msi, nmi`
195	5	robfinch	`sh r1,hs:PIC_IE`
196
197			`mov r1,r0`
198			`mov r2,r0`
199			`mov r3,r0`
200			`mov r4,r0`
201			`mov r5,r0`
202
203			`ldi r1,#1`
204	12	robfinch	`sc r1,hs:LEDS`
205	5	robfinch
206			`tlbwrreg DMA,r0 ; clear TLB miss registers`
207			`tlbwrreg IMA,r0`
208			`ldi r1,#2 ; 2 wired registers`
209			`tlbwrreg Wired,r1`
210			`ldi r1,#$2 ; 64kiB page size`
211			`tlbwrreg PageSize,r1`
212
213			`; setup the first translation`
214			`; virtual page $FFFF0000 maps to physical page $FFFF0000`
215			`; This places the BIOS ROM at $FFFFxxxx in the memory map`
216			`ldi r1,#$80000101 ; ASID=zero, G=1,valid=1`
217			`tlbwrreg ASID,r1`
218			`ldi r1,#$0FFFF`
219			`tlbwrreg VirtPage,r1`
220			`tlbwrreg PhysPage,r1`
221			`tlbwrreg Index,r0 ; select way #0`
222			`tlbwi ; write to TLB entry group #0 with hold registers`
223
224			`; setup second translation`
225			`; virtual page 0 maps to physical page 0`
226			`ldi r1,#$80000101 ; ASID=zero, G=1,valid=1`
227			`tlbwrreg ASID,r1`
228			`tlbwrreg VirtPage,r0`
229			`tlbwrreg PhysPage,r0`
230			`ldi r1,#8 ; select way#1`
231			`tlbwrreg Index,r1`
232			`tlbwi ; write to TLB entry group #0 with hold registers`
233
234			`; turn on the TLB`
235			`; tlben`
236
237			`; enable maskable interrupts`
238			`; Interrupts also are not enabled until an RTI instruction is executed.`
239			`; there will likely be a timer interrupt outstanding so this`
240			`; should go to the timer IRQ.`
241			`cli`
242
243			`; now globally enable interrupts using the RTI instruction, this will also`
244			`; switch to core to application/user mode.`
245			`ldis c14,#j1 ; c14 contains RTI return address`
246	12	robfinch	`sync`
247			`; rti`
248	5	robfinch	`j1:`
249			`ldi r1,#2`
250	12	robfinch	`sc r1,hs:LEDS`
251	5	robfinch	`sb r0,EscState`
252	12	robfinch	`bsr SerialInit`
253			`bsr Debugger`
254			`ldi r2,#msgStartup`
255			`ldis lc,#msgStartupEnd-msgStartup-1`
256			`j3:`
257			`; lbu r1,[r2]`
258			`; addui r2,r2,#1`
259			`; tst p0,r1`
260			`;p0.eq br j2`
261			`; bsr SerialPutChar`
262			`; loop j3`
263			`j2:`
264	5	robfinch	`bsr VideoInit`
265	12	robfinch	`bsr VBClearScreen`
266			`; bsr VBClearScreen2`
267	5	robfinch	`ldi r1,#3`
268	12	robfinch	`sc r1,hs:LEDS`
269			`mov r1,r0`
270			`mov r2,r0`
271			`ldi r6,#2 ; Set Cursor Pos`
272			`sys #10`
273	5	robfinch	`ldi r1,#6`
274	12	robfinch	`sc r1,hs:LEDS`
275			`bsr alphabet`
276			`ldi r1,#msgStartup`
277			`ldi r6,#$14`
278			`sys #10`
279			`; bsr VBDisplayString`
280	5	robfinch	`ldi r5,#TEXTSCR`
281			`.0001:`
282	12	robfinch	`.0002:`
283	5	robfinch	`bsr KeybdGetCharWait`
284	12	robfinch	`bsr VBDisplayChar`
285			`cmpi p0,r1,#CR`
286			`p0.ne br .0002`
287			`bsr VBAsciiToScreen`
288			`ori r1,r1,#%000000111_111111111_00_00000000`
289	5	robfinch	`sh r1,hs:[r5]`
290			`addui r5,r5,#4`
291			`br .0001`
292
293			`msgStartup:`
294			`byte "Thor Test System Starting...",CR,LF,0`
295	12	robfinch	`msgStartupEnd:`
296	5	robfinch
297			`bad_ram:`
298			`ldi r1,#'B'`
299	12	robfinch	`bsr VBAsciiToScreen`
300	5	robfinch	`ori r1,r1,#%011000000_111111111_00_00000000`
301			`sh r1,hs:TEXTSCR+16`
302			`.bram1: br .bram1`
303
304			`;------------------------------------------------------------------------------`
305	12	robfinch	`; alphabet:`
306			`;`
307			`; Display the alphabet across the top of the screen.`
308			`;------------------------------------------------------------------------------`
309
310			`alphabet:`
311			`addui sp,sp,#-8`
312			`sws c1,[sp] ; store off return address`
313			`ldi r5,#'A' ; the first char`
314			`ldi r3,#TEXTSCR ; screen address`
315			`ldis lc,#25 ; 25 chars`
316			`.0001:`
317			`mov r1,r5 ; r1 = ascii letter`
318			`bsr VBAsciiToScreen ; r1 = screen char`
319			`lhu r2,NormAttr ; r2 = attribute`
320			`or r1,r1,r2 ; r1 = screen char + attribute`
321			`sh r1,hs:[r3] ; store r1 to screen`
322			`addui r5,r5,#1 ; increment to next char`
323			`addui r3,r3,#4 ; increment to next screen loc`
324			`loop .0001 ; loop back`
325			`lws c1,[sp] ; restore return address`
326			`addui sp,sp,#8`
327			`rts`
328
329			`;------------------------------------------------------------------------------`
330	5	robfinch	`; Set interrupt vector`
331			`;`
332			`; Parameters:`
333			`; r1 = address of jump code`
334			`; r2 = vector number to set`
335			`; Trashes: r2,r3`
336			`;------------------------------------------------------------------------------`
337
338			`set_vector:`
339			`mfspr r3,c12 ; get base address of interrupt table`
340			`_16addu r2,r2,r3`
341			`lh r3,cs:[r1]`
342			`sh r3,zs:[r2]`
343			`lh r3,cs:4[r1]`
344			`sh r3,zs:4[r2]`
345			`lh r3,cs:8[r1]`
346			`sh r3,zs:8[r2]`
347			`lh r3,cs:12[r1]`
348			`sh r3,zs:12[r2]`
349			`rts`
350
351	12	robfinch	`.include "video.asm"`
352			`.include "keyboard.asm"`
353			`.include "serial.asm"`
354			`.include "debugger.asm"`
355	5	robfinch
356			`;------------------------------------------------------------------------------`
357	12	robfinch	`; Uninitialized interrupt`
358	5	robfinch	`;------------------------------------------------------------------------------`
359	12	robfinch	`uii_rout:`
360	5	robfinch	`sync`
361	12	robfinch	`ldi r31,#INT_STACK-16`
362			`sw r1,[r31]`
363			`sws hs,8[r31]`
364	5	robfinch
365	12	robfinch	`; set I/O segment`
366			`ldis hs,#$FFD00000`
367	5	robfinch
368	12	robfinch	`; update on-screen IRQ live indicator`
369			`ldi r1,#'U'\|%011000000_111111111_00_00000000`
370			`sh r1,hs:TEXTSCR+320`
371	5	robfinch
372	12	robfinch	`; restore regs and return`
373			`lw r1,[r31]`
374			`lws hs,8[r31]`
375			`sync`
376			`rti`
377	5	robfinch
378			`;------------------------------------------------------------------------------`
379	12	robfinch	`; Non-maskable interrupt routine.`
380	5	robfinch	`;`
381			`;------------------------------------------------------------------------------`
382			`;`
383	12	robfinch	`nmi_rout:`
384			`sync`
385			`ldi r31,#INT_STACK-16`
386			`sw r1,[r31]`
387			`sws hs,8[r31]`
388	5	robfinch
389	12	robfinch	`; set I/O segment`
390			`ldis hs,#$FFD00000`
391	5	robfinch
392	12	robfinch	`ldi r1,#16`
393			`sc r1,hs:LEDS`
394	5	robfinch
395	12	robfinch	`; reset the edge sense circuit to re-enable interrupts`
396			`ldi r1,#0`
397			`sh r1,hs:PIC_ESR`
398	5	robfinch
399	12	robfinch	`; update on-screen IRQ live indicator`
400			`lh r1,hs:TEXTSCR+324`
401			`addui r1,r1,#1`
402			`sh r1,hs:TEXTSCR+324`
403	5	robfinch
404	12	robfinch	`; restore regs and return`
405			`lw r1,[r31]`
406			`lws hs,8[r31]`
407			`sync`
408			`rti`
409	5	robfinch
410			`;------------------------------------------------------------------------------`
411	12	robfinch	`; Millisecond (1024 Hz) interrupt routine.`
412	5	robfinch	`;`
413			`;------------------------------------------------------------------------------`
414			`;`
415	12	robfinch	`msi_rout:`
416			`sync`
417			`ldi r31,#INT_STACK-16`
418			`sw r1,[r31]`
419			`sws hs,8[r31]`
420	5	robfinch
421	12	robfinch	`; set I/O segment`
422			`ldis hs,#$FFD00000`
423	5	robfinch
424	12	robfinch	`ldi r1,#24`
425			`sc r1,hs:LEDS`
426	5	robfinch
427	12	robfinch	`; reset the edge sense circuit to re-enable interrupts`
428			`ldi r1,#1`
429			`sh r1,hs:PIC_ESR`
430	5	robfinch
431	12	robfinch	`; update milliseconds`
432			`lh r1,Milliseconds`
433			`addui r1,r1,#1`
434			`sh r1,Milliseconds`
435	5	robfinch
436			`; restore regs and return`
437	12	robfinch	`lw r1,[r31]`
438			`lws hs,8[r31]`
439			`sync`
440	5	robfinch	`rti`
441
442			`;------------------------------------------------------------------------------`
443	12	robfinch	`; Time Slice IRQ routine.`
444	5	robfinch	`;`
445	12	robfinch	`;`
446	5	robfinch	`;------------------------------------------------------------------------------`
447			`;`
448	12	robfinch	`tms_rout:`
449			`sync`
450			`ldi r31,#INT_STACK-16`
451			`sw r1,[r31]`
452			`sws hs,8[r31]`
453	5	robfinch
454			`; set I/O segment`
455			`ldis hs,#$FFD00000`
456
457	12	robfinch	`ldi r1,#32`
458			`sc r1,hs:LEDS`
459
460	5	robfinch	`; reset the edge sense circuit to re-enable interrupts`
461	12	robfinch	`ldi r1,#2`
462	5	robfinch	`sh r1,hs:PIC_ESR`
463
464			`; update on-screen IRQ live indicator`
465	12	robfinch	`lh r1,hs:TEXTSCR+328`
466	5	robfinch	`addui r1,r1,#1`
467	12	robfinch	`sh r1,hs:TEXTSCR+328`
468	5	robfinch
469			`; restore regs and return`
470	12	robfinch	`lw r1,[r31]`
471			`lws hs,8[r31]`
472			`sync`
473	5	robfinch	`rti`
474
475			`;------------------------------------------------------------------------------`
476			`; Time Slice IRQ routine.`
477			`;`
478			`;`
479			`;------------------------------------------------------------------------------`
480			`;`
481	12	robfinch	`dbe_rout:`
482			`sync`
483			`ldi r31,#INT_STACK-24`
484			`sw r1,[r31]`
485			`sws hs,8[r31]`
486			`sw r5,16[r31]`
487	5	robfinch
488			`; set I/O segment`
489			`ldis hs,#$FFD00000`
490
491	12	robfinch	`ldi r1,#64`
492			`sc r1,hs:LEDS`
493	5	robfinch
494	12	robfinch	`; reset the bus error circuit to re-enable interrupts`
495			`sh r0,hs:$CFFE0`
496	5	robfinch
497	12	robfinch	`; update on-screen DBE indicator`
498			`ldi r1,'D'\|%011000000_000000110_0000000000`
499			`sh r1,hs:TEXTSCR+320`
500

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