URL https://opencores.org/ocsvn/thor/thor/trunk

Subversion Repositories thor

[/] [thor/] [trunk/] [software/] [emuThor/] [source/] [insn.h] - Blame information for rev 35

Details | Compare with Previous | View Log


// 0x0x = TST
// 0x1x = CMP
// 0x2x = CMPI
// 0x3x = BR
#define RR              0x40
#define ADD                     0x00
#define SUB                     0x01
#define MUL                     0x02
#define DIV                     0x03
#define ADDU            0x04
#define SUBU            0x05
#define MULU            0x06
#define DIVU            0x07
#define _2ADDU          0x08
#define _4ADDU          0x09
#define _8ADDU          0x0A
#define _16ADDU         0x0B
#define MOD                     0x13
#define MODU            0x17
#define R1              0x41
#define CPUID           0x00
#define REDOR           0x01
#define REDAND          0x02
#define PAR                     0x03
#define P1              0x42
#define PAND            0x00
#define POR                     0x01
#define PEOR            0x02
#define PNAND           0x03
#define PNOR            0x04
#define PENOR           0x05
#define PANDC           0x06
#define PORC            0x07
#define BITI    0x46
#define ADDUIS  0x47
#define ADDI    0x48
#define SUBI    0x49
#define MULI    0x4A
#define DIVI    0x4B
#define ADDUI   0x4C
#define SUBUI   0x4D
#define MULUI   0x4E
#define DIVUI   0x4F
#define LOGIC   0x50
#define AND                     0x00
#define OR                      0x01
#define EOR                     0x02
#define NAND            0x03
#define NOR                     0x04
#define ENOR            0x05
#define ANDC            0x06
#define ORC                     0x07
#define ANDI    0x53
#define ORI             0x54
#define EORI    0x55
#define SHIFT   0x58
#define MODI    0x5B
#define MODUI   0x5F
#define SHL                     0x00
#define SHR                     0x01
#define SHLU            0x02
#define SHRU            0x03
#define ROL                     0x04
#define ROR                     0x05
#define SHLI            0x10
#define SHRI            0x11
#define SHLUI           0x12
#define SHRUI           0x13
#define ROLI            0x14
#define RORI            0x15
#define LLA             0x6A
#define _2ADDUI 0x6B
#define _4ADDUI 0x6C
#define _8ADDUI 0x6D
#define _16ADDUI        0x6E
#define LDI             0x6F
#define LB              0x80
#define LBU             0x81
#define LC              0x82
#define LCU             0x83
#define LH              0x84
#define LHU             0x85
#define LW              0x86
#define LVWAR   0x8B
#define SWCR    0x8C
#define JSRI    0x8D
#define LWS             0x8E
#define SB              0x90
#define SC              0x91
#define SH              0x92
#define SW              0x93
#define STSET   0x98
#define LDIS    0x9D
#define SWS             0x9E
#define JSRR    0xA0
#define JSRS    0xA1
#define JSR             0xA2
#define RTS             0xA3
#define LOOP    0xA4
#define SYS             0xA5
#define INT             0xA6
#define GRPA7   0xA7
#define MOV                     0x00
#define NEG                     0x01
#define NOT                     0x02
#define ABS                     0x03
#define SGN                     0x04
#define CNTLZ           0x05
#define CNTLO           0x06
#define CNTPOP          0x07
#define SXB                     0x08
#define SXC                     0x09
#define SXH                     0x0A
#define COM                     0x0B
#define ZXB                     0x0C
#define ZXC                     0x0D
#define ZXH                     0x0E
#define MFSPR   0xA8
#define MTSPR   0xA9
#define LVB             0xAC
#define LVC             0xAD
#define LVH             0xAE
#define LVW             0xAF
#define LBX             0xB0
#define LBUX    0xB1
#define LCX             0xB2
#define LCUX    0xB3
#define LHX             0xB4
#define LHUX    0xB5
#define LWX             0xB6
#define SBX             0xC0
#define SCX             0xC1
#define SHX             0xC2
#define SWX             0xC3
#define INC             0xC7
#define TLB             0xF0
#define RTSQ    0xF2
#define RTE             0xF3
#define RTI             0xF4
#define STP             0xF6
#define SYNC    0xF7
#define MEMSB   0xF8
#define MEMDB   0xF9
#define CLI             0xFA
#define SEI             0xFB
#define RTD             0xFC

Line No.	Rev	Author	Line
1	32	robfinch	`// 0x0x = TST`
2			`// 0x1x = CMP`
3			`// 0x2x = CMPI`
4			`// 0x3x = BR`
5	30	robfinch	`#define RR 0x40`
6	32	robfinch	`#define ADD 0x00`
7			`#define SUB 0x01`
8			`#define MUL 0x02`
9			`#define DIV 0x03`
10			`#define ADDU 0x04`
11			`#define SUBU 0x05`
12			`#define MULU 0x06`
13			`#define DIVU 0x07`
14	30	robfinch	`#define _2ADDU 0x08`
15			`#define _4ADDU 0x09`
16			`#define _8ADDU 0x0A`
17			`#define _16ADDU 0x0B`
18	32	robfinch	`#define MOD 0x13`
19			`#define MODU 0x17`
20			`#define R1 0x41`
21			`#define CPUID 0x00`
22			`#define REDOR 0x01`
23			`#define REDAND 0x02`
24			`#define PAR 0x03`
25			`#define P1 0x42`
26			`#define PAND 0x00`
27			`#define POR 0x01`
28			`#define PEOR 0x02`
29			`#define PNAND 0x03`
30			`#define PNOR 0x04`
31			`#define PENOR 0x05`
32			`#define PANDC 0x06`
33			`#define PORC 0x07`
34			`#define BITI 0x46`
35	30	robfinch	`#define ADDUIS 0x47`
36	32	robfinch	`#define ADDI 0x48`
37			`#define SUBI 0x49`
38			`#define MULI 0x4A`
39			`#define DIVI 0x4B`
40	30	robfinch	`#define ADDUI 0x4C`
41	32	robfinch	`#define SUBUI 0x4D`
42			`#define MULUI 0x4E`
43			`#define DIVUI 0x4F`
44	30	robfinch	`#define LOGIC 0x50`
45	32	robfinch	`#define AND 0x00`
46	30	robfinch	`#define OR 0x01`
47	32	robfinch	`#define EOR 0x02`
48			`#define NAND 0x03`
49			`#define NOR 0x04`
50			`#define ENOR 0x05`
51			`#define ANDC 0x06`
52			`#define ORC 0x07`
53			`#define ANDI 0x53`
54			`#define ORI 0x54`
55			`#define EORI 0x55`
56	30	robfinch	`#define SHIFT 0x58`
57	32	robfinch	`#define MODI 0x5B`
58			`#define MODUI 0x5F`
59	30	robfinch	`#define SHL 0x00`
60	32	robfinch	`#define SHR 0x01`
61			`#define SHLU 0x02`
62			`#define SHRU 0x03`
63			`#define ROL 0x04`
64			`#define ROR 0x05`
65	30	robfinch	`#define SHLI 0x10`
66	32	robfinch	`#define SHRI 0x11`
67			`#define SHLUI 0x12`
68			`#define SHRUI 0x13`
69			`#define ROLI 0x14`
70			`#define RORI 0x15`
71	30	robfinch	`#define LLA 0x6A`
72	32	robfinch	`#define _2ADDUI 0x6B`
73			`#define _4ADDUI 0x6C`
74			`#define _8ADDUI 0x6D`
75			`#define _16ADDUI 0x6E`
76	30	robfinch	`#define LDI 0x6F`
77	32	robfinch	`#define LB 0x80`
78			`#define LBU 0x81`
79			`#define LC 0x82`
80			`#define LCU 0x83`
81	30	robfinch	`#define LH 0x84`
82	32	robfinch	`#define LHU 0x85`
83			`#define LW 0x86`
84			`#define LVWAR 0x8B`
85			`#define SWCR 0x8C`
86			`#define JSRI 0x8D`
87			`#define LWS 0x8E`
88	30	robfinch	`#define SB 0x90`
89			`#define SC 0x91`
90			`#define SH 0x92`
91			`#define SW 0x93`
92	32	robfinch	`#define STSET 0x98`
93	30	robfinch	`#define LDIS 0x9D`
94	32	robfinch	`#define SWS 0x9E`
95	30	robfinch	`#define JSRR 0xA0`
96			`#define JSRS 0xA1`
97			`#define JSR 0xA2`
98			`#define RTS 0xA3`
99			`#define LOOP 0xA4`
100	32	robfinch	`#define SYS 0xA5`
101			`#define INT 0xA6`
102			`#define GRPA7 0xA7`
103			`#define MOV 0x00`
104			`#define NEG 0x01`
105			`#define NOT 0x02`
106			`#define ABS 0x03`
107			`#define SGN 0x04`
108			`#define CNTLZ 0x05`
109			`#define CNTLO 0x06`
110			`#define CNTPOP 0x07`
111			`#define SXB 0x08`
112			`#define SXC 0x09`
113			`#define SXH 0x0A`
114			`#define COM 0x0B`
115			`#define ZXB 0x0C`
116			`#define ZXC 0x0D`
117			`#define ZXH 0x0E`
118	30	robfinch	`#define MFSPR 0xA8`
119			`#define MTSPR 0xA9`
120	32	robfinch	`#define LVB 0xAC`
121			`#define LVC 0xAD`
122			`#define LVH 0xAE`
123			`#define LVW 0xAF`
124			`#define LBX 0xB0`
125			`#define LBUX 0xB1`
126			`#define LCX 0xB2`
127			`#define LCUX 0xB3`
128			`#define LHX 0xB4`
129			`#define LHUX 0xB5`
130			`#define LWX 0xB6`
131			`#define SBX 0xC0`
132			`#define SCX 0xC1`
133			`#define SHX 0xC2`
134			`#define SWX 0xC3`
135	35	robfinch	`#define INC 0xC7`
136	32	robfinch	`#define TLB 0xF0`
137	30	robfinch	`#define RTSQ 0xF2`
138	32	robfinch	`#define RTE 0xF3`
139			`#define RTI 0xF4`
140	30	robfinch	`#define STP 0xF6`
141	32	robfinch	`#define SYNC 0xF7`
142			`#define MEMSB 0xF8`
143			`#define MEMDB 0xF9`
144			`#define CLI 0xFA`
145			`#define SEI 0xFB`
146			`#define RTD 0xFC`

Browse

Tools

Subversion Repositories thor

[/] [thor/] [trunk/] [software/] [emuThor/] [source/] [insn.h] - Blame information for rev 35