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[/] [threeaesc/] [trunk/] [aes_c_3/] [src/] [tb_aes_enc.vhd] - Blame information for rev 2

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1 2 entactogen
-- Copyright (c) 2011 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY tb_aes_enc IS
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END tb_aes_enc;
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ARCHITECTURE behavior OF tb_aes_enc IS
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    -- Component Declaration for the Unit Under Test (UUT)
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    COMPONENT aes_enc
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    PORT(
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         clk : IN  std_logic;
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         block_in : IN  std_logic_vector(127 downto 0);
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         sub_key : IN std_logic_vector(127 downto 0);
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         last : IN std_logic;
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         block_out : OUT  std_logic_vector(127 downto 0));
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    END COMPONENT;
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   --Inputs
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   signal clk : std_logic := '0';
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   signal block_in : std_logic_vector(127 downto 0) := (others => '0');
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   signal sub_key : std_logic_vector(127 downto 0) := (others=> '0');
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   signal last : std_logic := '0';
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        --Outputs
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   signal block_out : std_logic_vector(127 downto 0);
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   -- Clock period definitions
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   constant clk_period : time := 10 ns;
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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   uut: aes_enc PORT MAP (
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          clk => clk,
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          block_in => block_in,
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          sub_key => sub_key,
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          last => last,
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          block_out => block_out);
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   -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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   -- Stimulus process
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   stim_proc: process
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   begin
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                block_in <= X"0f0e0d0c0b0a09080706050403020100";
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                sub_key      <= X"0f0e0d0c0b0a09080706050403020100";
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                wait for clk_period*2;
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                wait;
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   end process;
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END;

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