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dewhisna |
#
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# TimerOCD Makefile for building/simulating with ghdl/gtkwave
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#
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# Copyright (C) 2015 Donna Whisnant/Dewtronics.
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# Contact: http://www.dewtronics.com/
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#
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# This file may be used under the terms of the GNU Lesser General Public License
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# version 3.0 as published by the Free Software Foundation and appearing
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# in the files lgpl-3.0.txt/gpl-3.0.txt included in the packaging of this file.
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# Please review the following information to ensure the GNU Lesser General
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# Public License version 3.0 requirements will be met:
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# https://www.gnu.org/licenses/lgpl-3.0.html
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# Attribution requested, but not required.
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#
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# Target Device: Xilinx Spartan-6 XC6SLX9-2-TQG144
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# Using Numato Mimas Spartan 6 FPGA Development Board
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# http://numato.com/mimas-spartan-6-fpga-development-board.html
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#
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# project name
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PROJECT=TimerOCD
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# vhdl files
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FILES = TimerOCD.vhd \
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spi_slave.vhd \
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../xilinx/TimerOCD/ipcore_dir/timer_memblk.vhd \
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../xilinx/TimerOCD/ipcore_dir/timerCT_memblk.vhd \
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../xilinx/TimerOCD/ipcore_dir/cmpFreqData_memblk.vhd \
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../xilinx/TimerOCD/ipcore_dir/cmpOnData_memblk.vhd \
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../xilinx/TimerOCD/ipcore_dir/InterpolateMultAdd.vhd
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# testbench
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SIMTOP = timerocd_testbench
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SIMFILES = testbench/TimerOCD_testbench.vhd
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# Simu break condition
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#GHDL_SIM_OPT = --assert-level=error --stop-time=1000ms --disp-time --stats
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#GHDL_SIM_OPT = --assert-level=warning --stop-time=1000ms --disp-time --stats
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GHDL_SIM_OPT = --assert-level=error --stop-time=1000ms --stats
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SIMDIR = simu
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XILINX_SRC_PATH = /opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src
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#----------------------------------------------------------
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MV = mv -f
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MKDIR = mkdir -p
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GHDL_CMD = ghdl
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GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic -fexplicit -P$(SIMDIR)
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VIEW_CMD = /usr/bin/gtkwave
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#----------------------------------------------------------
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$(SIMDIR):
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$(MKDIR) $(SIMDIR)
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#----------------------------------------------------------
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#
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# Note: The Xilinx ieee library will not compile under ghdl, using synopsys via GHDL_FLAGS above instead:
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#
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$(SIMDIR)/synopsys-obj93.cf:
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$(GHDL_CMD) -i $(GHDL_FLAGS) --work=synopsys --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/synopsys/*.vhd
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synopsys: $(SIMDIR)/synopsys-obj93.cf
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$(SIMDIR)/ieee-obj93.cf: synopsys
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$(GHDL_CMD) -i $(GHDL_FLAGS) --work=ieee --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/ieee/*.vhd
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#ieee: $(SIMDIR)/ieee-obj93.cf
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ieee:
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#----------------------------------------------------------
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$(SIMDIR)/xilinxcorelib-obj93.cf: ieee
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$(GHDL_CMD) -i $(GHDL_FLAGS) --work=XilinxCoreLib --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/XilinxCoreLib/*.vhd
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xilinxcorelib: $(SIMDIR)/xilinxcorelib-obj93.cf
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#----------------------------------------------------------
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$(SIMDIR)/unisim-obj93.cf: ieee
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$(GHDL_CMD) -i $(GHDL_FLAGS) --work=unisim --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/unisims/*.vhd $(XILINX_SRC_PATH)/unisims/primitive/*.vhd
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unisim: $(SIMDIR)/unisim-obj93.cf
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#----------------------------------------------------------
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$(SIMDIR)/$(SIMTOP): $(SIMDIR) $(FILES) $(SIMFILES) xilinxcorelib unisim
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$(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=$(SIMDIR) --work=work $(SIMFILES) $(FILES)
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$(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=$(SIMDIR) --work=work $(SIMTOP)
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$(MV) $(SIMTOP) $(SIMDIR)/$(SIMTOP)
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all: $(SIMDIR)/$(SIMTOP)
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$(SIMDIR)/$(SIMTOP).vcdgz: $(SIMDIR)/$(SIMTOP)
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@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
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run: $(SIMDIR)/$(SIMTOP).vcdgz
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view:
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gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
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clean:
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$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=work
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$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=unisim
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$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=XilinxCoreLib
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$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=ieee
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$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=synopsys
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