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dewhisna |
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-- File name : spi_slave.vhd
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--------------------------------------------------------------------------------
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-- Copyright (C) 2015 Donna Whisnant/Dewtronics.
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-- Contact: http://www.dewtronics.com/
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--
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-- This file may be used under the terms of the GNU Lesser General Public License
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-- version 3.0 as published by the Free Software Foundation and appearing
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-- in the files lgpl-3.0.txt/gpl-3.0.txt included in the packaging of this file.
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-- Please review the following information to ensure the GNU Lesser General
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-- Public License version 3.0 requirements will be met:
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-- https://www.gnu.org/licenses/lgpl-3.0.html
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-- Attribution requested, but not required.
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--
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-- Target Device: Xilinx Spartan-6 XC6SLX9-2-TQG144
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-- Using Numato Mimas Spartan 6 FPGA Development Board
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-- http://numato.com/mimas-spartan-6-fpga-development-board.html
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--
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--
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-- SPI Slave Entity for TimerOCD
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.VCOMPONENTS.all;
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entity spi_slave is
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generic (
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cpol : STD_LOGIC := '0'; --spi clock polarity mode
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cpha : STD_LOGIC := '0'; --spi clock phase mode
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d_width : INTEGER := 8 --data width in bits
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);
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port (
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sync_clk : in STD_LOGIC; --system clock in for synchronization of the SS signal
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sclk : in STD_LOGIC; --spi clk from master
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reset_n : in STD_LOGIC; --active low reset
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ss_n : in STD_LOGIC; --active low slave select
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mosi : in STD_LOGIC; --master out, slave in
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rrdy : out STD_LOGIC := '0'; --receive ready bit
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rx_data : out STD_LOGIC_VECTOR(d_width-1 downto 0) := (OTHERS => '0'); --receive register output to logic
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busy : out STD_LOGIC := '0'; --busy signal to logic ('1' during transaction)
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miso : out STD_LOGIC := 'Z'; --master in, slave out
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tx_load_data : in STD_LOGIC_VECTOR(d_width-1 downto 0); --Tx data to load (synchronous with end of address receive)
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addr : out STD_LOGIC_VECTOR(7 downto 0) := (OTHERS => '0'); -- Address to Read or Write (as received from SPI)
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addr_latch : out STD_LOGIC := '0'; -- Address Latch Enable Output (Set to True when the address is ready on the output and data should be supplied)
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cmd_load_data : in STD_LOGIC_VECTOR(3 downto 0) := (OTHERS => '0') -- Data nybble to shift out during low nybble of command byte receive
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);
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end spi_slave;
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architecture logic of spi_slave is
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signal mode : STD_LOGIC; --groups modes by clock polarity relation to data
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signal clk : STD_LOGIC; --clock
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constant nRSB : integer := 4; -- Number of RxState Bits (used for conversions)
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signal rx_state : STD_LOGIC_VECTOR(nRSB-1 downto 0); -- Receive state-machine
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signal rxbit_cnt : INTEGER range 0 to d_width-1; -- Bit count for data received
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constant nTSB : integer := 3; -- Number of TxState Bits (used for conversions)
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signal tx_state : STD_LOGIC_VECTOR(nTSB-1 downto 0); -- Transmit state-machine
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constant nTBCSB : integer := 3; -- Transmit Bit Count State Bits (used for conversions)
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signal txbit_flg : STD_LOGIC_VECTOR(nTBCSB-1 downto 0); -- Bit count for data sent
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signal wr_add : STD_LOGIC := '1'; -- address of register to write ('0' = receive, '1' = status)
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signal cmd_add : STD_LOGIC := '0'; -- command or data ('0' = data, '1' = command)
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signal rx_buf : STD_LOGIC_VECTOR(d_width-2 downto 0) := (OTHERS => '0'); --receiver buffer
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signal tx_buf : STD_LOGIC_VECTOR(d_width-1 downto 0) := (OTHERS => '0'); -- transmit buffer
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signal cmd_buf : STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); -- command buffer
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signal out_data : STD_LOGIC; -- Output data gated to miso
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signal syn_ss_n : STD_LOGIC; -- Synchronized SS_N signal
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signal syn_mosi : STD_LOGIC; -- MOSI synchronized to sync_clk
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signal syn_clk_fall : STD_LOGIC; -- CLK falling edge synchronized to sync_clk
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signal syn_clk_rise : STD_LOGIC; -- CLK rising edge synchronized to sync_clk
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signal resync_clk : STD_LOGIC_VECTOR(3 downto 0);
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signal resync_ss : STD_LOGIC_VECTOR(1 downto 0);
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signal resync_mosi : STD_LOGIC_VECTOR(1 downto 0);
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signal rrdy_int : STD_LOGIC; -- Internal rrdy. Set in the Rx State-Machine. Used to trigger a delayed rrdy pulse back to the main logic to get data a setup/hold time
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signal rrdy_out : STD_LOGIC; -- Output rrdy (used to eliminate buffer type)
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signal addr_latch_int : STD_LOGIC; -- Internal addr_latch. Set in the Rx State-Machine. Used to trigger a delayed addr_latch pulse back to the main logic to get data a setup/hold time
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signal addr_latch_out : STD_LOGIC; -- Output addr_latch (used to eliminate buffer type)
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begin
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--adjust clock so writes are on rising edge and reads on falling edge
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mode <= cpol XOR cpha; --'1' for modes that write on rising edge
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with mode select
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clk <= sclk when '1', NOT sclk when OTHERS;
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-- Input synchronization:
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sync_clk_proc:process(sync_clk)
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begin
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if (rising_edge(sync_clk)) then
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syn_ss_n <= resync_ss(0);
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syn_mosi <= resync_mosi(0);
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resync_clk <= resync_clk(2 downto 0) & clk;
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resync_ss <= resync_ss(0) & ss_n;
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resync_mosi <= resync_mosi(0) & mosi;
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end if;
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end process sync_clk_proc;
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syn_clk_fall <= resync_clk(3) and not resync_clk(2); -- '1' when going from 1 -> 0
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syn_clk_rise <= not resync_clk(2) and resync_clk(1); -- '1' when going from 0 -> 1
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-- output drive:
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with (syn_ss_n OR (NOT reset_n)) select
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miso <= 'Z' when '1', out_data when OTHERS;
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busy <= NOT syn_ss_n; --high during transactions
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-- rrdy synchronization:
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-- Since rxspiproc is triggered on the rising_edge of
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-- sync_clk, this process delays reporting it
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-- by 1/2 clock cycle, giving the data time to
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-- get stored:
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rrdyproc:process(syn_ss_n, sync_clk, reset_n)
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begin
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if ((syn_ss_n = '1') OR (reset_n = '0')) then
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rrdy_out <= '0';
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elsif (falling_edge(sync_clk)) then
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if (rrdy_out = '0') then
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rrdy_out <= rrdy_int;
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end if;
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end if;
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end process rrdyproc;
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rrdy <= rrdy_out;
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-- addr_latch synchronization:
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-- Since rxspiproc is triggered on the rising_edge of
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-- sync clk, this process delays reporting it
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-- by 1/2 clock cycle, giving the data time to
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-- get stored:
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addrlatchproc:process(syn_ss_n, sync_clk, reset_n)
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begin
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if ((syn_ss_n = '1') OR (reset_n = '0')) then
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addr_latch_out <= '0';
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elsif (falling_edge(sync_clk)) then
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if (addr_latch_out = '0') then
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addr_latch_out <= addr_latch_int;
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end if;
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end if;
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end process addrlatchproc;
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addr_latch <= addr_latch_out;
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-- rxspiproc: Receives incoming data
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rxspiproc:process(syn_ss_n, syn_clk_fall, reset_n)
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begin
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if ((syn_ss_n = '1') OR (reset_n = '0')) then
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rx_state <= (OTHERS => '0');
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rx_buf <= (OTHERS => '0');
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rxbit_cnt <= d_width-1;
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rrdy_int <= '0';
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addr_latch_int <= '0';
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elsif (falling_edge(syn_clk_fall)) then
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case CONV_INTEGER(rx_state) is
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when 0 =>
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--read/write mode ('0' for write, '1' for read)
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wr_add <= syn_mosi;
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addr(7) <= syn_mosi;
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rx_state <= CONV_STD_LOGIC_VECTOR(1, nRSB);
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when 1 =>
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--cmd/data mode ('0' for data, '1' for cmd)
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cmd_add <= syn_mosi;
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addr(6) <= syn_mosi;
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rx_state <= CONV_STD_LOGIC_VECTOR(3, nRSB);
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when 3 =>
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addr(5) <= syn_mosi;
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rx_state <= CONV_STD_LOGIC_VECTOR(2, nRSB);
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when 2 =>
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addr(4) <= syn_mosi;
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rx_state <= CONV_STD_LOGIC_VECTOR(6, nRSB);
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when 6 =>
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addr(3) <= syn_mosi;
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rx_state <= CONV_STD_LOGIC_VECTOR(7, nRSB);
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when 7 =>
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addr(2) <= syn_mosi;
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rx_state <= CONV_STD_LOGIC_VECTOR(5, nRSB);
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when 5 =>
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addr(1) <= syn_mosi;
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rx_state <= CONV_STD_LOGIC_VECTOR(4, nRSB);
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when 4 =>
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addr(0) <= syn_mosi;
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if (cmd_add = '1') then
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rx_state <= CONV_STD_LOGIC_VECTOR(13, nRSB);
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if (wr_add = '0') then
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rrdy_int <= '1';
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end if;
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else
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addr_latch_int <= '1';
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rx_state <= CONV_STD_LOGIC_VECTOR(12, nRSB);
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end if;
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when 12 =>
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if (rxbit_cnt = 0) then
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if (wr_add = '0') then
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rx_data <= rx_buf & syn_mosi;
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rrdy_int <= '1';
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end if;
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rx_state <= CONV_STD_LOGIC_VECTOR(13, nRSB);
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else
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if (wr_add = '0') then
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rx_buf <= rx_buf(rx_buf'HIGH-1 downto 0) & syn_mosi;
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end if;
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rxbit_cnt <= (rxbit_cnt - 1);
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-- Stay in this state until all bits are received
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end if;
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when 13 =>
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-- Stay in this state. The SS_n signal will release us
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when OTHERS =>
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end case;
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end if;
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end process rxspiproc;
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-- txspiproc: Transmits outgoing data
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-- Note: Commented out code for cmd_buf/cmd_load_data and
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-- tx_buf/tx_load_data can be used to determine the point
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-- where data must be ready/available from the main TimerOCD
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-- relative to the SPI traffic. This allows for faster SPI
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-- clock rates by only requiring the first couple of bits and/or
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-- first byte of data to be valid when the SPI clock begins
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-- shifting it out. Since several memory read operations are
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-- required to obtain the data needed to be sent, this allows
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-- for several SPI clock cycle times before that data reading
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-- must be completed.
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txspiproc:process(syn_ss_n, syn_clk_rise, reset_n)
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begin
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if ((syn_ss_n = '1') OR (reset_n = '0')) then
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tx_state <= (OTHERS => '0');
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tx_buf <= (OTHERS => '0');
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txbit_flg <= (OTHERS => '0');
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out_data <= '0';
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elsif (rising_edge(syn_clk_rise)) then
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case CONV_INTEGER(tx_state) is
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when 0 =>
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tx_state <= CONV_STD_LOGIC_VECTOR(1, nTSB);
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when 1 =>
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tx_state <= CONV_STD_LOGIC_VECTOR(3, nTSB);
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when 3 =>
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tx_state <= CONV_STD_LOGIC_VECTOR(2, nTSB);
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when 2 =>
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out_data <= cmd_load_data(3);
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-- cmd_buf <= cmd_load_data(2 downto 0);
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tx_state <= CONV_STD_LOGIC_VECTOR(6, nTSB);
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when 6 =>
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-- out_data <= cmd_buf(2);
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out_data <= cmd_load_data(2);
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cmd_buf <= cmd_load_data(2 downto 0);
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tx_state <= CONV_STD_LOGIC_VECTOR(7, nTSB);
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when 7 =>
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out_data <= cmd_buf(1);
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tx_state <= CONV_STD_LOGIC_VECTOR(5, nTSB);
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when 5 =>
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out_data <= cmd_buf(0);
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tx_state <= CONV_STD_LOGIC_VECTOR(4, nTSB);
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when 4 =>
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if (cmd_add='0') then
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case CONV_INTEGER(txbit_flg) is
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when 0 =>
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out_data <= tx_load_data(d_width-1);
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-- tx_buf <= tx_load_data(d_width-2 downto 0) & "0";
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txbit_flg <= CONV_STD_LOGIC_VECTOR(1, nTBCSB);
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when 1 =>
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out_data <= tx_load_data(d_width-2);
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-- tx_buf <= tx_load_data(d_width-3 downto 0) & "00";
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txbit_flg <= CONV_STD_LOGIC_VECTOR(3, nTBCSB);
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when 3 =>
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out_data <= tx_load_data(d_width-3);
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-- tx_buf <= tx_load_data(d_width-4 downto 0) & "000";
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txbit_flg <= CONV_STD_LOGIC_VECTOR(2, nTBCSB);
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when 2 =>
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out_data <= tx_load_data(d_width-4);
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-- tx_buf <= tx_load_data(d_width-5 downto 0) & "0000";
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txbit_flg <= CONV_STD_LOGIC_VECTOR(6, nTBCSB);
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when 6 =>
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out_data <= tx_load_data(d_width-5);
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-- tx_buf <= tx_load_data(d_width-6 downto 0) & "00000";
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txbit_flg <= CONV_STD_LOGIC_VECTOR(7, nTBCSB);
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when 7 =>
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out_data <= tx_load_data(d_width-6);
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-- tx_buf <= tx_load_data(d_width-7 downto 0) & "000000";
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txbit_flg <= CONV_STD_LOGIC_VECTOR(5, nTBCSB);
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when 5 =>
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out_data <= tx_load_data(d_width-7);
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tx_buf <= tx_load_data(d_width-8 downto 0) & "0000000";
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|
|
txbit_flg <= CONV_STD_LOGIC_VECTOR(4, nTBCSB);
|
| 283 |
|
|
when 4 =>
|
| 284 |
|
|
out_data <= tx_buf(tx_buf'HIGH);
|
| 285 |
|
|
tx_buf <= tx_buf(tx_buf'HIGH-1 downto 0) & "0";
|
| 286 |
|
|
-- Stay here and shift out remaining data. SS_n will release us
|
| 287 |
|
|
when OTHERS =>
|
| 288 |
|
|
end case;
|
| 289 |
|
|
else
|
| 290 |
|
|
out_data <= '0';
|
| 291 |
|
|
end if;
|
| 292 |
|
|
-- stay in this state shifting data out
|
| 293 |
|
|
when OTHERS => -- There are no other states, but keep ghdl happy
|
| 294 |
|
|
end case;
|
| 295 |
|
|
end if;
|
| 296 |
|
|
end process txspiproc;
|
| 297 |
|
|
end logic;
|
