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-- You must compile the wrapper file InterpolateMultAdd.vhd when simulating

-- the core, InterpolateMultAdd. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

ENTITY InterpolateMultAdd IS

  PORT (

    a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

    b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

    c : IN STD_LOGIC_VECTOR(27 DOWNTO 0);

    subtract : IN STD_LOGIC;

    p : OUT STD_LOGIC_VECTOR(27 DOWNTO 12);

    pcout : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)

  );

END InterpolateMultAdd;

ARCHITECTURE InterpolateMultAdd_a OF InterpolateMultAdd IS

-- synthesis translate_off

COMPONENT wrapped_InterpolateMultAdd

  PORT (

    a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

    b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

    c : IN STD_LOGIC_VECTOR(27 DOWNTO 0);

    subtract : IN STD_LOGIC;

    p : OUT STD_LOGIC_VECTOR(27 DOWNTO 12);

    pcout : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)

  );

END COMPONENT;

-- Configuration specification

  FOR ALL : wrapped_InterpolateMultAdd USE ENTITY XilinxCoreLib.xbip_multadd_v2_0(behavioral)

    GENERIC MAP (

      C_AB_LATENCY => 0,

      C_A_TYPE => 0,

      C_A_WIDTH => 16,

      C_B_TYPE => 1,

      C_B_WIDTH => 12,

      C_CE_OVERRIDES_SCLR => 0,

      C_C_LATENCY => 0,

      C_C_TYPE => 1,

      C_C_WIDTH => 28,

      C_OUT_HIGH => 27,

      C_OUT_LOW => 12,

      C_TEST_CORE => 0,

      C_USE_PCIN => 0,

      C_VERBOSITY => 0,

      C_XDEVICEFAMILY => "spartan6"

    );

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_InterpolateMultAdd

  PORT MAP (

    a => a,

    b => b,

    c => c,

    subtract => subtract,

    p => p,

    pcout => pcout

  );

-- synthesis translate_on

END InterpolateMultAdd_a;