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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# Wed Apr 11 16:23:26 2007
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
# Family:        virtex4
# Device:        xc4vfx12
# Package:       ff668
# Speed Grade:   -10
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory :  32 KB
# Total Off Chip Memory :  72 MB
# - DDR_SDRAM_32Mx32 =  64 MB
# - FLASH_2Mx32 =   8 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0
 
 PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
 PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin = fpga_0_Push_Buttons_Position_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
 PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, DIR = O, VEC = [0:12]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DM, DIR = O, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, DIR = IO, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
 PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
 PORT fpga_0_FLASH_2Mx32_Mem_A_pin = fpga_0_FLASH_2Mx32_Mem_A, DIR = O, VEC = [9:29]
 PORT fpga_0_FLASH_2Mx32_Mem_WEN_pin = fpga_0_FLASH_2Mx32_Mem_WEN, DIR = O
 PORT fpga_0_FLASH_2Mx32_Mem_DQ_pin = fpga_0_FLASH_2Mx32_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_FLASH_2Mx32_Mem_OEN_pin = fpga_0_FLASH_2Mx32_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_FLASH_2Mx32_Mem_CE_pin = fpga_0_FLASH_2Mx32_Mem_CE, DIR = O, VEC = [0:0]
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
 
 
BEGIN ppc405_virtex4
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
 BUS_INTERFACE IPLB = plb
 BUS_INTERFACE DPLB = plb
 PORT PLBCLK = sys_clk_s
 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
 PORT RSTC405RESETCORE = RSTC405RESETCORE
 PORT RSTC405RESETSYS = RSTC405RESETSYS
 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
 PORT CPMC405CLOCK = proc_clk_s
 # APU timestamp UDI
 PARAMETER C_APU_CONTROL = 0x1E01
 PARAMETER C_APU_UDI_1 = 0xC07605
 # APU
 PORT CPMFCMCLK = sys_clk_s
 PORT APUFCMFLUSH = APUFCMFLUSH
 PORT APUFCMDECODED = APUFCMDECODED
 PORT APUFCMINSTRVALID = APUFCMINSTRVALID
 PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID
 PORT APUFCMDECUDI = APUFCMDECUDI
 PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK
 PORT APUFCMRADATA = APUFCMRADATA
 PORT APUFCMRBDATA = APUFCMRBDATA
 PORT FCMAPUDONE = FCMAPUDONE
 PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY
END
 
BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
END
 
BEGIN proc_sys_reset
 PARAMETER INSTANCE = reset_block
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Ext_Reset_In = sys_rst_s
 PORT Slowest_sync_clk = sys_clk_s
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
 PORT Core_Reset_Req = C405RSTCORERESETREQ
 PORT System_Reset_Req = C405RSTSYSRESETREQ
 PORT Rstc405resetchip = RSTC405RESETCHIP
 PORT Rstc405resetcore = RSTC405RESETCORE
 PORT Rstc405resetsys = RSTC405RESETSYS
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Dcm_locked = dcm_1_lock
END
 
BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END
 
BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_s
END
 
BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG0_BASEADDR = 0x40000000
 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
END
 
BEGIN opb_uart16550
 PARAMETER INSTANCE = RS232_Uart
 PARAMETER HW_VER = 1.00.e
 PARAMETER C_IS_A_16550 = 1
 PARAMETER C_BASEADDR = 0x40400000
 PARAMETER C_HIGHADDR = 0x4040ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
 PORT sin = fpga_0_RS232_Uart_sin
 PORT sout = fpga_0_RS232_Uart_sout
END
 
BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END
 
BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_Positions
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = LEDs_Positions_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
END
 
BEGIN opb_gpio
 PARAMETER INSTANCE = Push_Buttons_Position
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = opb
 PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO
END
 
BEGIN opb_iic
 PARAMETER INSTANCE = IIC_EEPROM
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x40800000
 PARAMETER C_HIGHADDR = 0x4080ffff
 BUS_INTERFACE SOPB = opb
 PORT Scl = fpga_0_IIC_EEPROM_Scl
 PORT Sda = fpga_0_IIC_EEPROM_Sda
END
 
BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE SOPB = opb
 PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END
 
BEGIN plb_ddr
 PARAMETER INSTANCE = DDR_SDRAM_64Mx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 80000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 15000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFI = 7800000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 9
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 32
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x03ffffff
 BUS_INTERFACE SPLB = plb
 PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
 PORT Clk90_in = clk_90_s
 PORT Clk90_in_n = clk_90_n_s
 PORT PLB_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
 
BEGIN opb_ethernet
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_DMA_PRESENT = 1
 PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
 PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_BASEADDR = 0x40c00000
 PARAMETER C_HIGHADDR = 0x40c0ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
 PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END
 
BEGIN plb_emc
 PARAMETER INSTANCE = FLASH_2Mx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 110000
 PARAMETER C_TWC_PS_MEM_0 = 55000
 PARAMETER C_TAVDV_PS_MEM_0 = 110000
 PARAMETER C_TWP_PS_MEM_0 = 55000
 PARAMETER C_THZCE_PS_MEM_0 = 10000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER C_MEM0_BASEADDR = 0x06000000
 PARAMETER C_MEM0_HIGHADDR = 0x067fffff
 BUS_INTERFACE SPLB = plb
 PORT Mem_A = fpga_0_FLASH_2Mx32_Mem_A_split
 PORT Mem_WEN = fpga_0_FLASH_2Mx32_Mem_WEN
 PORT Mem_DQ = fpga_0_FLASH_2Mx32_Mem_DQ
 PORT Mem_OEN = fpga_0_FLASH_2Mx32_Mem_OEN
 PORT Mem_CE = fpga_0_FLASH_2Mx32_Mem_CE
END
 
BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_plb_clk_period_ps = 10000
 PARAMETER c_baseaddr = 0xffff8000
 PARAMETER c_highaddr = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
 
BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
 
BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE SOPB = opb
 PORT Interrupt = opb_timer_1_Interrupt
END
 
BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = opb
 PORT Irq = EICC405EXTINPUTIRQ
 PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & LEDs_Positions_IP2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt
END
 
BEGIN util_bus_split
 PARAMETER INSTANCE = FLASH_2Mx32_util_bus_split_3
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 9
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_FLASH_2Mx32_Mem_A_split
 PORT Out1 = fpga_0_FLASH_2Mx32_Mem_A
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END
 
BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKFX_BUF = TRUE
 PARAMETER C_CLKFX_DIVIDE = 1
 PARAMETER C_CLKFX_MULTIPLY = 3
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DFS_FREQUENCY_MODE = HIGH
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFX = proc_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END
 
BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_PHASE_SHIFT = 12
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END
 
##
## timestamp hw
##
 
BEGIN timestamp
 PARAMETER INSTANCE = timestamp_0
 BUS_INTERFACE PORTB = plb_bram_if_cntlr_0_PORTA
 PORT debug = fpga_0_scope
 PORT reset = sys_bus_reset
 PORT CPMFCMCLK = sys_clk_s
 PORT APUFCMFLUSH = APUFCMFLUSH
 PORT APUFCMDECODED = APUFCMDECODED
 PORT APUFCMINSTRVALID = APUFCMINSTRVALID
 PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID
 PORT APUFCMDECUDI = APUFCMDECUDI
 PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK
 PORT APUFCMRADATA = APUFCMRADATA
 PORT APUFCMRBDATA = APUFCMRBDATA
 PORT FCMAPUDONE = FCMAPUDONE
 PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY
END
 
BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_baseaddr = 0xCC000000
 PARAMETER c_highaddr = 0xCC003FFF
 PARAMETER c_plb_clk_period_ps = 10000
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_0_PORTA
END

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[/] [timestamp/] [trunk/] [system.mhs.example] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	robotron
2			`# ##############################################################################`
3			`# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4`
4			`# Wed Apr 11 16:23:26 2007`
5			`# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1`
6			`# Family: virtex4`
7			`# Device: xc4vfx12`
8			`# Package: ff668`
9			`# Speed Grade: -10`
10			`# Processor: PPC 405`
11			`# Processor clock frequency: 300.000000 MHz`
12			`# Bus clock frequency: 100.000000 MHz`
13			`# Debug interface: FPGA JTAG`
14			`# On Chip Memory : 32 KB`
15			`# Total Off Chip Memory : 72 MB`
16			`# - DDR_SDRAM_32Mx32 = 64 MB`
17			`# - FLASH_2Mx32 = 8 MB`
18			`# ##############################################################################`
19			`PARAMETER VERSION = 2.1.0`
20
21			`PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I`
22			`PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O`
23			`PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]`
24			`PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]`
25			`PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin = fpga_0_Push_Buttons_Position_GPIO_IO, DIR = IO, VEC = [0:4]`
26			`PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO`
27			`PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO`
28			`PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I`
29			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]`
30			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]`
31			`PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O`
32			`PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O`
33			`PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O`
34			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I`
35			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = O`
36			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = O`
37			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, DIR = O, VEC = [0:12]`
38			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, DIR = O, VEC = [0:1]`
39			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = O`
40			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = O`
41			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = O`
42			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = O`
43			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = O`
44			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DM, DIR = O, VEC = [0:3]`
45			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, DIR = IO, VEC = [0:3]`
46			`PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, DIR = IO, VEC = [0:31]`
47			`PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O`
48			`PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I`
49			`PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I`
50			`PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]`
51			`PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O`
52			`PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I`
53			`PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O`
54			`PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I`
55			`PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I`
56			`PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I`
57			`PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]`
58			`PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO`
59			`PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO`
60			`PORT fpga_0_FLASH_2Mx32_Mem_A_pin = fpga_0_FLASH_2Mx32_Mem_A, DIR = O, VEC = [9:29]`
61			`PORT fpga_0_FLASH_2Mx32_Mem_WEN_pin = fpga_0_FLASH_2Mx32_Mem_WEN, DIR = O`
62			`PORT fpga_0_FLASH_2Mx32_Mem_DQ_pin = fpga_0_FLASH_2Mx32_Mem_DQ, DIR = IO, VEC = [0:31]`
63			`PORT fpga_0_FLASH_2Mx32_Mem_OEN_pin = fpga_0_FLASH_2Mx32_Mem_OEN, DIR = O, VEC = [0:0]`
64			`PORT fpga_0_FLASH_2Mx32_Mem_CE_pin = fpga_0_FLASH_2Mx32_Mem_CE, DIR = O, VEC = [0:0]`
65			`PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000`
66			`PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000`
67			`PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST`
68
69
70			`BEGIN ppc405_virtex4`
71			`PARAMETER INSTANCE = ppc405_0`
72			`PARAMETER HW_VER = 1.01.a`
73			`BUS_INTERFACE JTAGPPC = jtagppc_0_0`
74			`BUS_INTERFACE IPLB = plb`
75			`BUS_INTERFACE DPLB = plb`
76			`PORT PLBCLK = sys_clk_s`
77			`PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ`
78			`PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ`
79			`PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ`
80			`PORT RSTC405RESETCHIP = RSTC405RESETCHIP`
81			`PORT RSTC405RESETCORE = RSTC405RESETCORE`
82			`PORT RSTC405RESETSYS = RSTC405RESETSYS`
83			`PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ`
84			`PORT CPMC405CLOCK = proc_clk_s`
85			`# APU timestamp UDI`
86			`PARAMETER C_APU_CONTROL = 0x1E01`
87			`PARAMETER C_APU_UDI_1 = 0xC07605`
88			`# APU`
89			`PORT CPMFCMCLK = sys_clk_s`
90			`PORT APUFCMFLUSH = APUFCMFLUSH`
91			`PORT APUFCMDECODED = APUFCMDECODED`
92			`PORT APUFCMINSTRVALID = APUFCMINSTRVALID`
93			`PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID`
94			`PORT APUFCMDECUDI = APUFCMDECUDI`
95			`PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK`
96			`PORT APUFCMRADATA = APUFCMRADATA`
97			`PORT APUFCMRBDATA = APUFCMRBDATA`
98			`PORT FCMAPUDONE = FCMAPUDONE`
99			`PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY`
100			`END`
101
102			`BEGIN jtagppc_cntlr`
103			`PARAMETER INSTANCE = jtagppc_0`
104			`PARAMETER HW_VER = 2.00.a`
105			`BUS_INTERFACE JTAGPPC0 = jtagppc_0_0`
106			`END`
107
108			`BEGIN proc_sys_reset`
109			`PARAMETER INSTANCE = reset_block`
110			`PARAMETER HW_VER = 1.00.a`
111			`PARAMETER C_EXT_RESET_HIGH = 0`
112			`PORT Ext_Reset_In = sys_rst_s`
113			`PORT Slowest_sync_clk = sys_clk_s`
114			`PORT Chip_Reset_Req = C405RSTCHIPRESETREQ`
115			`PORT Core_Reset_Req = C405RSTCORERESETREQ`
116			`PORT System_Reset_Req = C405RSTSYSRESETREQ`
117			`PORT Rstc405resetchip = RSTC405RESETCHIP`
118			`PORT Rstc405resetcore = RSTC405RESETCORE`
119			`PORT Rstc405resetsys = RSTC405RESETSYS`
120			`PORT Bus_Struct_Reset = sys_bus_reset`
121			`PORT Dcm_locked = dcm_1_lock`
122			`END`
123
124			`BEGIN plb_v34`
125			`PARAMETER INSTANCE = plb`
126			`PARAMETER HW_VER = 1.02.a`
127			`PARAMETER C_DCR_INTFCE = 0`
128			`PARAMETER C_EXT_RESET_HIGH = 1`
129			`PORT SYS_Rst = sys_bus_reset`
130			`PORT PLB_Clk = sys_clk_s`
131			`END`
132
133			`BEGIN opb_v20`
134			`PARAMETER INSTANCE = opb`
135			`PARAMETER HW_VER = 1.10.c`
136			`PARAMETER C_EXT_RESET_HIGH = 1`
137			`PORT SYS_Rst = sys_bus_reset`
138			`PORT OPB_Clk = sys_clk_s`
139			`END`
140
141			`BEGIN plb2opb_bridge`
142			`PARAMETER INSTANCE = plb2opb`
143			`PARAMETER HW_VER = 1.01.a`
144			`PARAMETER C_DCR_INTFCE = 0`
145			`PARAMETER C_NUM_ADDR_RNG = 1`
146			`PARAMETER C_RNG0_BASEADDR = 0x40000000`
147			`PARAMETER C_RNG0_HIGHADDR = 0x7fffffff`
148			`BUS_INTERFACE SPLB = plb`
149			`BUS_INTERFACE MOPB = opb`
150			`END`
151
152			`BEGIN opb_uart16550`
153			`PARAMETER INSTANCE = RS232_Uart`
154			`PARAMETER HW_VER = 1.00.e`
155			`PARAMETER C_IS_A_16550 = 1`
156			`PARAMETER C_BASEADDR = 0x40400000`
157			`PARAMETER C_HIGHADDR = 0x4040ffff`
158			`BUS_INTERFACE SOPB = opb`
159			`PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt`
160			`PORT sin = fpga_0_RS232_Uart_sin`
161			`PORT sout = fpga_0_RS232_Uart_sout`
162			`END`
163
164			`BEGIN opb_gpio`
165			`PARAMETER INSTANCE = LEDs_4Bit`
166			`PARAMETER HW_VER = 3.01.b`
167			`PARAMETER C_INTERRUPT_PRESENT = 1`
168			`PARAMETER C_GPIO_WIDTH = 4`
169			`PARAMETER C_IS_DUAL = 0`
170			`PARAMETER C_IS_BIDIR = 1`
171			`PARAMETER C_ALL_INPUTS = 0`
172			`PARAMETER C_BASEADDR = 0x40000000`
173			`PARAMETER C_HIGHADDR = 0x4000ffff`
174			`BUS_INTERFACE SOPB = opb`
175			`PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt`
176			`PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO`
177			`END`
178
179			`BEGIN opb_gpio`
180			`PARAMETER INSTANCE = LEDs_Positions`
181			`PARAMETER HW_VER = 3.01.b`
182			`PARAMETER C_INTERRUPT_PRESENT = 1`
183			`PARAMETER C_GPIO_WIDTH = 5`
184			`PARAMETER C_IS_DUAL = 0`
185			`PARAMETER C_IS_BIDIR = 1`
186			`PARAMETER C_ALL_INPUTS = 0`
187			`PARAMETER C_BASEADDR = 0x40020000`
188			`PARAMETER C_HIGHADDR = 0x4002ffff`
189			`BUS_INTERFACE SOPB = opb`
190			`PORT IP2INTC_Irpt = LEDs_Positions_IP2INTC_Irpt`
191			`PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO`
192			`END`
193
194			`BEGIN opb_gpio`
195			`PARAMETER INSTANCE = Push_Buttons_Position`
196			`PARAMETER HW_VER = 3.01.b`
197			`PARAMETER C_GPIO_WIDTH = 5`
198			`PARAMETER C_IS_DUAL = 0`
199			`PARAMETER C_IS_BIDIR = 1`
200			`PARAMETER C_ALL_INPUTS = 1`
201			`PARAMETER C_BASEADDR = 0x40040000`
202			`PARAMETER C_HIGHADDR = 0x4004ffff`
203			`BUS_INTERFACE SOPB = opb`
204			`PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO`
205			`END`
206
207			`BEGIN opb_iic`
208			`PARAMETER INSTANCE = IIC_EEPROM`
209			`PARAMETER HW_VER = 1.02.a`
210			`PARAMETER C_CLK_FREQ = 100000000`
211			`PARAMETER C_IIC_FREQ = 100000`
212			`PARAMETER C_TEN_BIT_ADR = 0`
213			`PARAMETER C_BASEADDR = 0x40800000`
214			`PARAMETER C_HIGHADDR = 0x4080ffff`
215			`BUS_INTERFACE SOPB = opb`
216			`PORT Scl = fpga_0_IIC_EEPROM_Scl`
217			`PORT Sda = fpga_0_IIC_EEPROM_Sda`
218			`END`
219
220			`BEGIN opb_sysace`
221			`PARAMETER INSTANCE = SysACE_CompactFlash`
222			`PARAMETER HW_VER = 1.00.c`
223			`PARAMETER C_MEM_WIDTH = 16`
224			`PARAMETER C_BASEADDR = 0x41800000`
225			`PARAMETER C_HIGHADDR = 0x4180ffff`
226			`BUS_INTERFACE SOPB = opb`
227			`PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ`
228			`PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK`
229			`PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA`
230			`PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD`
231			`PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN`
232			`PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN`
233			`PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN`
234			`PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ`
235			`END`
236
237			`BEGIN plb_ddr`
238			`PARAMETER INSTANCE = DDR_SDRAM_64Mx32`
239			`PARAMETER HW_VER = 2.00.a`
240			`PARAMETER C_PLB_CLK_PERIOD_PS = 10000`
241			`PARAMETER C_REG_DIMM = 0`
242			`PARAMETER C_DDR_TMRD = 20000`
243			`PARAMETER C_DDR_TWR = 20000`
244			`PARAMETER C_DDR_TRAS = 60000`
245			`PARAMETER C_DDR_TRC = 90000`
246			`PARAMETER C_DDR_TRFC = 80000`
247			`PARAMETER C_DDR_TRCD = 30000`
248			`PARAMETER C_DDR_TRRD = 15000`
249			`PARAMETER C_DDR_TRP = 30000`
250			`PARAMETER C_DDR_TREFI = 7800000`
251			`PARAMETER C_DDR_AWIDTH = 13`
252			`PARAMETER C_DDR_COL_AWIDTH = 9`
253			`PARAMETER C_DDR_BANK_AWIDTH = 2`
254			`PARAMETER C_DDR_DWIDTH = 32`
255			`PARAMETER C_MEM0_BASEADDR = 0x00000000`
256			`PARAMETER C_MEM0_HIGHADDR = 0x03ffffff`
257			`BUS_INTERFACE SPLB = plb`
258			`PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr`
259			`PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr`
260			`PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn`
261			`PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE`
262			`PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn`
263			`PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn`
264			`PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn`
265			`PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM`
266			`PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS`
267			`PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ`
268			`PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk`
269			`PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn`
270			`PORT Clk90_in = clk_90_s`
271			`PORT Clk90_in_n = clk_90_n_s`
272			`PORT PLB_Clk_n = sys_clk_n_s`
273			`PORT DDR_Clk90_in = ddr_clk_90_s`
274			`PORT DDR_Clk90_in_n = ddr_clk_90_n_s`
275			`END`
276
277			`BEGIN opb_ethernet`
278			`PARAMETER INSTANCE = Ethernet_MAC`
279			`PARAMETER HW_VER = 1.04.a`
280			`PARAMETER C_DMA_PRESENT = 1`
281			`PARAMETER C_IPIF_RDFIFO_DEPTH = 32768`
282			`PARAMETER C_IPIF_WRFIFO_DEPTH = 32768`
283			`PARAMETER C_OPB_CLK_PERIOD_PS = 10000`
284			`PARAMETER C_BASEADDR = 0x40c00000`
285			`PARAMETER C_HIGHADDR = 0x40c0ffff`
286			`BUS_INTERFACE SOPB = opb`
287			`PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt`
288			`PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n`
289			`PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs`
290			`PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col`
291			`PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data`
292			`PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en`
293			`PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk`
294			`PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er`
295			`PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er`
296			`PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk`
297			`PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv`
298			`PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data`
299			`PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk`
300			`PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data`
301			`END`
302
303			`BEGIN plb_emc`
304			`PARAMETER INSTANCE = FLASH_2Mx32`
305			`PARAMETER HW_VER = 2.00.a`
306			`PARAMETER C_PLB_CLK_PERIOD_PS = 10000`
307			`PARAMETER C_NUM_BANKS_MEM = 1`
308			`PARAMETER C_MAX_MEM_WIDTH = 32`
309			`PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1`
310			`PARAMETER C_MEM0_WIDTH = 32`
311			`PARAMETER C_SYNCH_MEM_0 = 0`
312			`PARAMETER C_TCEDV_PS_MEM_0 = 110000`
313			`PARAMETER C_TWC_PS_MEM_0 = 55000`
314			`PARAMETER C_TAVDV_PS_MEM_0 = 110000`
315			`PARAMETER C_TWP_PS_MEM_0 = 55000`
316			`PARAMETER C_THZCE_PS_MEM_0 = 10000`
317			`PARAMETER C_TLZWE_PS_MEM_0 = 35000`
318			`PARAMETER C_MEM0_BASEADDR = 0x06000000`
319			`PARAMETER C_MEM0_HIGHADDR = 0x067fffff`
320			`BUS_INTERFACE SPLB = plb`
321			`PORT Mem_A = fpga_0_FLASH_2Mx32_Mem_A_split`
322			`PORT Mem_WEN = fpga_0_FLASH_2Mx32_Mem_WEN`
323			`PORT Mem_DQ = fpga_0_FLASH_2Mx32_Mem_DQ`
324			`PORT Mem_OEN = fpga_0_FLASH_2Mx32_Mem_OEN`
325			`PORT Mem_CE = fpga_0_FLASH_2Mx32_Mem_CE`
326			`END`
327
328			`BEGIN plb_bram_if_cntlr`
329			`PARAMETER INSTANCE = plb_bram_if_cntlr_1`
330			`PARAMETER HW_VER = 1.00.b`
331			`PARAMETER c_plb_clk_period_ps = 10000`
332			`PARAMETER c_baseaddr = 0xffff8000`
333			`PARAMETER c_highaddr = 0xffffffff`
334			`BUS_INTERFACE SPLB = plb`
335			`BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port`
336			`END`
337
338			`BEGIN bram_block`
339			`PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram`
340			`PARAMETER HW_VER = 1.00.a`
341			`BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port`
342			`END`
343
344			`BEGIN opb_timer`
345			`PARAMETER INSTANCE = opb_timer_1`
346			`PARAMETER HW_VER = 1.00.b`
347			`PARAMETER C_COUNT_WIDTH = 32`
348			`PARAMETER C_ONE_TIMER_ONLY = 0`
349			`PARAMETER C_BASEADDR = 0x41c00000`
350			`PARAMETER C_HIGHADDR = 0x41c0ffff`
351			`BUS_INTERFACE SOPB = opb`
352			`PORT Interrupt = opb_timer_1_Interrupt`
353			`END`
354
355			`BEGIN opb_intc`
356			`PARAMETER INSTANCE = opb_intc_0`
357			`PARAMETER HW_VER = 1.00.c`
358			`PARAMETER C_BASEADDR = 0x41200000`
359			`PARAMETER C_HIGHADDR = 0x4120ffff`
360			`BUS_INTERFACE SOPB = opb`
361			`PORT Irq = EICC405EXTINPUTIRQ`
362			`PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & LEDs_Positions_IP2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt`
363			`END`
364
365			`BEGIN util_bus_split`
366			`PARAMETER INSTANCE = FLASH_2Mx32_util_bus_split_3`
367			`PARAMETER HW_VER = 1.00.a`
368			`PARAMETER C_SIZE_IN = 32`
369			`PARAMETER C_LEFT_POS = 9`
370			`PARAMETER C_SPLIT = 30`
371			`PORT Sig = fpga_0_FLASH_2Mx32_Mem_A_split`
372			`PORT Out1 = fpga_0_FLASH_2Mx32_Mem_A`
373			`END`
374
375			`BEGIN util_vector_logic`
376			`PARAMETER INSTANCE = sysclk_inv`
377			`PARAMETER HW_VER = 1.00.a`
378			`PARAMETER C_SIZE = 1`
379			`PARAMETER C_OPERATION = not`
380			`PORT Op1 = sys_clk_s`
381			`PORT Res = sys_clk_n_s`
382			`END`
383
384			`BEGIN util_vector_logic`
385			`PARAMETER INSTANCE = clk90_inv`
386			`PARAMETER HW_VER = 1.00.a`
387			`PARAMETER C_SIZE = 1`
388			`PARAMETER C_OPERATION = not`
389			`PORT Op1 = clk_90_s`
390			`PORT Res = clk_90_n_s`
391			`END`
392
393			`BEGIN util_vector_logic`
394			`PARAMETER INSTANCE = ddr_clk90_inv`
395			`PARAMETER HW_VER = 1.00.a`
396			`PARAMETER C_SIZE = 1`
397			`PARAMETER C_OPERATION = not`
398			`PORT Op1 = ddr_clk_90_s`
399			`PORT Res = ddr_clk_90_n_s`
400			`END`
401
402			`BEGIN dcm_module`
403			`PARAMETER INSTANCE = dcm_0`
404			`PARAMETER HW_VER = 1.00.c`
405			`PARAMETER C_CLK0_BUF = TRUE`
406			`PARAMETER C_CLK90_BUF = TRUE`
407			`PARAMETER C_CLKFX_BUF = TRUE`
408			`PARAMETER C_CLKFX_DIVIDE = 1`
409			`PARAMETER C_CLKFX_MULTIPLY = 3`
410			`PARAMETER C_CLKIN_PERIOD = 10.000000`
411			`PARAMETER C_CLK_FEEDBACK = 1X`
412			`PARAMETER C_DFS_FREQUENCY_MODE = HIGH`
413			`PARAMETER C_DLL_FREQUENCY_MODE = LOW`
414			`PARAMETER C_EXT_RESET_HIGH = 1`
415			`PORT CLKIN = dcm_clk_s`
416			`PORT CLK0 = sys_clk_s`
417			`PORT CLK90 = clk_90_s`
418			`PORT CLKFX = proc_clk_s`
419			`PORT CLKFB = sys_clk_s`
420			`PORT RST = net_gnd`
421			`PORT LOCKED = dcm_0_lock`
422			`END`
423
424			`BEGIN dcm_module`
425			`PARAMETER INSTANCE = dcm_1`
426			`PARAMETER HW_VER = 1.00.c`
427			`PARAMETER C_CLK0_BUF = TRUE`
428			`PARAMETER C_CLK90_BUF = TRUE`
429			`PARAMETER C_CLKIN_PERIOD = 10.000000`
430			`PARAMETER C_CLK_FEEDBACK = 1X`
431			`PARAMETER C_DLL_FREQUENCY_MODE = LOW`
432			`PARAMETER C_PHASE_SHIFT = 12`
433			`PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED`
434			`PARAMETER C_EXT_RESET_HIGH = 0`
435			`PORT CLKIN = ddr_feedback_s`
436			`PORT CLK90 = ddr_clk_90_s`
437			`PORT CLK0 = dcm_1_FB`
438			`PORT CLKFB = dcm_1_FB`
439			`PORT RST = dcm_0_lock`
440			`PORT LOCKED = dcm_1_lock`
441			`END`
442
443			`##`
444			`## timestamp hw`
445			`##`
446
447			`BEGIN timestamp`
448			`PARAMETER INSTANCE = timestamp_0`
449			`BUS_INTERFACE PORTB = plb_bram_if_cntlr_0_PORTA`
450			`PORT debug = fpga_0_scope`
451			`PORT reset = sys_bus_reset`
452			`PORT CPMFCMCLK = sys_clk_s`
453			`PORT APUFCMFLUSH = APUFCMFLUSH`
454			`PORT APUFCMDECODED = APUFCMDECODED`
455			`PORT APUFCMINSTRVALID = APUFCMINSTRVALID`
456			`PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID`
457			`PORT APUFCMDECUDI = APUFCMDECUDI`
458			`PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK`
459			`PORT APUFCMRADATA = APUFCMRADATA`
460			`PORT APUFCMRBDATA = APUFCMRBDATA`
461			`PORT FCMAPUDONE = FCMAPUDONE`
462			`PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY`
463			`END`
464
465			`BEGIN plb_bram_if_cntlr`
466			`PARAMETER INSTANCE = plb_bram_if_cntlr_0`
467			`PARAMETER HW_VER = 1.00.b`
468			`PARAMETER c_baseaddr = 0xCC000000`
469			`PARAMETER c_highaddr = 0xCC003FFF`
470			`PARAMETER c_plb_clk_period_ps = 10000`
471			`BUS_INTERFACE SPLB = plb`
472			`BUS_INTERFACE PORTA = plb_bram_if_cntlr_0_PORTA`
473			`END`