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robotron |
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# ##############################################################################
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# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
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# Wed Apr 11 16:23:26 2007
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# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
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# Family: virtex4
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# Device: xc4vfx12
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# Package: ff668
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# Speed Grade: -10
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# Processor: PPC 405
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# Processor clock frequency: 300.000000 MHz
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# Bus clock frequency: 100.000000 MHz
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# Debug interface: FPGA JTAG
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# On Chip Memory : 32 KB
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# Total Off Chip Memory : 72 MB
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# - DDR_SDRAM_32Mx32 = 64 MB
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# - FLASH_2Mx32 = 8 MB
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# ##############################################################################
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PARAMETER VERSION = 2.1.0
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PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
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PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
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PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
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PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
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PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin = fpga_0_Push_Buttons_Position_GPIO_IO, DIR = IO, VEC = [0:4]
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PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
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PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
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PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
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PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
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PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
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PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
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PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
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PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
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PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = O
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = O
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, DIR = O, VEC = [0:12]
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, DIR = O, VEC = [0:1]
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = O
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = O
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = O
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = O
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = O
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DM, DIR = O, VEC = [0:3]
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, DIR = IO, VEC = [0:3]
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PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, DIR = IO, VEC = [0:31]
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PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
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PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
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PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
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PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
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PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
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PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
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PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
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PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
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PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
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PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
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PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
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PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
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PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
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PORT fpga_0_FLASH_2Mx32_Mem_A_pin = fpga_0_FLASH_2Mx32_Mem_A, DIR = O, VEC = [9:29]
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PORT fpga_0_FLASH_2Mx32_Mem_WEN_pin = fpga_0_FLASH_2Mx32_Mem_WEN, DIR = O
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PORT fpga_0_FLASH_2Mx32_Mem_DQ_pin = fpga_0_FLASH_2Mx32_Mem_DQ, DIR = IO, VEC = [0:31]
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PORT fpga_0_FLASH_2Mx32_Mem_OEN_pin = fpga_0_FLASH_2Mx32_Mem_OEN, DIR = O, VEC = [0:0]
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PORT fpga_0_FLASH_2Mx32_Mem_CE_pin = fpga_0_FLASH_2Mx32_Mem_CE, DIR = O, VEC = [0:0]
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PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
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BEGIN ppc405_virtex4
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PARAMETER INSTANCE = ppc405_0
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PARAMETER HW_VER = 1.01.a
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BUS_INTERFACE JTAGPPC = jtagppc_0_0
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BUS_INTERFACE IPLB = plb
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BUS_INTERFACE DPLB = plb
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PORT PLBCLK = sys_clk_s
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PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
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PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
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PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
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PORT RSTC405RESETCHIP = RSTC405RESETCHIP
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PORT RSTC405RESETCORE = RSTC405RESETCORE
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PORT RSTC405RESETSYS = RSTC405RESETSYS
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PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
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PORT CPMC405CLOCK = proc_clk_s
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# APU timestamp UDI
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PARAMETER C_APU_CONTROL = 0x1E01
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PARAMETER C_APU_UDI_1 = 0xC07605
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# APU
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PORT CPMFCMCLK = sys_clk_s
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PORT APUFCMFLUSH = APUFCMFLUSH
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PORT APUFCMDECODED = APUFCMDECODED
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PORT APUFCMINSTRVALID = APUFCMINSTRVALID
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PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID
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PORT APUFCMDECUDI = APUFCMDECUDI
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PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK
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PORT APUFCMRADATA = APUFCMRADATA
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PORT APUFCMRBDATA = APUFCMRBDATA
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PORT FCMAPUDONE = FCMAPUDONE
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PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY
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END
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BEGIN jtagppc_cntlr
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PARAMETER INSTANCE = jtagppc_0
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PARAMETER HW_VER = 2.00.a
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BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
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END
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BEGIN proc_sys_reset
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PARAMETER INSTANCE = reset_block
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT Ext_Reset_In = sys_rst_s
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PORT Slowest_sync_clk = sys_clk_s
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PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
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PORT Core_Reset_Req = C405RSTCORERESETREQ
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PORT System_Reset_Req = C405RSTSYSRESETREQ
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PORT Rstc405resetchip = RSTC405RESETCHIP
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PORT Rstc405resetcore = RSTC405RESETCORE
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PORT Rstc405resetsys = RSTC405RESETSYS
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PORT Bus_Struct_Reset = sys_bus_reset
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PORT Dcm_locked = dcm_1_lock
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END
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BEGIN plb_v34
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PARAMETER INSTANCE = plb
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PARAMETER HW_VER = 1.02.a
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT SYS_Rst = sys_bus_reset
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PORT PLB_Clk = sys_clk_s
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END
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BEGIN opb_v20
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PARAMETER INSTANCE = opb
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PARAMETER HW_VER = 1.10.c
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT SYS_Rst = sys_bus_reset
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PORT OPB_Clk = sys_clk_s
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END
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BEGIN plb2opb_bridge
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PARAMETER INSTANCE = plb2opb
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_NUM_ADDR_RNG = 1
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PARAMETER C_RNG0_BASEADDR = 0x40000000
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PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
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BUS_INTERFACE SPLB = plb
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BUS_INTERFACE MOPB = opb
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END
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BEGIN opb_uart16550
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PARAMETER INSTANCE = RS232_Uart
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PARAMETER HW_VER = 1.00.e
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PARAMETER C_IS_A_16550 = 1
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PARAMETER C_BASEADDR = 0x40400000
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PARAMETER C_HIGHADDR = 0x4040ffff
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BUS_INTERFACE SOPB = opb
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PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
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PORT sin = fpga_0_RS232_Uart_sin
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PORT sout = fpga_0_RS232_Uart_sout
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END
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BEGIN opb_gpio
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PARAMETER INSTANCE = LEDs_4Bit
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PARAMETER HW_VER = 3.01.b
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PARAMETER C_INTERRUPT_PRESENT = 1
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PARAMETER C_GPIO_WIDTH = 4
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_IS_BIDIR = 1
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PARAMETER C_ALL_INPUTS = 0
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PARAMETER C_BASEADDR = 0x40000000
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PARAMETER C_HIGHADDR = 0x4000ffff
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BUS_INTERFACE SOPB = opb
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PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
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PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
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END
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BEGIN opb_gpio
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PARAMETER INSTANCE = LEDs_Positions
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PARAMETER HW_VER = 3.01.b
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PARAMETER C_INTERRUPT_PRESENT = 1
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PARAMETER C_GPIO_WIDTH = 5
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_IS_BIDIR = 1
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PARAMETER C_ALL_INPUTS = 0
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PARAMETER C_BASEADDR = 0x40020000
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PARAMETER C_HIGHADDR = 0x4002ffff
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BUS_INTERFACE SOPB = opb
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PORT IP2INTC_Irpt = LEDs_Positions_IP2INTC_Irpt
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PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
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END
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BEGIN opb_gpio
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PARAMETER INSTANCE = Push_Buttons_Position
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PARAMETER HW_VER = 3.01.b
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PARAMETER C_GPIO_WIDTH = 5
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_IS_BIDIR = 1
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PARAMETER C_ALL_INPUTS = 1
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PARAMETER C_BASEADDR = 0x40040000
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PARAMETER C_HIGHADDR = 0x4004ffff
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BUS_INTERFACE SOPB = opb
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PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO
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END
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BEGIN opb_iic
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PARAMETER INSTANCE = IIC_EEPROM
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PARAMETER HW_VER = 1.02.a
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PARAMETER C_CLK_FREQ = 100000000
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PARAMETER C_IIC_FREQ = 100000
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PARAMETER C_TEN_BIT_ADR = 0
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PARAMETER C_BASEADDR = 0x40800000
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PARAMETER C_HIGHADDR = 0x4080ffff
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BUS_INTERFACE SOPB = opb
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PORT Scl = fpga_0_IIC_EEPROM_Scl
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PORT Sda = fpga_0_IIC_EEPROM_Sda
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END
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BEGIN opb_sysace
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PARAMETER INSTANCE = SysACE_CompactFlash
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PARAMETER HW_VER = 1.00.c
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PARAMETER C_MEM_WIDTH = 16
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PARAMETER C_BASEADDR = 0x41800000
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PARAMETER C_HIGHADDR = 0x4180ffff
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BUS_INTERFACE SOPB = opb
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PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
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PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
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PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA
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PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
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PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
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PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
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PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
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PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
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END
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BEGIN plb_ddr
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PARAMETER INSTANCE = DDR_SDRAM_64Mx32
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_PLB_CLK_PERIOD_PS = 10000
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PARAMETER C_REG_DIMM = 0
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PARAMETER C_DDR_TMRD = 20000
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PARAMETER C_DDR_TWR = 20000
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PARAMETER C_DDR_TRAS = 60000
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PARAMETER C_DDR_TRC = 90000
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PARAMETER C_DDR_TRFC = 80000
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PARAMETER C_DDR_TRCD = 30000
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PARAMETER C_DDR_TRRD = 15000
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PARAMETER C_DDR_TRP = 30000
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PARAMETER C_DDR_TREFI = 7800000
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PARAMETER C_DDR_AWIDTH = 13
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PARAMETER C_DDR_COL_AWIDTH = 9
|
253 |
|
|
PARAMETER C_DDR_BANK_AWIDTH = 2
|
254 |
|
|
PARAMETER C_DDR_DWIDTH = 32
|
255 |
|
|
PARAMETER C_MEM0_BASEADDR = 0x00000000
|
256 |
|
|
PARAMETER C_MEM0_HIGHADDR = 0x03ffffff
|
257 |
|
|
BUS_INTERFACE SPLB = plb
|
258 |
|
|
PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
|
259 |
|
|
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
|
260 |
|
|
PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
|
261 |
|
|
PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
|
262 |
|
|
PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
|
263 |
|
|
PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
|
264 |
|
|
PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
|
265 |
|
|
PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
|
266 |
|
|
PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
|
267 |
|
|
PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
|
268 |
|
|
PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
|
269 |
|
|
PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
|
270 |
|
|
PORT Clk90_in = clk_90_s
|
271 |
|
|
PORT Clk90_in_n = clk_90_n_s
|
272 |
|
|
PORT PLB_Clk_n = sys_clk_n_s
|
273 |
|
|
PORT DDR_Clk90_in = ddr_clk_90_s
|
274 |
|
|
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
|
275 |
|
|
END
|
276 |
|
|
|
277 |
|
|
BEGIN opb_ethernet
|
278 |
|
|
PARAMETER INSTANCE = Ethernet_MAC
|
279 |
|
|
PARAMETER HW_VER = 1.04.a
|
280 |
|
|
PARAMETER C_DMA_PRESENT = 1
|
281 |
|
|
PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
|
282 |
|
|
PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
|
283 |
|
|
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
|
284 |
|
|
PARAMETER C_BASEADDR = 0x40c00000
|
285 |
|
|
PARAMETER C_HIGHADDR = 0x40c0ffff
|
286 |
|
|
BUS_INTERFACE SOPB = opb
|
287 |
|
|
PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
|
288 |
|
|
PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
|
289 |
|
|
PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
|
290 |
|
|
PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
|
291 |
|
|
PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
|
292 |
|
|
PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
|
293 |
|
|
PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
|
294 |
|
|
PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
|
295 |
|
|
PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
|
296 |
|
|
PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
|
297 |
|
|
PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
|
298 |
|
|
PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
|
299 |
|
|
PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
|
300 |
|
|
PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
|
301 |
|
|
END
|
302 |
|
|
|
303 |
|
|
BEGIN plb_emc
|
304 |
|
|
PARAMETER INSTANCE = FLASH_2Mx32
|
305 |
|
|
PARAMETER HW_VER = 2.00.a
|
306 |
|
|
PARAMETER C_PLB_CLK_PERIOD_PS = 10000
|
307 |
|
|
PARAMETER C_NUM_BANKS_MEM = 1
|
308 |
|
|
PARAMETER C_MAX_MEM_WIDTH = 32
|
309 |
|
|
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
|
310 |
|
|
PARAMETER C_MEM0_WIDTH = 32
|
311 |
|
|
PARAMETER C_SYNCH_MEM_0 = 0
|
312 |
|
|
PARAMETER C_TCEDV_PS_MEM_0 = 110000
|
313 |
|
|
PARAMETER C_TWC_PS_MEM_0 = 55000
|
314 |
|
|
PARAMETER C_TAVDV_PS_MEM_0 = 110000
|
315 |
|
|
PARAMETER C_TWP_PS_MEM_0 = 55000
|
316 |
|
|
PARAMETER C_THZCE_PS_MEM_0 = 10000
|
317 |
|
|
PARAMETER C_TLZWE_PS_MEM_0 = 35000
|
318 |
|
|
PARAMETER C_MEM0_BASEADDR = 0x06000000
|
319 |
|
|
PARAMETER C_MEM0_HIGHADDR = 0x067fffff
|
320 |
|
|
BUS_INTERFACE SPLB = plb
|
321 |
|
|
PORT Mem_A = fpga_0_FLASH_2Mx32_Mem_A_split
|
322 |
|
|
PORT Mem_WEN = fpga_0_FLASH_2Mx32_Mem_WEN
|
323 |
|
|
PORT Mem_DQ = fpga_0_FLASH_2Mx32_Mem_DQ
|
324 |
|
|
PORT Mem_OEN = fpga_0_FLASH_2Mx32_Mem_OEN
|
325 |
|
|
PORT Mem_CE = fpga_0_FLASH_2Mx32_Mem_CE
|
326 |
|
|
END
|
327 |
|
|
|
328 |
|
|
BEGIN plb_bram_if_cntlr
|
329 |
|
|
PARAMETER INSTANCE = plb_bram_if_cntlr_1
|
330 |
|
|
PARAMETER HW_VER = 1.00.b
|
331 |
|
|
PARAMETER c_plb_clk_period_ps = 10000
|
332 |
|
|
PARAMETER c_baseaddr = 0xffff8000
|
333 |
|
|
PARAMETER c_highaddr = 0xffffffff
|
334 |
|
|
BUS_INTERFACE SPLB = plb
|
335 |
|
|
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
|
336 |
|
|
END
|
337 |
|
|
|
338 |
|
|
BEGIN bram_block
|
339 |
|
|
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
|
340 |
|
|
PARAMETER HW_VER = 1.00.a
|
341 |
|
|
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
|
342 |
|
|
END
|
343 |
|
|
|
344 |
|
|
BEGIN opb_timer
|
345 |
|
|
PARAMETER INSTANCE = opb_timer_1
|
346 |
|
|
PARAMETER HW_VER = 1.00.b
|
347 |
|
|
PARAMETER C_COUNT_WIDTH = 32
|
348 |
|
|
PARAMETER C_ONE_TIMER_ONLY = 0
|
349 |
|
|
PARAMETER C_BASEADDR = 0x41c00000
|
350 |
|
|
PARAMETER C_HIGHADDR = 0x41c0ffff
|
351 |
|
|
BUS_INTERFACE SOPB = opb
|
352 |
|
|
PORT Interrupt = opb_timer_1_Interrupt
|
353 |
|
|
END
|
354 |
|
|
|
355 |
|
|
BEGIN opb_intc
|
356 |
|
|
PARAMETER INSTANCE = opb_intc_0
|
357 |
|
|
PARAMETER HW_VER = 1.00.c
|
358 |
|
|
PARAMETER C_BASEADDR = 0x41200000
|
359 |
|
|
PARAMETER C_HIGHADDR = 0x4120ffff
|
360 |
|
|
BUS_INTERFACE SOPB = opb
|
361 |
|
|
PORT Irq = EICC405EXTINPUTIRQ
|
362 |
|
|
PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & LEDs_Positions_IP2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt
|
363 |
|
|
END
|
364 |
|
|
|
365 |
|
|
BEGIN util_bus_split
|
366 |
|
|
PARAMETER INSTANCE = FLASH_2Mx32_util_bus_split_3
|
367 |
|
|
PARAMETER HW_VER = 1.00.a
|
368 |
|
|
PARAMETER C_SIZE_IN = 32
|
369 |
|
|
PARAMETER C_LEFT_POS = 9
|
370 |
|
|
PARAMETER C_SPLIT = 30
|
371 |
|
|
PORT Sig = fpga_0_FLASH_2Mx32_Mem_A_split
|
372 |
|
|
PORT Out1 = fpga_0_FLASH_2Mx32_Mem_A
|
373 |
|
|
END
|
374 |
|
|
|
375 |
|
|
BEGIN util_vector_logic
|
376 |
|
|
PARAMETER INSTANCE = sysclk_inv
|
377 |
|
|
PARAMETER HW_VER = 1.00.a
|
378 |
|
|
PARAMETER C_SIZE = 1
|
379 |
|
|
PARAMETER C_OPERATION = not
|
380 |
|
|
PORT Op1 = sys_clk_s
|
381 |
|
|
PORT Res = sys_clk_n_s
|
382 |
|
|
END
|
383 |
|
|
|
384 |
|
|
BEGIN util_vector_logic
|
385 |
|
|
PARAMETER INSTANCE = clk90_inv
|
386 |
|
|
PARAMETER HW_VER = 1.00.a
|
387 |
|
|
PARAMETER C_SIZE = 1
|
388 |
|
|
PARAMETER C_OPERATION = not
|
389 |
|
|
PORT Op1 = clk_90_s
|
390 |
|
|
PORT Res = clk_90_n_s
|
391 |
|
|
END
|
392 |
|
|
|
393 |
|
|
BEGIN util_vector_logic
|
394 |
|
|
PARAMETER INSTANCE = ddr_clk90_inv
|
395 |
|
|
PARAMETER HW_VER = 1.00.a
|
396 |
|
|
PARAMETER C_SIZE = 1
|
397 |
|
|
PARAMETER C_OPERATION = not
|
398 |
|
|
PORT Op1 = ddr_clk_90_s
|
399 |
|
|
PORT Res = ddr_clk_90_n_s
|
400 |
|
|
END
|
401 |
|
|
|
402 |
|
|
BEGIN dcm_module
|
403 |
|
|
PARAMETER INSTANCE = dcm_0
|
404 |
|
|
PARAMETER HW_VER = 1.00.c
|
405 |
|
|
PARAMETER C_CLK0_BUF = TRUE
|
406 |
|
|
PARAMETER C_CLK90_BUF = TRUE
|
407 |
|
|
PARAMETER C_CLKFX_BUF = TRUE
|
408 |
|
|
PARAMETER C_CLKFX_DIVIDE = 1
|
409 |
|
|
PARAMETER C_CLKFX_MULTIPLY = 3
|
410 |
|
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
411 |
|
|
PARAMETER C_CLK_FEEDBACK = 1X
|
412 |
|
|
PARAMETER C_DFS_FREQUENCY_MODE = HIGH
|
413 |
|
|
PARAMETER C_DLL_FREQUENCY_MODE = LOW
|
414 |
|
|
PARAMETER C_EXT_RESET_HIGH = 1
|
415 |
|
|
PORT CLKIN = dcm_clk_s
|
416 |
|
|
PORT CLK0 = sys_clk_s
|
417 |
|
|
PORT CLK90 = clk_90_s
|
418 |
|
|
PORT CLKFX = proc_clk_s
|
419 |
|
|
PORT CLKFB = sys_clk_s
|
420 |
|
|
PORT RST = net_gnd
|
421 |
|
|
PORT LOCKED = dcm_0_lock
|
422 |
|
|
END
|
423 |
|
|
|
424 |
|
|
BEGIN dcm_module
|
425 |
|
|
PARAMETER INSTANCE = dcm_1
|
426 |
|
|
PARAMETER HW_VER = 1.00.c
|
427 |
|
|
PARAMETER C_CLK0_BUF = TRUE
|
428 |
|
|
PARAMETER C_CLK90_BUF = TRUE
|
429 |
|
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
430 |
|
|
PARAMETER C_CLK_FEEDBACK = 1X
|
431 |
|
|
PARAMETER C_DLL_FREQUENCY_MODE = LOW
|
432 |
|
|
PARAMETER C_PHASE_SHIFT = 12
|
433 |
|
|
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
|
434 |
|
|
PARAMETER C_EXT_RESET_HIGH = 0
|
435 |
|
|
PORT CLKIN = ddr_feedback_s
|
436 |
|
|
PORT CLK90 = ddr_clk_90_s
|
437 |
|
|
PORT CLK0 = dcm_1_FB
|
438 |
|
|
PORT CLKFB = dcm_1_FB
|
439 |
|
|
PORT RST = dcm_0_lock
|
440 |
|
|
PORT LOCKED = dcm_1_lock
|
441 |
|
|
END
|
442 |
|
|
|
443 |
|
|
##
|
444 |
|
|
## timestamp hw
|
445 |
|
|
##
|
446 |
|
|
|
447 |
|
|
BEGIN timestamp
|
448 |
|
|
PARAMETER INSTANCE = timestamp_0
|
449 |
|
|
BUS_INTERFACE PORTB = plb_bram_if_cntlr_0_PORTA
|
450 |
|
|
PORT debug = fpga_0_scope
|
451 |
|
|
PORT reset = sys_bus_reset
|
452 |
|
|
PORT CPMFCMCLK = sys_clk_s
|
453 |
|
|
PORT APUFCMFLUSH = APUFCMFLUSH
|
454 |
|
|
PORT APUFCMDECODED = APUFCMDECODED
|
455 |
|
|
PORT APUFCMINSTRVALID = APUFCMINSTRVALID
|
456 |
|
|
PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID
|
457 |
|
|
PORT APUFCMDECUDI = APUFCMDECUDI
|
458 |
|
|
PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK
|
459 |
|
|
PORT APUFCMRADATA = APUFCMRADATA
|
460 |
|
|
PORT APUFCMRBDATA = APUFCMRBDATA
|
461 |
|
|
PORT FCMAPUDONE = FCMAPUDONE
|
462 |
|
|
PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY
|
463 |
|
|
END
|
464 |
|
|
|
465 |
|
|
BEGIN plb_bram_if_cntlr
|
466 |
|
|
PARAMETER INSTANCE = plb_bram_if_cntlr_0
|
467 |
|
|
PARAMETER HW_VER = 1.00.b
|
468 |
|
|
PARAMETER c_baseaddr = 0xCC000000
|
469 |
|
|
PARAMETER c_highaddr = 0xCC003FFF
|
470 |
|
|
PARAMETER c_plb_clk_period_ps = 10000
|
471 |
|
|
BUS_INTERFACE SPLB = plb
|
472 |
|
|
BUS_INTERFACE PORTA = plb_bram_if_cntlr_0_PORTA
|
473 |
|
|
END
|