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[/] [tiny_aes/] [trunk/] [rtl/] [aes_192.v] - Blame information for rev 12

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1 6 homer.hsin
/*
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 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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 *
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 * Licensed under the Apache License, Version 2.0 (the "License");
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 * you may not use this file except in compliance with the License.
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 * You may obtain a copy of the License at
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 *
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 * http://www.apache.org/licenses/LICENSE-2.0
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 *
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 * Unless required by applicable law or agreed to in writing, software
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 * distributed under the License is distributed on an "AS IS" BASIS,
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 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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 * See the License for the specific language governing permissions and
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 * limitations under the License.
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 */
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module aes_192 (clk, state, key, out);
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    input          clk;
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    input  [127:0] state;
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    input  [191:0] key;
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    output [127:0] out;
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    reg    [127:0] s0;
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    reg    [191:0] k0;
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    wire   [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
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    wire   [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
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    wire   [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
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    always @ (posedge clk)
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      begin
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        s0 <= state ^ key[191:64];
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        k0 <= key;
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      end
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    expand_key_type_D_192  a0 (clk, k0, 8'h1,   k1,  k0b);
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    expand_key_type_B_192  a1 (clk, k1,         k2,  k1b);
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    expand_key_type_A_192  a2 (clk, k2, 8'h2,   k3,  k2b);
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    expand_key_type_C_192  a3 (clk, k3, 8'h4,   k4,  k3b);
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    expand_key_type_B_192  a4 (clk, k4,         k5,  k4b);
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    expand_key_type_A_192  a5 (clk, k5, 8'h8,   k6,  k5b);
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    expand_key_type_C_192  a6 (clk, k6, 8'h10,  k7,  k6b);
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    expand_key_type_B_192  a7 (clk, k7,         k8,  k7b);
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    expand_key_type_A_192  a8 (clk, k8, 8'h20,  k9,  k8b);
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    expand_key_type_C_192  a9 (clk, k9, 8'h40, k10,  k9b);
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    expand_key_type_B_192 a10 (clk,k10,        k11, k10b);
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    expand_key_type_A_192 a11 (clk,k11, 8'h80,    , k11b);
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    one_round
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         r1 (clk, s0, k0b, s1),
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         r2 (clk, s1, k1b, s2),
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         r3 (clk, s2, k2b, s3),
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         r4 (clk, s3, k3b, s4),
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         r5 (clk, s4, k4b, s5),
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         r6 (clk, s5, k5b, s6),
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         r7 (clk, s6, k6b, s7),
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         r8 (clk, s7, k7b, s8),
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         r9 (clk, s8, k8b, s9),
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        r10 (clk, s9, k9b, s10),
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        r11 (clk, s10, k10b, s11);
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    final_round
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        rf (clk, s11, k11b, out);
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endmodule
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/* expand k0,k1,k2,k3 for every two clock cycles */
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module expand_key_type_A_192 (clk, in, rcon, out_1, out_2);
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    input              clk;
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    input      [191:0] in;
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    input      [7:0]   rcon;
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    output reg [191:0] out_1;
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    output     [127:0] out_2;
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    wire       [31:0]  k0, k1, k2, k3, k4, k5,
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                       v0, v1, v2, v3;
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    reg        [31:0]  k0a, k1a, k2a, k3a, k4a, k5a;
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    wire       [31:0]  k0b, k1b, k2b, k3b, k4b, k5b, k6a;
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    assign {k0, k1, k2, k3, k4, k5} = in;
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    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
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    assign v1 = v0 ^ k1;
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    assign v2 = v1 ^ k2;
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    assign v3 = v2 ^ k3;
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    always @ (posedge clk)
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        {k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, v2, v3, k4, k5};
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    S4
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        S4_0 (clk, {k5[23:0], k5[31:24]}, k6a);
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    assign k0b = k0a ^ k6a;
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    assign k1b = k1a ^ k6a;
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    assign k2b = k2a ^ k6a;
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    assign k3b = k3a ^ k6a;
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    assign {k4b, k5b} = {k4a, k5a};
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    always @ (posedge clk)
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        out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
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    assign out_2 = {k0b, k1b, k2b, k3b};
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endmodule
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/* expand k2,k3,k4,k5 for every two clock cycles */
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module expand_key_type_B_192 (clk, in, out_1, out_2);
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    input              clk;
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    input      [191:0] in;
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    output reg [191:0] out_1;
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    output     [127:0] out_2;
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    wire       [31:0]  k0, k1, k2, k3, k4, k5,
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                       v2, v3, v4, v5;
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    reg        [31:0]  k0a, k1a, k2a, k3a, k4a, k5a;
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    assign {k0, k1, k2, k3, k4, k5} = in;
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    assign v2 = k1 ^ k2;
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    assign v3 = v2 ^ k3;
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    assign v4 = v3 ^ k4;
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    assign v5 = v4 ^ k5;
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    always @ (posedge clk)
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        {k0a, k1a, k2a, k3a, k4a, k5a} <= {k0, k1, v2, v3, v4, v5};
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    always @ (posedge clk)
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        out_1 <= {k0a, k1a, k2a, k3a, k4a, k5a};
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    assign out_2 = {k2a, k3a, k4a, k5a};
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endmodule
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/* expand k0,k1,k4,k5 for every two clock cycles */
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module expand_key_type_C_192 (clk, in, rcon, out_1, out_2);
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    input              clk;
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    input      [191:0] in;
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    input      [7:0]   rcon;
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    output reg [191:0] out_1;
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    output     [127:0] out_2;
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    wire       [31:0]  k0, k1, k2, k3, k4, k5,
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                       v4, v5, v0, v1;
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    reg        [31:0]  k0a, k1a, k2a, k3a, k4a, k5a;
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    wire       [31:0]  k0b, k1b, k2b, k3b, k4b, k5b, k6a;
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    assign {k0, k1, k2, k3, k4, k5} = in;
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    assign v4 = k3 ^ k4;
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    assign v5 = v4 ^ k5;
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    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
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    assign v1 = v0 ^ k1;
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    always @ (posedge clk)
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        {k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, v4, v5};
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    S4
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        S4_0 (clk, {v5[23:0], v5[31:24]}, k6a);
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    assign k0b = k0a ^ k6a;
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    assign k1b = k1a ^ k6a;
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    assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
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    always @ (posedge clk)
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        out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
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    assign out_2 = {k4b, k5b, k0b, k1b};
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endmodule
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/* expand k0,k1 for every two clock cycles */
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module expand_key_type_D_192 (clk, in, rcon, out_1, out_2);
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    input              clk;
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    input      [191:0] in;
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    input      [7:0]   rcon;
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    output reg [191:0] out_1;
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    output     [127:0] out_2;
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    wire       [31:0]  k0, k1, k2, k3, k4, k5,
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                       v0, v1;
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    reg        [31:0]  k0a, k1a, k2a, k3a, k4a, k5a;
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    wire       [31:0]  k0b, k1b, k2b, k3b, k4b, k5b, k6a;
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    assign {k0, k1, k2, k3, k4, k5} = in;
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    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
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    assign v1 = v0 ^ k1;
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    always @ (posedge clk)
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        {k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, k4, k5};
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    S4
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        S4_0 (clk, {k5[23:0], k5[31:24]}, k6a);
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    assign k0b = k0a ^ k6a;
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    assign k1b = k1a ^ k6a;
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    assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
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    always @ (posedge clk)
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        out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
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    assign out_2 = {k4b, k5b, k0b, k1b};
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endmodule

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