Subversion Repositories tiny_encryption_algorithm

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-- Company: 

-- Engineer:

--

-- Create Date:   22:14:25 07/09/2015

-- Design Name:   

-- Module Name:   C:/Users/FeketeBV/projects/fpga/tea/tea1tb.vhd

-- Project Name:  tea

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: tea1

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY tea1tb IS

END tea1tb;

ARCHITECTURE behavior OF tea1tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT tea1

    PORT(

         clock, reset : IN  std_logic;

         start : IN  std_logic;

         ready : OUT  std_logic;

         key : IN  std_logic_vector(127 downto 0);

         text : IN  std_logic_vector(63 downto 0);

         cipher : OUT  std_logic_vector(63 downto 0)

        );

    END COMPONENT;

   --Inputs

   signal reset : std_logic := '0';

   signal clock : std_logic := '0';

   signal start : std_logic := '0';

   signal key : std_logic_vector(127 downto 0) := (others => '0');

   signal text : std_logic_vector(63 downto 0) := (others => '0');

        --Outputs

   signal ready : std_logic;

   signal cipher : std_logic_vector(63 downto 0);

   -- Clock period definitions

   constant clock_period : time := 10 ns;

BEGIN

        -- Instantiate the Unit Under Test (UUT)

   uut: tea1 PORT MAP (

                         reset => reset,

          clock => clock,

          start => start,

          ready => ready,

          key => key,

          text => text,

          cipher => cipher

        );

   -- Clock process definitions

   clock_process :process

   begin

                clock <= '0';

                wait for clock_period/2;

                clock <= '1';

                wait for clock_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin

      -- hold reset state for 100 ns.

      reset <= '1';

                wait for 100 ns;

                reset <= '0';

      wait for clock_period*10;

      key <= x"abcdef00111111111111111187654321";

                text <= x"1234567812345678";

                wait for clock_period;

                start <= '1';

      wait for clock_period;

      start <= '0';

                wait for clock_period*65;

      wait;

      -- insert stimulus here 

      wait;

   end process;

END;

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