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[/] [tiny_tate_bilinear_pairing/] [trunk/] [group_size_is_697_bits/] [testbench/] [test_pairing.v] - Blame information for rev 18

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1 18 homer.hsin
/*
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 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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 *
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 * Licensed under the Apache License, Version 2.0 (the "License");
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 * you may not use this file except in compliance with the License.
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 * You may obtain a copy of the License at
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 *
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 * http://www.apache.org/licenses/LICENSE-2.0
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 *
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 * Unless required by applicable law or agreed to in writing, software
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 * distributed under the License is distributed on an "AS IS" BASIS,
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 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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 * See the License for the specific language governing permissions and
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 * limitations under the License.
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 */
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`timescale 1ns / 1ps
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`define P 20 // clock period 
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`define M     503         // M is the degree of the irreducible polynomial
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`define WIDTH (2*`M-1)    // width for a GF(3^M) element
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`define WIDTH_D0 (1008-1)
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module test_pairing;
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        // Inputs
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        reg clk;
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        reg reset;
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        reg sel;
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        reg [5:0] addr;
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        reg w;
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    reg update;
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    reg ready;
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    reg i;
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        // Outputs
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        wire done;
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    wire o;
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    // Buffers
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        reg [`WIDTH_D0:0] out;
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        // Instantiate the Unit Under Test (UUT)
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        pairing uut (
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        .clk(clk),
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        .reset(reset),
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        .sel(sel),
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        .addr(addr),
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        .w(w),
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        .update(update),
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        .ready(ready),
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        .i(i),
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        .o(o),
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        .done(done)
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        );
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        initial begin
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                // Initialize Inputs
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                clk = 0;
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                reset = 0;
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                sel = 0;
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                addr = 0;
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                w = 0;
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        update = 0;
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        ready = 0;
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        i = 0;
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        out = 0;
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                // Wait 100 ns for global reset to finish
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                #100;
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                // Add stimulus here
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        /* keep FSM silent */
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        reset = 1;
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            /* init xp, yp, xq, yq */
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            write(3, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
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            write(5, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
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            write(6, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
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            write(7, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
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            /* read back. uncomment me if error happens */
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            /* read(3);
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            $display("xp = %h", out);
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            read(5);
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            $display("yp = %h", out);
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            read(6);
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            $display("xq = %h", out);
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            read(7);
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            $display("yq = %h", out);*/
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        reset = 0;
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        sel = 0; w = 0;
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        @(posedge done);
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        @(negedge clk);
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            read(9);
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            check(1006'h2965a664a44a85426524a19821aa12a42605258540a056525248149a96061560451a6a95861496a8140985a8902955951552696a425948159a2141a0aaa5840442851218546a49a2a2496658644656a9a6162a5098a025645151aa668902aaa102a0805900488980545120462896204252584282868449488a00884995a9);
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            read(10);
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            check(1006'h244151402864a58144a0509a26121148024224a299a4062a248944801589895a04a8a681a4245492a5aa5958901a142120515582941220529512012554699982594528256086220a55641a5a212511aa50a0a4a198200560a628994925551249659028459a8a24688191044a08529064119949a112564a52082068858890);
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            read(11);
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            check(1006'h180645a168488aa651260a226a124a66080299922a8595404428610808262992a22682905a55625665824505a609882a88422a886296551a6221a29a16aa11141a12280942aa84094946860205964a26669684569054810a914124a086212a5a5821440119015a98844101854a9951141981221169224a1599a11914a504);
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            read(12);
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            check(1006'h18a6911a415584242209a6a52629464160400a0a45554552866a9a20a8520a551856814024118140a144a151604449609aa24085a609a2a0851285445a96602a2461212641204a591a66a5604211004882191912920862a9860a861a88a005516611622a44880a48690412292244615156004952521664a84a5961510225);
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            read(13);
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            check(1006'h250869062a008a1882940945a20441680111009595094282260a95488aaa4588262641912aa64a29a8526408451940619612014212441090209588888a004002462206a8294a158809258852650a15226a99808952201191614814166198a52a8151454968a288295994286919811691aa21048661a5288402182a558215);
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            read(14);
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            check(1006'h016641111896469064656661124a160226a89485469954a6a5406aa28590655a018922965688045984585a61888165085289a61a051258a59459210842108082566966664250991442a2941521806608610a52182256042680a4881900605a8459260a9824295244629865a6a62a18958a66955152404814065588150894);
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            $display("Good");
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        $finish;
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        end
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    initial #100 forever #(`P/2) clk = ~clk;
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    task write;
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        input [5:0] adr;
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        input [`WIDTH_D0:0] dat;
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        integer j;
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        begin
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            sel = 1;
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            w = 0;
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            addr = adr;
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            update = 1;
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            #`P;
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            update = 0;
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            ready = 1;
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            for(j=0;j<`WIDTH_D0+1;j=j+1)
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               begin
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               i = dat[j];
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               #`P;
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               end
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            ready = 0;
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            w = 1; #`P; w = 0;
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        end
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    endtask
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    task read;
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        input [5:0] adr;
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        integer j;
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        begin
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            sel = 1;
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            w = 0;
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            addr = adr;
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            #`P;
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            update = 1;
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            #`P;
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            update = 0;
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            out = 0;
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            ready = 1;
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            for(j=0;j<`WIDTH_D0+1;j=j+1)
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               begin
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               out = {o, out[`WIDTH_D0:1]};
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               #`P;
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               end
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        end
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    endtask
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    task check;
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        input [`WIDTH_D0:0] wish;
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        begin
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            if (out !== wish)
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                begin $display("Error!"); $finish; end
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        end
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    endtask
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endmodule
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