1 |
18 |
homer.hsin |
/*
|
2 |
|
|
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
|
3 |
|
|
*
|
4 |
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
5 |
|
|
* you may not use this file except in compliance with the License.
|
6 |
|
|
* You may obtain a copy of the License at
|
7 |
|
|
*
|
8 |
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
9 |
|
|
*
|
10 |
|
|
* Unless required by applicable law or agreed to in writing, software
|
11 |
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
12 |
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
13 |
|
|
* See the License for the specific language governing permissions and
|
14 |
|
|
* limitations under the License.
|
15 |
|
|
*/
|
16 |
|
|
|
17 |
|
|
`timescale 1ns / 1ps
|
18 |
|
|
`define P 20 // clock period
|
19 |
|
|
`define M 503 // M is the degree of the irreducible polynomial
|
20 |
|
|
`define WIDTH (2*`M-1) // width for a GF(3^M) element
|
21 |
|
|
`define WIDTH_D0 (1008-1)
|
22 |
|
|
|
23 |
|
|
module test_pairing;
|
24 |
|
|
|
25 |
|
|
// Inputs
|
26 |
|
|
reg clk;
|
27 |
|
|
reg reset;
|
28 |
|
|
reg sel;
|
29 |
|
|
reg [5:0] addr;
|
30 |
|
|
reg w;
|
31 |
|
|
reg update;
|
32 |
|
|
reg ready;
|
33 |
|
|
reg i;
|
34 |
|
|
|
35 |
|
|
// Outputs
|
36 |
|
|
wire done;
|
37 |
|
|
wire o;
|
38 |
|
|
|
39 |
|
|
// Buffers
|
40 |
|
|
reg [`WIDTH_D0:0] out;
|
41 |
|
|
|
42 |
|
|
// Instantiate the Unit Under Test (UUT)
|
43 |
|
|
pairing uut (
|
44 |
|
|
.clk(clk),
|
45 |
|
|
.reset(reset),
|
46 |
|
|
.sel(sel),
|
47 |
|
|
.addr(addr),
|
48 |
|
|
.w(w),
|
49 |
|
|
.update(update),
|
50 |
|
|
.ready(ready),
|
51 |
|
|
.i(i),
|
52 |
|
|
.o(o),
|
53 |
|
|
.done(done)
|
54 |
|
|
);
|
55 |
|
|
|
56 |
|
|
initial begin
|
57 |
|
|
// Initialize Inputs
|
58 |
|
|
clk = 0;
|
59 |
|
|
reset = 0;
|
60 |
|
|
sel = 0;
|
61 |
|
|
addr = 0;
|
62 |
|
|
w = 0;
|
63 |
|
|
update = 0;
|
64 |
|
|
ready = 0;
|
65 |
|
|
i = 0;
|
66 |
|
|
out = 0;
|
67 |
|
|
|
68 |
|
|
// Wait 100 ns for global reset to finish
|
69 |
|
|
#100;
|
70 |
|
|
|
71 |
|
|
// Add stimulus here
|
72 |
|
|
/* keep FSM silent */
|
73 |
|
|
reset = 1;
|
74 |
|
|
/* init xp, yp, xq, yq */
|
75 |
|
|
write(3, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
|
76 |
|
|
write(5, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
|
77 |
|
|
write(6, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
|
78 |
|
|
write(7, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
|
79 |
|
|
/* read back. uncomment me if error happens */
|
80 |
|
|
/* read(3);
|
81 |
|
|
$display("xp = %h", out);
|
82 |
|
|
read(5);
|
83 |
|
|
$display("yp = %h", out);
|
84 |
|
|
read(6);
|
85 |
|
|
$display("xq = %h", out);
|
86 |
|
|
read(7);
|
87 |
|
|
$display("yq = %h", out);*/
|
88 |
|
|
reset = 0;
|
89 |
|
|
|
90 |
|
|
sel = 0; w = 0;
|
91 |
|
|
@(posedge done);
|
92 |
|
|
@(negedge clk);
|
93 |
|
|
read(9);
|
94 |
|
|
check(1006'h2965a664a44a85426524a19821aa12a42605258540a056525248149a96061560451a6a95861496a8140985a8902955951552696a425948159a2141a0aaa5840442851218546a49a2a2496658644656a9a6162a5098a025645151aa668902aaa102a0805900488980545120462896204252584282868449488a00884995a9);
|
95 |
|
|
read(10);
|
96 |
|
|
check(1006'h244151402864a58144a0509a26121148024224a299a4062a248944801589895a04a8a681a4245492a5aa5958901a142120515582941220529512012554699982594528256086220a55641a5a212511aa50a0a4a198200560a628994925551249659028459a8a24688191044a08529064119949a112564a52082068858890);
|
97 |
|
|
read(11);
|
98 |
|
|
check(1006'h180645a168488aa651260a226a124a66080299922a8595404428610808262992a22682905a55625665824505a609882a88422a886296551a6221a29a16aa11141a12280942aa84094946860205964a26669684569054810a914124a086212a5a5821440119015a98844101854a9951141981221169224a1599a11914a504);
|
99 |
|
|
read(12);
|
100 |
|
|
check(1006'h18a6911a415584242209a6a52629464160400a0a45554552866a9a20a8520a551856814024118140a144a151604449609aa24085a609a2a0851285445a96602a2461212641204a591a66a5604211004882191912920862a9860a861a88a005516611622a44880a48690412292244615156004952521664a84a5961510225);
|
101 |
|
|
read(13);
|
102 |
|
|
check(1006'h250869062a008a1882940945a20441680111009595094282260a95488aaa4588262641912aa64a29a8526408451940619612014212441090209588888a004002462206a8294a158809258852650a15226a99808952201191614814166198a52a8151454968a288295994286919811691aa21048661a5288402182a558215);
|
103 |
|
|
read(14);
|
104 |
|
|
check(1006'h016641111896469064656661124a160226a89485469954a6a5406aa28590655a018922965688045984585a61888165085289a61a051258a59459210842108082566966664250991442a2941521806608610a52182256042680a4881900605a8459260a9824295244629865a6a62a18958a66955152404814065588150894);
|
105 |
|
|
$display("Good");
|
106 |
|
|
$finish;
|
107 |
|
|
end
|
108 |
|
|
|
109 |
|
|
initial #100 forever #(`P/2) clk = ~clk;
|
110 |
|
|
|
111 |
|
|
task write;
|
112 |
|
|
input [5:0] adr;
|
113 |
|
|
input [`WIDTH_D0:0] dat;
|
114 |
|
|
integer j;
|
115 |
|
|
begin
|
116 |
|
|
sel = 1;
|
117 |
|
|
w = 0;
|
118 |
|
|
addr = adr;
|
119 |
|
|
update = 1;
|
120 |
|
|
#`P;
|
121 |
|
|
update = 0;
|
122 |
|
|
ready = 1;
|
123 |
|
|
for(j=0;j<`WIDTH_D0+1;j=j+1)
|
124 |
|
|
begin
|
125 |
|
|
i = dat[j];
|
126 |
|
|
#`P;
|
127 |
|
|
end
|
128 |
|
|
ready = 0;
|
129 |
|
|
w = 1; #`P; w = 0;
|
130 |
|
|
end
|
131 |
|
|
endtask
|
132 |
|
|
|
133 |
|
|
task read;
|
134 |
|
|
input [5:0] adr;
|
135 |
|
|
integer j;
|
136 |
|
|
begin
|
137 |
|
|
sel = 1;
|
138 |
|
|
w = 0;
|
139 |
|
|
addr = adr;
|
140 |
|
|
#`P;
|
141 |
|
|
update = 1;
|
142 |
|
|
#`P;
|
143 |
|
|
update = 0;
|
144 |
|
|
out = 0;
|
145 |
|
|
ready = 1;
|
146 |
|
|
for(j=0;j<`WIDTH_D0+1;j=j+1)
|
147 |
|
|
begin
|
148 |
|
|
out = {o, out[`WIDTH_D0:1]};
|
149 |
|
|
#`P;
|
150 |
|
|
end
|
151 |
|
|
end
|
152 |
|
|
endtask
|
153 |
|
|
|
154 |
|
|
task check;
|
155 |
|
|
input [`WIDTH_D0:0] wish;
|
156 |
|
|
begin
|
157 |
|
|
if (out !== wish)
|
158 |
|
|
begin $display("Error!"); $finish; end
|
159 |
|
|
end
|
160 |
|
|
endtask
|
161 |
|
|
endmodule
|
162 |
|
|
|