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This is the design of TinyCPU. It's goals are as follows:

1. 8-bit registers and operations (8 bit processor)

2. 16-bit address bus

3. fixed 16-bit instruction length

4. use a small amount of "rich" instructions to do powerful things

5. 1 instruction per clock cycle

Register list:

r0-r5 general purpose registers

sp stack pointer (represented as r6)

ip instruction pointer register (represented as r7)

cs, ds, es, ss segment registers (code segment, data segment, extra segment, stack segment)

tr truth register for conditionals

general opcode format

first byte:

first 4 bits: actual instruction

next 3 bits: (target) register

last 1 bit: conditional

second byte:

first 1 bit: second portion of condition (if not immediate) (1 for only if false)

next 1 bit: use extra segment

next 3 bits: other register

last 3 bits: extra opcode information or third register. such as for ADD it could be target=source+third_register

...or second byte is immediate value

For opcodes requiring 3 registers but without room, the target opcode is assume to be the second operation. Such as for AND, target=source AND target

short list of instructions: (not final, still planning)

immediates:

1. move reg, immediate

2. move [reg], immediate

3. push and move reg, immediate (or call immediate)

4. push immediate

5. jmp immediate

groups: (limited to 2 registers and no immediates. each group has 8 opcodes)

group 1:

move(store) [reg],reg

move(load) reg,[reg]

out reg1,reg2 (output to port reg1 value reg2)

in reg1,reg2 (input from port reg2 and store in reg1)

pop reg

push reg

move segmentreg,reg

move reg,segmentreg

group 2:

and reg1,reg2 (reg1=reg1 and reg2)

or reg, reg

xor reg,reg

not reg1,reg2 (reg1=not reg2)

left shift reg,reg

right shift reg,reg

rotate right reg,reg

rotate left reg,reg

group 3: compares

is greater than reg1,reg2 (TR=reg1>reg2)

is greater or equal to reg,reg

is less than reg,reg

is less than or equal to reg,reg

is equal to reg,reg

is not equal to reg,reg

equals 0 reg

not equals 0 reg

group 4:

push segmentreg

pop segmentreg

push and move reg, reg (or call reg)

exchange reg,reg

exchange reg,seg

clear TR

Set TR

group 5:

increment reg

decrement reg

far jmp reg1, reg2 (CS=reg1 and IP=reg2)

far call reg1,reg2

far jmp [reg] (first byte is CS, second byte is IP)

push extended segmentreg, reg (equivalent to push seg; push reg)

pop extended segmentreg, reg (equivalent to pop reg; pop seg)

reset processor (will completely reset the processor to starting state, but not RAM or anything else)

group 6:

set register bank 0

set register bank 1

push extended reg, reg

pop extended reg,reg

3 register instructions:

1. add reg1, reg2, reg3 (reg1=reg2+reg3)

2. sub reg1, reg2, reg3

opcodes used: 12 of 16. 4 more opcodes available. Decide what to do with the room later.

1 -move immediate (only uses first byte)

2 -move

3 -push

4 -push immediate

5 -push and move (or call when acting on ip)

6 -compare (is less than, is less than or equal, is greater than, is greater than or equal, is equal, is not equal) (6 conditions room for 2 more in extra)

7 -add

8 -subtract

9 -bitwise operations (xor, or, and, shift right, shift left, not)

x -multiply (if room)

x -divide

conditionals

1 -- only if true

for only if false, there should basically be another compare or if applicable an always afterwards

push

pop

move

add

sub

limitations that shouldn't be passed with instructions

* Doing 2 memory references

* pushing a memory reference (equates to 2 memory references)

Note it is possible however to read and write 16bits at one time to the memory to consecutive addresses.

segments:

DS is used in all "normal" memory references

SS is used in all push and pop instructions

ES is used when the ExtraSegment bit is set for either push/pop or normal memory references

CS is only used for fetching instructions

States needed:

0. reset

1. decode current instruction (All without memory capable within 1 clock cycle)

2. increment IP(and SP if needed) and fetch next instruction

3. Write 1 register to memory

4. Read 1 register from memory

5. Write 2 registers to memory

6. Read 2 registers from memory

7. Write 1 register to memory and setup increment of sp

8. Write 2 registers to memory and setup double increment of sp

9. Read 1 register from memory and setup decrement of sp

10. Read 2 registers from memory and setup double decrement of sp

11.

registerfile map:

0000: general r0

0001: general r1

0010: general r2

0011: general r3

0100: general r4

0101: general r5

0110: SP (r6)

0111: IP (r7)

1000: second bank r0

1001: second bank r1

1010: second bank r2

1011: second bank r3

1100: CS

1101: DS

1110: ES

1111: SS

Banking works like if(regnumber(2) = '0') then regnumber(3)=regbank; end if;

ALU operations

00000 and reg1,reg2 (reg1=reg1 and reg2)

00001 or reg, reg

00010 xor reg,reg

00011 not reg1,reg2 (reg1=not reg2)

00100 left shift reg,reg (logical)

00101 right shift reg,reg (logical)

00110 rotate right reg,reg

00111 rotate left reg,reg

01000 is greater than reg1,reg2 (TR=reg1>reg2)

01001 is greater or equal to reg,reg

01010 is less than reg,reg

01011 is less than or equal to reg,reg

01100 is equal to reg,reg

01101 is not equal to reg,reg

01110 equals 0 reg

01111 not equals 0 reg

10000 Set TR

10001 Reset TR

10011 Increment

10010 Decrement

10100 Add

10101 Subtract