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earlz |
--Core module.
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--This module is basically connects everything and decodes the opcodes.
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--The only thing above this is toplevel.vhd which actually sets the pinout for the FPGA
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.tinycpu.all;
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entity core is
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port(
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--memory interface
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MemAddr: out std_logic_vector(15 downto 0); --memory address (in bytes)
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MemWW: out std_logic; --memory writeword
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MemWE: out std_logic; --memory writeenable
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MemOut: in std_logic_vector(15 downto 0);
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MemIn: out std_logic_vector(15 downto 0);
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--general interface
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Clock: in std_logic;
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Reset: in std_logic; --When this is high, CPU will reset within 1 clock cycles.
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--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
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Hold: in std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
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HoldAck: out std_logic; --when high, CPU acknowledged hold and buses are in high Z
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--todo: port interface
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--debug ports:
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DebugIR: out std_logic_vector(15 downto 0); --current instruction
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DebugIP: out std_logic_vector(15 downto 0); --current IP
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DebugCS: out std_logic_vector(15 downto 0); --current code segment
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DebugTR: out std_logic; --current value of TR
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);
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end core;
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architecture Behavioral of core is
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component fetch is
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port(
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Enable: in std_logic;
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AddressIn: in std_logic_vector(15 downto 0);
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0); --interface from memory
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IROut: out std_logic_vector(15 downto 0);
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AddressOut: out std_logic_vector(15 downto 0) --interface to memory
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);
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end component;
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component alu is
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port(
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Op: in std_logic_vector(4 downto 0);
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DataIn1: in std_logic_vector(7 downto 0);
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DataIn2: in std_logic_vector(7 downto 0);
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DataOut: out std_logic_vector(7 downto 0);
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TR: out std_logic
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);
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end component;
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component carryover is
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port(
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EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
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DataIn: in std_logic_vector(7 downto 0);
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SegmentIn: in std_logic_vector(7 downto 0);
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Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
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DataOut: out std_logic_vector(7 downto 0);
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SegmentOut: out std_logic_vector(7 downto 0)
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);
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end component;
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component registerfile is
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port(
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WriteEnable: in regwritetype;
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DataIn: in regdatatype;
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Clock: in std_logic;
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DataOut: out regdatatype
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);
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end component;
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constant REGIP: integer := 7;
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constant REGSP: integer := 6;
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constant REGSS: integer := 15;
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constant REGES: integer := 14;
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constant REGDS: integer := 13;
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constant REGCS: integer := 12;
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type ProcessorState is (
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ResetProcessor,
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FirstFetch,
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Execute,
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WaitForMemory,
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HoldMemory
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);
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signal state: ProcessState;
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signal HeldState: ProcessState; --state the processor was in when HOLD was activated
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--carryout signals
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signal CarryCS: std_logic;
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signal CarrySS: std_logic;
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signal IPAddend: std_logic_vector(7 downto 0);
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signal SPAddend: std_logic_vector(7 downto 0);
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signal IPCarryOut: std_logic_vector(7 downto 0);
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signal CSCarryOut: std_logic_vector(7 downto 0);
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--register signals
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signal regWE:regwritetype;
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signal regIn: regdatatype;
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signal regOut: regdatatype;
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--fetch signals
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signal fetchEN: std_logic;
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signal IR: std_logic_vector(15 downto 0);
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--control signals
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signal InReset: std_logic;
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--opcode shortcut signals
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signal opmain: std_logic_vector(3 downto 0);
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signal opimmd: std_logic_vector(7 downto 0);
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signal opcond1: std_logic; --first conditional bit
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signal opcond2: std_logic; --second conditional bit
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signal opreg1: std_logic_vector(2 downto 0);
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signal opreg2: std_logic_vector(2 downto 0);
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signal opreg3: std_logic_vector(2 downto 0);
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signal opseges: std_logic; --use ES segment
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begin
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reg: port map registerfile(
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WriteEnable => regWE,
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DataIn => regIn,
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Clock => Clock,
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DataOut => regOut
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);
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carryovercs: port map carryover(
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EnableCarry => CarryCS,
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DataIn => regOut(REGIP);
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SegmentIn => regOut(REGCS);
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Addend => IPAddend;
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DataOut => IPCarryOut;
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SegmentOut => CSCarryOut;\
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);
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fetcher: port map fetch(
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Enable => fetchEN,
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AddressIn => regOut(REGCS) & regOut(REGIP),
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Clock => Clock,
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DataIn => MemIn,
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IROut => IR,
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AddressOut => MemAddr --this component supports tristate, so no worries about an intermediate signal
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);
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opmain <= IR(15 downto 12);
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opimmd <= IR(7 downto 0);
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opcond1 <= IR(8);
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opcond2 <= IR(7);
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opreg1 <= IR(11 downto 9);
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opreg3 <= IR(2 downto 0);
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opreg2 <= IR(5 downto 3);
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opseges <= IR(6);
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states: process()
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begin
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if rising_edge(Clock) then
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if reset='1' then
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InReset <= '1';
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state <= ResetProcessor;
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CarryCS <= '1';
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CarrySS <= '0';
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--finish up
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elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
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InReset <= '0';
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state <= FirstFetch;
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fetchEN <= '1';
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elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
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state <= HoldMemory;
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HoldAck <= '1';
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FetchEN <= '0';
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MemAddr <= "ZZZZZZZZZZZZZZZZ";
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MemIn <= "ZZZZZZZZZZZZZZZZ";
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elsif Hold='0' and state=HoldMemory then
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state <= ResetProcessor when reset='1' else Execute;
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FetchEN <= '1';
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elsif state=FirstFetch then --we have to let IR get loaded before we can execute.
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state <= Execute;
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end if;
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end if;
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end process;
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decode: process()
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begin
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if rising_edge(Clock) and Hold='0' then
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if state=Execute then
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--reset to "usual"
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RegIn(REGIP) <= IPCarryOut;
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RegIn(REGCS) <= CSCarryOut;
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RegWE <= (others => '0');
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--actual decoding
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case opmain is
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when "0000" => --mov reg,imm
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RegIn(to_integer(unsigned(opreg1))) <= opimmd;
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RegWE(to_integer(unsigned(opreg1))) <= '1';
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when others =>
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--synthesis off
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report "Not implemented" severity error;
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--synthesis on
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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