1 |
19 |
earlz |
--Core module.
|
2 |
|
|
--This module is basically connects everything and decodes the opcodes.
|
3 |
|
|
--The only thing above this is toplevel.vhd which actually sets the pinout for the FPGA
|
4 |
|
|
|
5 |
|
|
|
6 |
|
|
library IEEE;
|
7 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
8 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
9 |
|
|
use work.tinycpu.all;
|
10 |
|
|
|
11 |
|
|
entity core is
|
12 |
|
|
port(
|
13 |
|
|
--memory interface
|
14 |
|
|
MemAddr: out std_logic_vector(15 downto 0); --memory address (in bytes)
|
15 |
|
|
MemWW: out std_logic; --memory writeword
|
16 |
|
|
MemWE: out std_logic; --memory writeenable
|
17 |
20 |
earlz |
MemIn: in std_logic_vector(15 downto 0);
|
18 |
|
|
MemOut: out std_logic_vector(15 downto 0);
|
19 |
19 |
earlz |
--general interface
|
20 |
|
|
Clock: in std_logic;
|
21 |
|
|
Reset: in std_logic; --When this is high, CPU will reset within 1 clock cycles.
|
22 |
|
|
--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
|
23 |
|
|
Hold: in std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
|
24 |
|
|
HoldAck: out std_logic; --when high, CPU acknowledged hold and buses are in high Z
|
25 |
|
|
--todo: port interface
|
26 |
|
|
|
27 |
|
|
--debug ports:
|
28 |
|
|
DebugIR: out std_logic_vector(15 downto 0); --current instruction
|
29 |
20 |
earlz |
DebugIP: out std_logic_vector(7 downto 0); --current IP
|
30 |
|
|
DebugCS: out std_logic_vector(7 downto 0); --current code segment
|
31 |
19 |
earlz |
DebugTR: out std_logic; --current value of TR
|
32 |
20 |
earlz |
DebugR0: out std_logic_vector(7 downto 0)
|
33 |
19 |
earlz |
);
|
34 |
|
|
end core;
|
35 |
|
|
|
36 |
|
|
architecture Behavioral of core is
|
37 |
|
|
component fetch is
|
38 |
|
|
port(
|
39 |
|
|
Enable: in std_logic;
|
40 |
|
|
AddressIn: in std_logic_vector(15 downto 0);
|
41 |
|
|
Clock: in std_logic;
|
42 |
|
|
DataIn: in std_logic_vector(15 downto 0); --interface from memory
|
43 |
|
|
IROut: out std_logic_vector(15 downto 0);
|
44 |
|
|
AddressOut: out std_logic_vector(15 downto 0) --interface to memory
|
45 |
|
|
);
|
46 |
|
|
end component;
|
47 |
|
|
component alu is
|
48 |
|
|
port(
|
49 |
|
|
Op: in std_logic_vector(4 downto 0);
|
50 |
|
|
DataIn1: in std_logic_vector(7 downto 0);
|
51 |
|
|
DataIn2: in std_logic_vector(7 downto 0);
|
52 |
|
|
DataOut: out std_logic_vector(7 downto 0);
|
53 |
|
|
TR: out std_logic
|
54 |
|
|
);
|
55 |
|
|
end component;
|
56 |
|
|
component carryover is
|
57 |
|
|
port(
|
58 |
|
|
EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
|
59 |
|
|
DataIn: in std_logic_vector(7 downto 0);
|
60 |
|
|
SegmentIn: in std_logic_vector(7 downto 0);
|
61 |
|
|
Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
|
62 |
|
|
DataOut: out std_logic_vector(7 downto 0);
|
63 |
21 |
earlz |
SegmentOut: out std_logic_vector(7 downto 0);
|
64 |
|
|
Clock: in std_logic
|
65 |
19 |
earlz |
);
|
66 |
|
|
end component;
|
67 |
|
|
component registerfile is
|
68 |
|
|
port(
|
69 |
|
|
WriteEnable: in regwritetype;
|
70 |
|
|
DataIn: in regdatatype;
|
71 |
|
|
Clock: in std_logic;
|
72 |
|
|
DataOut: out regdatatype
|
73 |
|
|
);
|
74 |
|
|
end component;
|
75 |
|
|
|
76 |
|
|
constant REGIP: integer := 7;
|
77 |
|
|
constant REGSP: integer := 6;
|
78 |
|
|
constant REGSS: integer := 15;
|
79 |
|
|
constant REGES: integer := 14;
|
80 |
|
|
constant REGDS: integer := 13;
|
81 |
|
|
constant REGCS: integer := 12;
|
82 |
|
|
|
83 |
|
|
type ProcessorState is (
|
84 |
|
|
ResetProcessor,
|
85 |
21 |
earlz |
FirstFetch1, --the fetcher needs two clock cycles to catch up
|
86 |
|
|
FirstFetch2,
|
87 |
23 |
earlz |
Firstfetch3,
|
88 |
19 |
earlz |
Execute,
|
89 |
|
|
WaitForMemory,
|
90 |
|
|
HoldMemory
|
91 |
|
|
);
|
92 |
20 |
earlz |
signal state: ProcessorState;
|
93 |
|
|
signal HeldState: ProcessorState; --state the processor was in when HOLD was activated
|
94 |
19 |
earlz |
|
95 |
|
|
--carryout signals
|
96 |
|
|
signal CarryCS: std_logic;
|
97 |
|
|
signal CarrySS: std_logic;
|
98 |
|
|
signal IPAddend: std_logic_vector(7 downto 0);
|
99 |
|
|
signal SPAddend: std_logic_vector(7 downto 0);
|
100 |
|
|
signal IPCarryOut: std_logic_vector(7 downto 0);
|
101 |
|
|
signal CSCarryOut: std_logic_vector(7 downto 0);
|
102 |
25 |
earlz |
signal SPCarryOut: std_logic_vector(7 downto 0);
|
103 |
|
|
signal SSCarryOut: std_logic_vector(7 downto 0);
|
104 |
|
|
|
105 |
19 |
earlz |
--register signals
|
106 |
|
|
signal regWE:regwritetype;
|
107 |
|
|
signal regIn: regdatatype;
|
108 |
|
|
signal regOut: regdatatype;
|
109 |
|
|
--fetch signals
|
110 |
|
|
signal fetchEN: std_logic;
|
111 |
|
|
signal IR: std_logic_vector(15 downto 0);
|
112 |
25 |
earlz |
--alu signals
|
113 |
|
|
signal AluOp: std_logic_vector(4 downto 0);
|
114 |
|
|
signal AluIn1: std_logic_vector(7 downto 0);
|
115 |
|
|
signal AluIn2: std_logic_vector(7 downto 0);
|
116 |
|
|
signal AluOut: std_logic_vector(7 downto 0);
|
117 |
|
|
signal TR: std_logic;
|
118 |
19 |
earlz |
|
119 |
|
|
--control signals
|
120 |
|
|
signal InReset: std_logic;
|
121 |
25 |
earlz |
signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
|
122 |
|
|
signal OpData: std_logic_vector(15 downto 0); --data to write or will load to here
|
123 |
|
|
signal OpWW: std_logic;
|
124 |
|
|
signal OpWE: std_logic;
|
125 |
19 |
earlz |
|
126 |
|
|
--opcode shortcut signals
|
127 |
|
|
signal opmain: std_logic_vector(3 downto 0);
|
128 |
|
|
signal opimmd: std_logic_vector(7 downto 0);
|
129 |
|
|
signal opcond1: std_logic; --first conditional bit
|
130 |
|
|
signal opcond2: std_logic; --second conditional bit
|
131 |
|
|
signal opreg1: std_logic_vector(2 downto 0);
|
132 |
|
|
signal opreg2: std_logic_vector(2 downto 0);
|
133 |
|
|
signal opreg3: std_logic_vector(2 downto 0);
|
134 |
|
|
signal opseges: std_logic; --use ES segment
|
135 |
25 |
earlz |
|
136 |
|
|
signal regbank: std_logic;
|
137 |
19 |
earlz |
|
138 |
20 |
earlz |
signal fetcheraddress: std_logic_vector(15 downto 0);
|
139 |
25 |
earlz |
|
140 |
27 |
earlz |
|
141 |
|
|
signal bankreg1: std_logic_vector(3 downto 0); --these signals have register bank stuff baked in
|
142 |
|
|
signal bankreg2: std_logic_vector(3 downto 0);
|
143 |
|
|
signal bankreg3: std_logic_vector(3 downto 0);
|
144 |
25 |
earlz |
signal FetchMemAddr: std_logic_vector(15 downto 0);
|
145 |
|
|
|
146 |
29 |
earlz |
signal UsuallySS: std_logic_vector(3 downto 0);
|
147 |
|
|
signal UsuallyDS: std_logic_vector(3 downto 0);
|
148 |
19 |
earlz |
begin
|
149 |
20 |
earlz |
reg: registerfile port map(
|
150 |
19 |
earlz |
WriteEnable => regWE,
|
151 |
|
|
DataIn => regIn,
|
152 |
|
|
Clock => Clock,
|
153 |
|
|
DataOut => regOut
|
154 |
|
|
);
|
155 |
20 |
earlz |
carryovercs: carryover port map(
|
156 |
19 |
earlz |
EnableCarry => CarryCS,
|
157 |
28 |
earlz |
DataIn => regOut(REGIP),
|
158 |
|
|
SegmentIn => regOut(REGCS),
|
159 |
20 |
earlz |
Addend => IPAddend,
|
160 |
|
|
DataOut => IPCarryOut,
|
161 |
21 |
earlz |
SegmentOut => CSCarryOut,
|
162 |
|
|
Clock => Clock
|
163 |
19 |
earlz |
);
|
164 |
25 |
earlz |
carryoverss: carryover port map(
|
165 |
|
|
EnableCarry => CarrySS,
|
166 |
28 |
earlz |
DataIn => regOut(REGSP),
|
167 |
|
|
SegmentIn => RegOut(REGSS),
|
168 |
25 |
earlz |
Addend => SPAddend,
|
169 |
|
|
DataOut => SPCarryOut,
|
170 |
|
|
SegmentOut => SSCarryOut,
|
171 |
|
|
Clock => Clock
|
172 |
|
|
);
|
173 |
20 |
earlz |
fetcher: fetch port map(
|
174 |
19 |
earlz |
Enable => fetchEN,
|
175 |
20 |
earlz |
AddressIn => fetcheraddress,
|
176 |
19 |
earlz |
Clock => Clock,
|
177 |
|
|
DataIn => MemIn,
|
178 |
|
|
IROut => IR,
|
179 |
25 |
earlz |
AddressOut => FetchMemAddr
|
180 |
19 |
earlz |
);
|
181 |
25 |
earlz |
cpualu: alu port map(
|
182 |
|
|
Op => AluOp,
|
183 |
|
|
DataIn1 => AluIn1,
|
184 |
|
|
DataIn2 => AluIn2,
|
185 |
|
|
DataOut => AluOut,
|
186 |
|
|
TR => TR
|
187 |
|
|
);
|
188 |
21 |
earlz |
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
|
189 |
25 |
earlz |
MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
|
190 |
28 |
earlz |
MemOut <= OpData when (state=WaitForMemory and OpWE='1') else "ZZZZZZZZZZZZZZZZ" when state=HoldMemory else x"0000";
|
191 |
|
|
MemWE <= OpWE when state=WaitForMemory else 'Z' when state=HoldMemory else '0';
|
192 |
|
|
MemWW <= OpWW when state=WaitForMemory else 'Z' when state=HoldMEmory else '0';
|
193 |
25 |
earlz |
OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
|
194 |
20 |
earlz |
--opcode shortcuts
|
195 |
19 |
earlz |
opmain <= IR(15 downto 12);
|
196 |
|
|
opimmd <= IR(7 downto 0);
|
197 |
|
|
opcond1 <= IR(8);
|
198 |
|
|
opcond2 <= IR(7);
|
199 |
|
|
opreg1 <= IR(11 downto 9);
|
200 |
|
|
opreg3 <= IR(2 downto 0);
|
201 |
27 |
earlz |
opreg2 <= IR(6 downto 4);
|
202 |
|
|
opseges <= IR(3);
|
203 |
20 |
earlz |
--debug ports
|
204 |
|
|
DebugCS <= regOut(REGCS);
|
205 |
|
|
DebugIP <= regOut(REGIP);
|
206 |
|
|
DebugR0 <= regOut(0);
|
207 |
|
|
DebugIR <= IR;
|
208 |
25 |
earlz |
DebugTR <= TR;
|
209 |
|
|
--register addresses with registerbank baked in
|
210 |
27 |
earlz |
bankreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
|
211 |
|
|
bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
|
212 |
|
|
bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
|
213 |
29 |
earlz |
--UsuallySegment shortcuts (only used when not an immediate
|
214 |
|
|
UsuallyDS <= "1101" when opseges='0' else "1110";
|
215 |
|
|
UsuallySS <= "1111" when opseges='0' else "1110";
|
216 |
19 |
earlz |
|
217 |
21 |
earlz |
|
218 |
29 |
earlz |
foo: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
|
219 |
19 |
earlz |
begin
|
220 |
|
|
if rising_edge(Clock) then
|
221 |
21 |
earlz |
|
222 |
|
|
--states
|
223 |
20 |
earlz |
if reset='1' and hold='0' then
|
224 |
19 |
earlz |
InReset <= '1';
|
225 |
|
|
state <= ResetProcessor;
|
226 |
20 |
earlz |
HoldAck <= '0';
|
227 |
21 |
earlz |
CarryCS <= '1';
|
228 |
|
|
CarrySS <= '0';
|
229 |
|
|
regWE <= (others => '1');
|
230 |
|
|
regIn <= (others => "00000000");
|
231 |
|
|
regIn(REGCS) <= x"01";
|
232 |
|
|
IPAddend <= x"00";
|
233 |
25 |
earlz |
SPAddend <= x"00";
|
234 |
|
|
AluOp <= "10001"; --reset TR in ALU
|
235 |
|
|
regbank <= '0';
|
236 |
21 |
earlz |
fetchEN <= '1';
|
237 |
25 |
earlz |
OpData <= "ZZZZZZZZZZZZZZZZ";
|
238 |
|
|
OpAddress <= x"0000";
|
239 |
|
|
OpWE <= '0';
|
240 |
|
|
opWW <= '0';
|
241 |
19 |
earlz |
--finish up
|
242 |
|
|
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
|
243 |
|
|
InReset <= '0';
|
244 |
21 |
earlz |
fetchEN <= '1';
|
245 |
|
|
state <= FirstFetch1;
|
246 |
19 |
earlz |
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
247 |
20 |
earlz |
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
248 |
19 |
earlz |
state <= HoldMemory;
|
249 |
|
|
HoldAck <= '1';
|
250 |
21 |
earlz |
FetchEN <= '0';
|
251 |
19 |
earlz |
elsif Hold='0' and state=HoldMemory then
|
252 |
20 |
earlz |
if reset='1' or InReset='1' then
|
253 |
|
|
state <= ResetProcessor;
|
254 |
|
|
else
|
255 |
|
|
state <= Execute;
|
256 |
|
|
end if;
|
257 |
21 |
earlz |
FetchEN <= '1';
|
258 |
|
|
elsif state=FirstFetch1 then --we have to let IR get loaded before we can execute.
|
259 |
20 |
earlz |
--regWE <= (others => '0');
|
260 |
21 |
earlz |
fetchEN <= '1'; --already enabled, but anyway
|
261 |
23 |
earlz |
--regWE <= (others => '0');
|
262 |
21 |
earlz |
IPAddend <= x"02";
|
263 |
|
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
264 |
|
|
RegWE <= (others => '0');
|
265 |
|
|
regIn(REGIP) <= IPCarryOut;
|
266 |
|
|
regWE(REGIP) <= '1';
|
267 |
|
|
regWE(REGCS) <= '1';
|
268 |
|
|
regIn(REGCS) <= CSCarryOut;
|
269 |
23 |
earlz |
state <= Execute;
|
270 |
|
|
elsif state=FirstFetch2 then
|
271 |
|
|
state <= FirstFetch3;
|
272 |
|
|
|
273 |
|
|
elsif state=FirstFetch3 then
|
274 |
|
|
state <= Execute;
|
275 |
25 |
earlz |
elsif state=WaitForMemory then
|
276 |
|
|
state <= Execute;
|
277 |
|
|
FetchEn <= '1';
|
278 |
|
|
IpAddend <= x"02";
|
279 |
29 |
earlz |
SpAddend <= x"00";
|
280 |
19 |
earlz |
end if;
|
281 |
21 |
earlz |
|
282 |
|
|
|
283 |
19 |
earlz |
if state=Execute then
|
284 |
20 |
earlz |
fetchEN <= '1';
|
285 |
19 |
earlz |
--reset to "usual"
|
286 |
20 |
earlz |
IPAddend <= x"02";
|
287 |
|
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
288 |
19 |
earlz |
RegWE <= (others => '0');
|
289 |
21 |
earlz |
regIn(REGIP) <= IPCarryOut;
|
290 |
|
|
regWE(REGIP) <= '1';
|
291 |
|
|
regWE(REGCS) <= '1';
|
292 |
|
|
regIn(REGCS) <= CSCarryOut;
|
293 |
25 |
earlz |
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
|
294 |
|
|
regIn(REGSS) <= SSCarryOut;
|
295 |
|
|
regWE(REGSP) <= '1';
|
296 |
|
|
regWE(REGSS) <= '1';
|
297 |
|
|
OpAddress <= "ZZZZZZZZZZZZZZZZ";
|
298 |
21 |
earlz |
|
299 |
19 |
earlz |
--actual decoding
|
300 |
25 |
earlz |
if opcond1='0' or (opcond1='1' and TR='1') then
|
301 |
|
|
case opmain is
|
302 |
|
|
when "0000" => --mov reg,imm
|
303 |
27 |
earlz |
regIn(to_integer(unsigned(bankreg1))) <= opimmd;
|
304 |
|
|
regWE(to_integer(unsigned(bankreg1))) <= '1';
|
305 |
25 |
earlz |
when "0001" => --mov [reg],imm
|
306 |
27 |
earlz |
OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(bankreg1)));
|
307 |
25 |
earlz |
OpWE <= '1';
|
308 |
|
|
OpData <= x"00" & opimmd;
|
309 |
|
|
OpWW <= '0';
|
310 |
|
|
state <= WaitForMemory;
|
311 |
|
|
IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
|
312 |
|
|
FetchEN <= '0';
|
313 |
27 |
earlz |
when "0011" => --group 3 comparisons
|
314 |
|
|
AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
|
315 |
29 |
earlz |
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
|
316 |
|
|
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
|
317 |
27 |
earlz |
when "0100" => --group 4 bitwise operations
|
318 |
|
|
AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
|
319 |
29 |
earlz |
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
|
320 |
|
|
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
|
321 |
|
|
regIn(to_integer(unsigned(bankreg1))) <= AluOut;
|
322 |
|
|
regWE(to_integer(unsigned(bankreg1))) <= '1';
|
323 |
|
|
when "0101" => --group 5
|
324 |
|
|
case opreg3 is
|
325 |
|
|
when "000" => --subgroup 5-0
|
326 |
|
|
case opreg2 is
|
327 |
|
|
when "000" => --push reg
|
328 |
|
|
SpAddend <= x"02"; --set SP to increment
|
329 |
|
|
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
|
330 |
|
|
OpWE <= '1';
|
331 |
|
|
OpData <= x"00" & regOut(to_integer(unsigned(bankreg1)));
|
332 |
|
|
OpWW <= '1';
|
333 |
|
|
state <= WaitForMemory;
|
334 |
|
|
IPAddend <= x"00";
|
335 |
|
|
FetchEN <= '0';
|
336 |
|
|
when "001" => --pop reg
|
337 |
|
|
SPAddend <= x"FE"; --set SP to decrement
|
338 |
|
|
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
|
339 |
|
|
OpWE <= '0';
|
340 |
|
|
regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0);
|
341 |
|
|
OpWW <= '0';
|
342 |
|
|
state <= WaitForMemory;
|
343 |
|
|
IPAddend <= x"00";
|
344 |
|
|
FetchEN <= '0';
|
345 |
|
|
when others =>
|
346 |
|
|
--synthesis off
|
347 |
|
|
report "Not implemented subgroup 5-0" severity error;
|
348 |
|
|
--synthesis on
|
349 |
|
|
end case;
|
350 |
|
|
when others =>
|
351 |
|
|
--synthesis off
|
352 |
|
|
report "Not implemented group 5" severity error;
|
353 |
|
|
--synthesis on
|
354 |
|
|
end case;
|
355 |
25 |
earlz |
when others =>
|
356 |
|
|
--synthesis off
|
357 |
|
|
report "Not implemented" severity error;
|
358 |
|
|
--synthesis on
|
359 |
|
|
end case;
|
360 |
|
|
end if;
|
361 |
19 |
earlz |
end if;
|
362 |
21 |
earlz |
|
363 |
29 |
earlz |
end if;
|
364 |
21 |
earlz |
|
365 |
|
|
|
366 |
29 |
earlz |
|
367 |
19 |
earlz |
end process;
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
end Behavioral;
|