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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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use work.tinycpu.all;
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ENTITY core_tb IS
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END core_tb;
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ARCHITECTURE behavior OF core_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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component core is
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port(
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--memory interface
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MemAddr: out std_logic_vector(15 downto 0); --memory address (in bytes)
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MemWW: out std_logic; --memory writeword
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MemWE: out std_logic; --memory writeenable
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MemIn: in std_logic_vector(15 downto 0);
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MemOut: out std_logic_vector(15 downto 0);
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--general interface
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Clock: in std_logic;
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Reset: in std_logic; --When this is high, CPU will reset within 1 clock cycles.
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--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
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Hold: in std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
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HoldAck: out std_logic; --when high, CPU acknowledged hold and buses are in high Z
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--todo: port interface
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--debug ports:
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DebugIR: out std_logic_vector(15 downto 0); --current instruction
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DebugIP: out std_logic_vector(7 downto 0); --current IP
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DebugCS: out std_logic_vector(7 downto 0); --current code segment
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DebugTR: out std_logic; --current value of TR
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DebugR0: out std_logic_vector(7 downto 0)
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);
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end component;
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--memory interface
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signal MemAddr: std_logic_vector(15 downto 0); --memory address (in bytes)
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signal MemWW: std_logic; --memory writeword
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signal MemWE: std_logic; --memory writeenable
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signal MemOut: std_logic_vector(15 downto 0);
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signal MemIn: std_logic_vector(15 downto 0):=x"0000";
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--general interface
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signal Reset: std_logic:='0'; --When this is high, CPU will reset within 1 clock cycles.
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--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
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signal Hold: std_logic:='0'; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
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signal HoldAck: std_logic; --when high, CPU acknowledged hold and buses are in high Z
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--todo: port interface
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--debug ports:
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signal DebugIR: std_logic_vector(15 downto 0); --current instruction
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signal DebugIP: std_logic_vector(7 downto 0); --current IP
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signal DebugCS: std_logic_vector(7 downto 0); --current code segment
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signal DebugTR: std_logic; --current value of TR
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signal DebugR0: std_logic_vector(7 downto 0);
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: core PORT MAP (
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MemAddr => MemAddr,
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MemWW => MemWW,
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MemWE => MemWE,
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MemOut => MemOut,
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MemIn => MemIn,
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--general interface
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Clock => Clock,
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Reset => Reset,
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--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
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Hold => Hold,
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HoldAck => HoldAck,
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DebugIR => DebugIR,
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DebugIP => DebugIP,
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DebugCS => DebugCS,
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DebugTR => DebugTR,
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DebugR0 => DebugR0
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);
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-- Clock process definitions
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clock_process :process
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begin
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Clock <= '0';
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wait for clock_period/2;
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Clock <= '1';
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wait for clock_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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variable err_cnt: integer :=0;
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begin
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Reset <= '1';
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wait for 20 ns;
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--state tests:
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Hold <= '1';
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wait for 10 ns;
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assert(HoldAck = '1') report "hold state is not acknowledged" severity error;
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--assert(MemAddr = "ZZZZZZZZZZZZZZZZ" and MemWW="Z" and MemWE="Z" and MemOut = "ZZZZZZZZZZZZZZZZZZZZ")
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-- report "hold state does not set high-Z" severity error;
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Hold <= '0';
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wait for 10 ns;
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assert(HoldAck = '0') report "hold state lasts longer than it should" severity error;
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Reset <= '0';
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MemIn <= x"0012"; --mov r0, 0xFF
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wait for 20 ns; --fetcher needs two clock cycles to catch up
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assert(MemAddr = x"0100") report "Not fetching from correct start address" severity error;
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MemIn <= x"00F1"; --mov r0, 0xF1
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wait for 10 ns;
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assert(MemAddr = x"0102") report "fetcher is not incrementing address" severity error;
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assert(DebugIR = x"00F1" and DebugR0 /= x"12") report "IR is not correct. Execution occurs during first fetch";
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MemIn <= x"0056";
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wait for 10 ns;
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assert(DebugR0 = x"56") report "loaded value of R0 is not correct" severity error;
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MemIn <= x"0E50"; --mov IP, 0x50
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wait for 10 ns;
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assert( MemAddr = x"0150") report "mov to IP doesn't work" severity error; --DebugIP uses regOut, so it won't be updated until next clock cycle actually, but it's correct.
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MemIn <= x"0020"; --mov r0, 0x20
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wait for 10 ns;
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assert (MemAddr = x"0152" and DebugIP=x"52") report "fetching is wrong after move to IP" severity error; --DebugIP uses regOut, Fetchaddress uses regIn, so this is correct
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MemIn <= x"0160"; --mov r0,0x60 if TR is set
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wait for 10 ns; --wait until register write happens
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assert(DebugR0 = x"20") report "mov to r0 is wrong after move to IP" severity error;
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MemIn <= x"1050"; --mov [r0], 0x50 (r0 is 0x20)
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wait for 10 ns;
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MemIn <= x"0025"; --mov r0,0x25
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assert(DebugR0 = x"20" and DebugTR='0') report "moved to r0 conditional thought TR is 0" severity error;
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assert(MemAddr = x"0020" and MemWE='1' and MemWW='0' and MemOut=x"0050") report "Write to memory doesn't work" severity error;
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wait for 20 ns; --wait an extra cycle because of WaitForMemory state
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MemIn <= x"0235"; --mov r1,0x35
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wait for 10 ns;
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MemIn <= "0011000000010000"; --compare greater than r0, r1 : TR=r0 > r1
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wait for 10 ns;
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assert(DebugTR ='0') report "ALU compare is not correct for greater than" severity error;
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MemIn <= "0011000000010010"; --TR=r0 < r1
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wait for 10 ns;
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MemIn <= x"0F20"; --jmp to 0x20 if TR=1
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assert(DebugTR='1') report "ALU compare is not correct for less than" severity error;
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wait for 10 ns;
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assert(DebugIP=x"20") report "conditional TR is not correct after ALU compare" severity error;
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--now test bitwise
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MemIn <= x"0E50"; --mov IP, 0x50 -- do this just so we can count IP easily
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wait for 10 ns;
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MemIn <= x"00F0"; --mov r0, 0xFO
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wait for 10 ns;
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MemIn <= x"0218"; --mov r1, 0x18
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wait for 10 ns;
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MemIn <= "0100000000010001"; --or r0, r1 (r0 = r0 or r1)
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wait for 10 ns;
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wait for 10 ns; --wait for settling
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assert(DebugR0 = x"F8") report "ALU OR is not correct" severity error;
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assert( MemAddr=x"0156") report "Fetching is wrong after WaitForAlu" severity error;
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MemIn <= x"0070"; --mov r0, 0x70 -- for debugging
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wait for 10 ns;
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assert( MemAddr=x"0158") report "IP increment is wrong after WaitForAlu" severity error;
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MemIn <= "0101000000000000"; --push r0
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wait for 10 ns;
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assert(MemAddr=x"0200" and MemOut=x"0070") report "push is not correct" severity error;
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wait for 10 ns;
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MemIn <= "0101000001100001"; --mov r0, SP
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wait for 10 ns;
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assert(Debugr0 = x"02") report "SP is not correct" severity error;
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MemIn <= "0101000000010000"; --pop r0
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assert(MemAddr=x"015C") report "IP increment is wrong after push" severity error;
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wait for 10 ns;
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MemIn <= x"0020"; --the value to be popped into r0
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assert(MemAddr=x"0200") report "Pop is not fetching from correct address" severity error;
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wait for 10 ns;
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assert(DebugR0=x"20") report "Pop is not assigning to R0 correct" severity error;
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MemIn <= x"0040"; --mov r0, 0x40
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wait for 10 ns;
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MemIn <= b"0101_0010_0000_0001"; --mov r1,r0
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wait for 10 ns;
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MemIn <= b"0101_0000_0001_0010"; --mov r0, [r1]
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wait for 10 ns;
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assert(MemAddr=x"0040") report "load operation doesn't fetch from proper address" severity error;
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MemIn <= x"1234"; --value to be loaded to r0 (lower value only)
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wait for 10 ns;
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assert(DebugR0=x"34") report "load operation doesn't load into r0 properly" severity error;
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MemIn <= b"0101_0000_0001_0011"; --mov [r0], r1
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wait for 10 ns;
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assert(MemAddr=x"0034") report "store operation doesn't store to proper address" severity error;
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assert(MemOut=x"0040") report "store operation doesn't have proper value" severity error;
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wait for 10 ns;
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MemIn <= x"0010";
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-- summary of testbench
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assert false
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report "Testbench of core completed successfully!"
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severity note;
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wait;
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-- insert stimulus here
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wait;
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end process;
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END;
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