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[/] [tinyvliw8/] [trunk/] [design/] [AlteraDK1/] [AlteraDK1.vhd] - Blame information for rev 9

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
library altera;
use altera.altera_syn_attributes.all;
 
entity alteraDK1 is
        port (
                clock   : in    std_logic;
 
                -- 7-Segments-LEDs
                hex0    : out   std_logic_vector(6 downto 0);
                hex1    : out   std_logic_vector(6 downto 0);
                hex2    : out   std_logic_vector(6 downto 0);
                hex3    : out   std_logic_vector(6 downto 0);
 
                -- GPIO
                jp1     : inout std_logic_vector(0 to 35);
                jp2     : inout std_logic_vector(0 to 35);
 
                -- UART
                uart0_rxd : in std_logic;
                uart0_txd : out std_logic;
 
                -- keys
                key       : in  std_logic_vector(3 downto 0);
                -- switches
                sw        : in  std_logic_vector(9 downto 0);
 
                -- LEDs
                led_red   : out std_logic_vector(9 downto 0);
                led_green : out std_logic_vector(7 downto 0)
        );
end alteraDK1;
 
architecture rtl of AlteraDK1 is
 
component instMem IS
        PORT (
                address         : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
                data                    : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                inclock         : IN STD_LOGIC  := '1';
                outclock                : IN STD_LOGIC ;
                wren                    : IN STD_LOGIC ;
                q                               : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
        );
END component;
 
component dataMem IS
        PORT (
                address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                inclock : IN STD_LOGIC  := '1';
                outclock        : IN STD_LOGIC ;
                wren            : IN STD_LOGIC ;
                q                       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
END component;
 
component vliwProc
        port (
                clk           : in  std_logic;
 
                instMemAddr   : out std_logic_vector(10 downto 0);
                instMemDataIn : in  std_logic_vector(31 downto 0);
                instMemEn_n   : out std_logic;
 
                ioMemAddr    : out std_logic_vector(7 downto 0);
                ioMemDataOut : out std_logic_vector(7 downto 0);
                ioMemDataIn  : in  std_logic_vector(7 downto 0);
                ioMemWr_n    : out std_logic;
                ioMemEn_n    : out std_logic;
 
                -- IO bus
                dataMemAddr    : out std_logic_vector(7 downto 0);
                dataMemDataOut : out std_logic_vector(7 downto 0);
                dataMemDataIn  : in  std_logic_vector(7 downto 0);
                dataMemWr_n    : out std_logic;
                dataMemEn_n    : out std_logic;
 
                irqLine        : in  std_logic_vector(4 downto 0);
                irqLineAck     : out std_logic_vector(4 downto 0);
 
                stall_n      : in std_logic;
                stalled_n    : out std_logic;
 
                rst_n        : in std_logic
        );
end component;
 
component spiSlave
        PORT (
                sclk      : IN  STD_LOGIC;
                cs        : IN  STD_LOGIC;
                mosi      : IN  STD_LOGIC;
                miso      : OUT STD_LOGIC;
                addr      : OUT std_logic_vector(10 downto 0);
                memSel    : out std_logic_vector(1 downto 0);
                writeEn_n : OUT STD_LOGIC;
                readEn_n  : OUT STD_LOGIC;
 
                dataOut  : OUT std_logic_vector(31 downto 0);
                dataIn    : IN std_logic_vector(31 downto 0);
 
                rst_n     : IN  STD_LOGIC
        );
end component;
 
component ioport
        port (
                cs_n     : IN  STD_LOGIC;                                   -- chip select signal
 
                        clk      : IN  STD_LOGIC;
 
                        -- memory interface
                mdbwr_n  : IN  STD_LOGIC;                    -- write enable signal    
                mdb_i           : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
                mdb_o           : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus    
                mab     : IN  STD_LOGIC_VECTOR(2 downto 0);      -- address registers 
 
                        -- interrupt interface
                        irq      : out std_logic;
                        irqAck   : in std_logic;
 
                -- port interface
                PnIN    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
                PnOUT           : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
                PnOEN   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
 
                -- MODxIN   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);         -- data to peripheral
                -- MODxDIR  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);         -- direction
                -- MODxOUT  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);         -- data from peripheral 
 
                rst_n           : IN STD_LOGIC
                );
end component;
 
component timer
        PORT (
                clk       : in std_logic;
 
                addr      : in std_logic_vector(2 downto 0);        -- register address
 
                writeEn_n : in  STD_LOGIC;                           -- write enable, low active
                readEn_n  : in  STD_LOGIC;                      -- read enable, low active
 
                dataOut   : OUT std_logic_vector(7 downto 0);    -- data bus for writing register
                dataIn    : IN std_logic_vector(7 downto 0);    -- data bus for reading register
 
                irq       : out std_logic;
                irq_ack   : in  std_logic;
 
                rst_n     : IN  STD_LOGIC                        -- asynchr. reset, low active
        );
end component;
 
component gendelay
        generic (n: integer := 1);
        port (
                a_in    : in    std_logic;
                a_out   : out   std_logic
        );
end component;
 
        signal mclk_s   : std_logic;                          -- main clock
 
        -- mdu interface
        signal mduClk_s     : std_logic;
        signal mduDataOut_s : std_logic_vector(31 downto 0);
        signal mduEn_n_s : std_logic;
        signal mduIoDataOut_s : std_logic_vector(7 downto 0);
 
        -- instruction memory interface
        signal instMemAddr_s   : std_logic_vector(10 downto 0);
        signal instMemDataIn_s : std_logic_vector(31 downto 0);
        signal instMemInClk_s  : std_logic;
        signal instMemOutClk_s : std_logic;
        signal instMemWrEn_s   : std_logic;
 
        signal instRdEn_n_s    : std_logic;
        signal instRdEnDly_n_s : std_logic;
        signal instWrEn_n_s    : std_logic;
 
        signal instAddr_s    : std_logic_vector(10 downto 0);
        signal instDataOut_s : std_logic_vector(31 downto 0);
        signal instEn_n_s    : std_logic;
 
        -- IO bus
        signal ioAddr_s    : std_logic_vector(7 downto 0);
        signal ioDataOut_s : std_logic_vector(7 downto 0);
        signal ioDataIn_s  : std_logic_vector(7 downto 0);
        signal ioEn_n_s    : std_logic;
        signal ioWr_n_s    : std_logic;
 
        -- GPIO signals
        signal ioDataGpio_s : std_logic_vector(7 downto 0);
        signal ioPortEn_n_s : std_logic;
        signal ioPortIrq_s  : std_logic;
 
        -- Data bus
        signal procDataAddr_s : std_logic_vector(7 downto 0);
        signal procDataOut_s  : std_logic_vector(7 downto 0);
        signal procDataIn_s   : std_logic_vector(7 downto 0);
        signal procDataWr_n_s : std_logic;
        signal procDataEn_n_s : std_logic;
 
        signal dataMemAddr_s   : std_logic_vector(7 downto 0);
        signal dataMemIn_s     : std_logic_vector(7 downto 0);
        signal dataWrEn_s      : std_logic;
        signal dataRdEnDly_n_s : std_logic;
        signal dataMemInClk_s  : std_logic;
        signal dataMemOutClk_s : std_logic;
        signal dataRdEn_n_s    : std_logic;
        signal dataWrEn_n_s    : std_logic;
 
        signal rst_n_s     : std_logic;
 
        signal stall_n_s   : std_logic;
        signal stalled_n_s : std_logic;
 
        signal irqLine_s      : std_logic_vector(4 downto 0);
        signal irqLineAck_s   : std_logic_vector(4 downto 0);
 
        -- timer signals 
        signal timer_irq_s      : std_logic;
        signal ioTimerEn_n_s    : std_logic;
        signal ioTimerDataOut_s : std_logic_vector(7 downto 0);
 
        -- spi slave
        signal spiCsIn_s    : std_logic;
        signal sclk_s       : std_logic;
        signal cs_s         : std_logic;
        signal mosi_s       : std_logic;
        signal miso_s       : std_logic;
        signal spiAddr_s    : std_logic_vector(10 downto 0);
        signal spiMemSel_s  : std_logic_vector(1 downto 0);
        signal spiWrEn_n_s  : std_logic;
        signal spiRdEn_n_s  : std_logic;
        signal spiDataOut_s : std_logic_vector(31 downto 0);
        signal spiDataIn_s  : std_logic_vector(31 downto 0);
 
        signal gpio_in_s  : std_logic_vector(7 downto 0);
        signal gpio_out_s : std_logic_vector(7 downto 0);
        signal gpio_dir_s : std_logic_vector(7 downto 0);
 
begin
 
        gpio_gen: for i in 7 downto 0 generate
        begin
                jp2(i) <= gpio_out_s(i) when gpio_dir_s(i) = '1' else
                          'Z';
                gpio_in_s(i) <= jp2(i);
        end generate;
 
        rst_sync: process (clock)
        begin
                if clock'event and clock = '1' then
                        rst_n_s <= key(0);
                end if;
        end process;
 
        mclk_s <= clock;
 
        irqLine_s <= ioPortIrq_s & timer_irq_s & "000";
 
 
        -- instruction memory
        ---------------------
 
        instMemOut_delay_i: gendelay
                generic map (n => 2)
                port map (
                        a_in    => instRdEn_n_s,
                        a_out   => instRdEnDly_n_s
                );
 
        instMem_i : instMem
        port map (
                address  => instMemAddr_s,
                data     => instMemDataIn_s,
                inclock  => instMemInClk_s,
                outclock => instMemOutClk_s,
                wren     => instMemWrEn_s,
                q        => instDataOut_s
        );
 
        instMemAddr_s <= spiAddr_s when cs_s = '0' and spiMemSel_s = "00" else
                         instAddr_s;
 
        instMemDataIn_s <= spiDataOut_s;
        instMemWrEn_s   <= not(instWrEn_n_s);
 
        instMemInClk_s  <= not(instRdEn_n_s) and not(instRdEnDly_n_s xor instWrEn_n_s);
        instMemOutClk_s <= not(instMemInClk_s);
 
        instRdEn_n_s <= '0' when (cs_s = '0' and spiRdEn_n_s = '0' and spiMemSel_s = "00") or
                                 (cs_s = '1' and instEn_n_s = '0') else
                                            '1';
        instWrEn_n_s <= '0' when (cs_s = '0' and spiWrEn_n_s = '0' and spiMemSel_s = "00") else
                        '1';
 
        -- data memory
        --------------------------
        dataMem_i : dataMem
        port map (
                address  => dataMemAddr_s,
                data     => dataMemIn_s,
                inclock  => dataMemInClk_s,
                outclock => dataMemOutClk_s,
                wren     => dataWrEn_s,
                q        => procDataOut_s
        );
 
        dataMemAddr_s <= spiAddr_s(7 downto 0) when cs_s = '0' and spiMemSel_s = "01" else
                         procDataAddr_s;
 
        dataMemIn_s   <= spiDataOut_s(7 downto 0) when cs_s = '0' and spiMemSel_s = "01" else
                         procDataIn_s;
        dataWrEn_s    <= not(dataWrEn_n_s);
 
        dataMemOutClk_delay_i: gendelay
                generic map (n => 2)
                port map (
                        a_in    => dataRdEn_n_s,
                        a_out   => dataRdEnDly_n_s
                );
 
        dataMemInClk_s  <= not(dataRdEn_n_s) and not(dataRdEnDly_n_s xor dataWrEn_n_s);
        dataMemOutClk_s <= not(dataMemInClk_s);
 
 
        dataRdEn_n_s <= '0' when (cs_s = '0' and spiRdEn_n_s = '0' and spiMemSel_s = "01") or
                                 (cs_s = '1' and procDataEn_n_s = '0') else
                                            '1';
        dataWrEn_n_s <= '0' when (cs_s = '0' and spiWrEn_n_s = '0' and spiMemSel_s = "01") or
                                 (cs_s = '1' and procDataWr_n_s = '0') else
                        '1';
 
        ioDataIn_s <= ioDataGpio_s     when ioPortEn_n_s = '0' else
                      ioTimerDataOut_s when ioTimerEn_n_s = '0' else
                                          mduIoDataOut_s     when mduEn_n_s = '0' else
                      (others => '0');
 
        vliwProc_i : vliwProc
        port map (
                clk            => mclk_s,
 
                instMemAddr    => instAddr_s,
                instMemDataIn  => instDataOut_s,
                instMemEn_n    => instEn_n_s,
 
                ioMemAddr      => ioAddr_s,
                ioMemDataOut   => ioDataOut_s,
                ioMemDataIn    => ioDataIn_s,
                ioMemEn_n      => ioEn_n_s,
                ioMemWr_n      => ioWr_n_s,
 
                dataMemAddr    => procDataAddr_s,
                dataMemDataOut => procDataIn_s,
                dataMemDataIn  => procDataOut_s,
                dataMemEn_n    => procDataEn_n_s,
                dataMemWr_n    => procDataWr_n_s,
 
                irqLine        => irqLine_s,
                irqLineAck     => irqLineAck_s,
 
                stall_n        => stall_n_s,
                stalled_n      => stalled_n_s,
 
                rst_n          => rst_n_s
        );
 
        -- instruction  memory (read only)
        ----------------------------------
        spiSlave_i: spiSlave
        port map (
                sclk      => sclk_s,
                cs        => cs_s,
                mosi      => mosi_s,
                miso      => miso_s,
 
                addr      => spiAddr_s,
                memSel    => spiMemSel_s,
 
                dataOut   => spiDataOut_s,
                dataIn    => spiDataIn_s,
 
                writeEn_n => spiWrEn_n_s,
                readEn_n  => spiRdEn_n_s,
 
                -- rst_n     => '0'
                rst_n     => rst_n_s
        );
 
        spiCsIn_s <= jp2(32);
        stall_n_s <= '0' when spiCsIn_s = '0' else
                     '1';
        cs_s <= '0' when  spiCsIn_s = '0' and stalled_n_s = '0' else
                '1';
        jp2(32) <= 'Z';
 
        spiDataIn_s <= instDataOut_s(31 downto 0) when cs_s = '0' and spiMemSel_s = "00" else
                       x"000000" & procDataOut_s  when cs_s = '0' and spiMemSel_s = "01" else
                       (others => '0');
        jp2(33) <= '1'    when spiCsIn_s = '0' and stalled_n_s = '1' else
                   miso_s when cs_s = '0' else
                   'Z';
        mosi_s <= jp2(34);
        sclk_s <= jp2(35);
 
        ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00010" else
                        '1';
 
        ioport_i : ioport
        port map (
                cs_n     => ioPortEn_n_s,
                clk      => sclk_s,
 
                mdbwr_n  => ioWr_n_s,
                mdb_i           => ioDataOut_s,
                mdb_o           => ioDataGpio_s,
                mab     => ioAddr_s(2 downto 0),
 
                irq      => ioPortIrq_s,
                irqAck   => irqLineAck_s(4),
 
                -- port interface
                PnIN    => gpio_in_s,
                PnOUT           => gpio_out_s,
                PnOEN   => gpio_dir_s,
 
                rst_n           => rst_n_s
        );
 
        ioTimerEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00011" else
                         '1';
 
        timer_i : timer
        port map (
                clk       => mclk_s,
                -- clk       => '0',
 
                addr      => ioAddr_s(2 downto 0),
 
                writeEn_n => ioWr_n_s,
                readEn_n  => ioTimerEn_n_s,
 
                dataOut   => ioTimerDataOut_s,
                dataIn    => ioDataOut_s,
 
                irq       => timer_irq_s,
                irq_ack   => irqLineAck_s(3),
 
                rst_n     => rst_n_s
        );
 
end rtl;

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Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [design/] [AlteraDK1/] [AlteraDK1.vhd] - Blame information for rev 9

Line No.	Rev	Author	Line
1	2	steckol	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_arith.all;`
4
5			`library altera;`
6			`use altera.altera_syn_attributes.all;`
7
8			`entity alteraDK1 is`
9			`port (`
10			`clock : in std_logic;`
11
12			`-- 7-Segments-LEDs`
13			`hex0 : out std_logic_vector(6 downto 0);`
14			`hex1 : out std_logic_vector(6 downto 0);`
15			`hex2 : out std_logic_vector(6 downto 0);`
16			`hex3 : out std_logic_vector(6 downto 0);`
17
18			`-- GPIO`
19			`jp1 : inout std_logic_vector(0 to 35);`
20			`jp2 : inout std_logic_vector(0 to 35);`
21
22			`-- UART`
23			`uart0_rxd : in std_logic;`
24			`uart0_txd : out std_logic;`
25
26			`-- keys`
27			`key : in std_logic_vector(3 downto 0);`
28			`-- switches`
29			`sw : in std_logic_vector(9 downto 0);`
30
31			`-- LEDs`
32			`led_red : out std_logic_vector(9 downto 0);`
33			`led_green : out std_logic_vector(7 downto 0)`
34			`);`
35			`end alteraDK1;`
36
37			`architecture rtl of AlteraDK1 is`
38
39			`component instMem IS`
40			`PORT (`
41			`address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);`
42			`data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);`
43			`inclock : IN STD_LOGIC := '1';`
44			`outclock : IN STD_LOGIC ;`
45			`wren : IN STD_LOGIC ;`
46			`q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)`
47			`);`
48			`END component;`
49
50			`component dataMem IS`
51			`PORT (`
52			`address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);`
53			`data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);`
54			`inclock : IN STD_LOGIC := '1';`
55			`outclock : IN STD_LOGIC ;`
56			`wren : IN STD_LOGIC ;`
57			`q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)`
58			`);`
59			`END component;`
60
61			`component vliwProc`
62			`port (`
63			`clk : in std_logic;`
64
65			`instMemAddr : out std_logic_vector(10 downto 0);`
66			`instMemDataIn : in std_logic_vector(31 downto 0);`
67			`instMemEn_n : out std_logic;`
68
69			`ioMemAddr : out std_logic_vector(7 downto 0);`
70			`ioMemDataOut : out std_logic_vector(7 downto 0);`
71			`ioMemDataIn : in std_logic_vector(7 downto 0);`
72			`ioMemWr_n : out std_logic;`
73			`ioMemEn_n : out std_logic;`
74
75			`-- IO bus`
76			`dataMemAddr : out std_logic_vector(7 downto 0);`
77			`dataMemDataOut : out std_logic_vector(7 downto 0);`
78			`dataMemDataIn : in std_logic_vector(7 downto 0);`
79			`dataMemWr_n : out std_logic;`
80			`dataMemEn_n : out std_logic;`
81
82			`irqLine : in std_logic_vector(4 downto 0);`
83			`irqLineAck : out std_logic_vector(4 downto 0);`
84
85			`stall_n : in std_logic;`
86			`stalled_n : out std_logic;`
87
88			`rst_n : in std_logic`
89			`);`
90			`end component;`
91
92			`component spiSlave`
93			`PORT (`
94			`sclk : IN STD_LOGIC;`
95			`cs : IN STD_LOGIC;`
96			`mosi : IN STD_LOGIC;`
97			`miso : OUT STD_LOGIC;`
98			`addr : OUT std_logic_vector(10 downto 0);`
99			`memSel : out std_logic_vector(1 downto 0);`
100			`writeEn_n : OUT STD_LOGIC;`
101			`readEn_n : OUT STD_LOGIC;`
102
103			`dataOut : OUT std_logic_vector(31 downto 0);`
104			`dataIn : IN std_logic_vector(31 downto 0);`
105
106			`rst_n : IN STD_LOGIC`
107			`);`
108			`end component;`
109
110			`component ioport`
111			`port (`
112			`cs_n : IN STD_LOGIC; -- chip select signal`
113
114			`clk : IN STD_LOGIC;`
115
116			`-- memory interface`
117			`mdbwr_n : IN STD_LOGIC; -- write enable signal`
118			`mdb_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus`
119			`mdb_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus`
120			`mab : IN STD_LOGIC_VECTOR(2 downto 0); -- address registers`
121
122			`-- interrupt interface`
123			`irq : out std_logic;`
124			`irqAck : in std_logic;`
125
126			`-- port interface`
127			`PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)`
128			`PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)`
129			`PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)`
130
131			`-- MODxIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to peripheral`
132			`-- MODxDIR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- direction`
133			`-- MODxOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from peripheral`
134
135			`rst_n : IN STD_LOGIC`
136			`);`
137			`end component;`
138
139			`component timer`
140			`PORT (`
141			`clk : in std_logic;`
142
143			`addr : in std_logic_vector(2 downto 0); -- register address`
144
145			`writeEn_n : in STD_LOGIC; -- write enable, low active`
146			`readEn_n : in STD_LOGIC; -- read enable, low active`
147
148			`dataOut : OUT std_logic_vector(7 downto 0); -- data bus for writing register`
149			`dataIn : IN std_logic_vector(7 downto 0); -- data bus for reading register`
150
151			`irq : out std_logic;`
152			`irq_ack : in std_logic;`
153
154			`rst_n : IN STD_LOGIC -- asynchr. reset, low active`
155			`);`
156			`end component;`
157
158			`component gendelay`
159			`generic (n: integer := 1);`
160			`port (`
161			`a_in : in std_logic;`
162			`a_out : out std_logic`
163			`);`
164			`end component;`
165
166			`signal mclk_s : std_logic; -- main clock`
167
168			`-- mdu interface`
169			`signal mduClk_s : std_logic;`
170			`signal mduDataOut_s : std_logic_vector(31 downto 0);`
171			`signal mduEn_n_s : std_logic;`
172			`signal mduIoDataOut_s : std_logic_vector(7 downto 0);`
173
174			`-- instruction memory interface`
175			`signal instMemAddr_s : std_logic_vector(10 downto 0);`
176			`signal instMemDataIn_s : std_logic_vector(31 downto 0);`
177			`signal instMemInClk_s : std_logic;`
178			`signal instMemOutClk_s : std_logic;`
179			`signal instMemWrEn_s : std_logic;`
180
181			`signal instRdEn_n_s : std_logic;`
182			`signal instRdEnDly_n_s : std_logic;`
183			`signal instWrEn_n_s : std_logic;`
184
185			`signal instAddr_s : std_logic_vector(10 downto 0);`
186			`signal instDataOut_s : std_logic_vector(31 downto 0);`
187			`signal instEn_n_s : std_logic;`
188
189			`-- IO bus`
190			`signal ioAddr_s : std_logic_vector(7 downto 0);`
191			`signal ioDataOut_s : std_logic_vector(7 downto 0);`
192			`signal ioDataIn_s : std_logic_vector(7 downto 0);`
193			`signal ioEn_n_s : std_logic;`
194			`signal ioWr_n_s : std_logic;`
195
196			`-- GPIO signals`
197			`signal ioDataGpio_s : std_logic_vector(7 downto 0);`
198			`signal ioPortEn_n_s : std_logic;`
199			`signal ioPortIrq_s : std_logic;`
200
201			`-- Data bus`
202			`signal procDataAddr_s : std_logic_vector(7 downto 0);`
203			`signal procDataOut_s : std_logic_vector(7 downto 0);`
204			`signal procDataIn_s : std_logic_vector(7 downto 0);`
205			`signal procDataWr_n_s : std_logic;`
206			`signal procDataEn_n_s : std_logic;`
207
208			`signal dataMemAddr_s : std_logic_vector(7 downto 0);`
209			`signal dataMemIn_s : std_logic_vector(7 downto 0);`
210			`signal dataWrEn_s : std_logic;`
211			`signal dataRdEnDly_n_s : std_logic;`
212			`signal dataMemInClk_s : std_logic;`
213			`signal dataMemOutClk_s : std_logic;`
214			`signal dataRdEn_n_s : std_logic;`
215			`signal dataWrEn_n_s : std_logic;`
216
217			`signal rst_n_s : std_logic;`
218
219			`signal stall_n_s : std_logic;`
220			`signal stalled_n_s : std_logic;`
221
222			`signal irqLine_s : std_logic_vector(4 downto 0);`
223			`signal irqLineAck_s : std_logic_vector(4 downto 0);`
224
225			`-- timer signals`
226			`signal timer_irq_s : std_logic;`
227			`signal ioTimerEn_n_s : std_logic;`
228			`signal ioTimerDataOut_s : std_logic_vector(7 downto 0);`
229
230			`-- spi slave`
231			`signal spiCsIn_s : std_logic;`
232			`signal sclk_s : std_logic;`
233			`signal cs_s : std_logic;`
234			`signal mosi_s : std_logic;`
235			`signal miso_s : std_logic;`
236			`signal spiAddr_s : std_logic_vector(10 downto 0);`
237			`signal spiMemSel_s : std_logic_vector(1 downto 0);`
238			`signal spiWrEn_n_s : std_logic;`
239			`signal spiRdEn_n_s : std_logic;`
240			`signal spiDataOut_s : std_logic_vector(31 downto 0);`
241			`signal spiDataIn_s : std_logic_vector(31 downto 0);`
242
243			`signal gpio_in_s : std_logic_vector(7 downto 0);`
244			`signal gpio_out_s : std_logic_vector(7 downto 0);`
245			`signal gpio_dir_s : std_logic_vector(7 downto 0);`
246
247			`begin`
248
249			`gpio_gen: for i in 7 downto 0 generate`
250			`begin`
251			`jp2(i) <= gpio_out_s(i) when gpio_dir_s(i) = '1' else`
252			`'Z';`
253			`gpio_in_s(i) <= jp2(i);`
254			`end generate;`
255
256			`rst_sync: process (clock)`
257			`begin`
258			`if clock'event and clock = '1' then`
259			`rst_n_s <= key(0);`
260			`end if;`
261			`end process;`
262
263			`mclk_s <= clock;`
264
265			`irqLine_s <= ioPortIrq_s & timer_irq_s & "000";`
266
267
268			`-- instruction memory`
269			`---------------------`
270
271			`instMemOut_delay_i: gendelay`
272			`generic map (n => 2)`
273			`port map (`
274			`a_in => instRdEn_n_s,`
275			`a_out => instRdEnDly_n_s`
276			`);`
277
278			`instMem_i : instMem`
279			`port map (`
280			`address => instMemAddr_s,`
281			`data => instMemDataIn_s,`
282			`inclock => instMemInClk_s,`
283			`outclock => instMemOutClk_s,`
284			`wren => instMemWrEn_s,`
285			`q => instDataOut_s`
286			`);`
287
288			`instMemAddr_s <= spiAddr_s when cs_s = '0' and spiMemSel_s = "00" else`
289			`instAddr_s;`
290
291			`instMemDataIn_s <= spiDataOut_s;`
292			`instMemWrEn_s <= not(instWrEn_n_s);`
293
294			`instMemInClk_s <= not(instRdEn_n_s) and not(instRdEnDly_n_s xor instWrEn_n_s);`
295			`instMemOutClk_s <= not(instMemInClk_s);`
296
297			`instRdEn_n_s <= '0' when (cs_s = '0' and spiRdEn_n_s = '0' and spiMemSel_s = "00") or`
298			`(cs_s = '1' and instEn_n_s = '0') else`
299			`'1';`
300			`instWrEn_n_s <= '0' when (cs_s = '0' and spiWrEn_n_s = '0' and spiMemSel_s = "00") else`
301			`'1';`
302
303			`-- data memory`
304			`--------------------------`
305			`dataMem_i : dataMem`
306			`port map (`
307			`address => dataMemAddr_s,`
308			`data => dataMemIn_s,`
309			`inclock => dataMemInClk_s,`
310			`outclock => dataMemOutClk_s,`
311			`wren => dataWrEn_s,`
312			`q => procDataOut_s`
313			`);`
314
315			`dataMemAddr_s <= spiAddr_s(7 downto 0) when cs_s = '0' and spiMemSel_s = "01" else`
316			`procDataAddr_s;`
317
318			`dataMemIn_s <= spiDataOut_s(7 downto 0) when cs_s = '0' and spiMemSel_s = "01" else`
319			`procDataIn_s;`
320			`dataWrEn_s <= not(dataWrEn_n_s);`
321
322			`dataMemOutClk_delay_i: gendelay`
323			`generic map (n => 2)`
324			`port map (`
325			`a_in => dataRdEn_n_s,`
326			`a_out => dataRdEnDly_n_s`
327			`);`
328
329			`dataMemInClk_s <= not(dataRdEn_n_s) and not(dataRdEnDly_n_s xor dataWrEn_n_s);`
330			`dataMemOutClk_s <= not(dataMemInClk_s);`
331
332
333			`dataRdEn_n_s <= '0' when (cs_s = '0' and spiRdEn_n_s = '0' and spiMemSel_s = "01") or`
334			`(cs_s = '1' and procDataEn_n_s = '0') else`
335			`'1';`
336			`dataWrEn_n_s <= '0' when (cs_s = '0' and spiWrEn_n_s = '0' and spiMemSel_s = "01") or`
337			`(cs_s = '1' and procDataWr_n_s = '0') else`
338			`'1';`
339
340			`ioDataIn_s <= ioDataGpio_s when ioPortEn_n_s = '0' else`
341			`ioTimerDataOut_s when ioTimerEn_n_s = '0' else`
342			`mduIoDataOut_s when mduEn_n_s = '0' else`
343			`(others => '0');`
344
345			`vliwProc_i : vliwProc`
346			`port map (`
347			`clk => mclk_s,`
348
349			`instMemAddr => instAddr_s,`
350			`instMemDataIn => instDataOut_s,`
351			`instMemEn_n => instEn_n_s,`
352
353			`ioMemAddr => ioAddr_s,`
354			`ioMemDataOut => ioDataOut_s,`
355			`ioMemDataIn => ioDataIn_s,`
356			`ioMemEn_n => ioEn_n_s,`
357			`ioMemWr_n => ioWr_n_s,`
358
359			`dataMemAddr => procDataAddr_s,`
360			`dataMemDataOut => procDataIn_s,`
361			`dataMemDataIn => procDataOut_s,`
362			`dataMemEn_n => procDataEn_n_s,`
363			`dataMemWr_n => procDataWr_n_s,`
364
365			`irqLine => irqLine_s,`
366			`irqLineAck => irqLineAck_s,`
367
368			`stall_n => stall_n_s,`
369			`stalled_n => stalled_n_s,`
370
371			`rst_n => rst_n_s`
372			`);`
373
374			`-- instruction memory (read only)`
375			`----------------------------------`
376			`spiSlave_i: spiSlave`
377			`port map (`
378			`sclk => sclk_s,`
379			`cs => cs_s,`
380			`mosi => mosi_s,`
381			`miso => miso_s,`
382
383			`addr => spiAddr_s,`
384			`memSel => spiMemSel_s,`
385
386			`dataOut => spiDataOut_s,`
387			`dataIn => spiDataIn_s,`
388
389			`writeEn_n => spiWrEn_n_s,`
390			`readEn_n => spiRdEn_n_s,`
391
392			`-- rst_n => '0'`
393			`rst_n => rst_n_s`
394			`);`
395
396			`spiCsIn_s <= jp2(32);`
397			`stall_n_s <= '0' when spiCsIn_s = '0' else`
398			`'1';`
399			`cs_s <= '0' when spiCsIn_s = '0' and stalled_n_s = '0' else`
400			`'1';`
401			`jp2(32) <= 'Z';`
402
403			`spiDataIn_s <= instDataOut_s(31 downto 0) when cs_s = '0' and spiMemSel_s = "00" else`
404			`x"000000" & procDataOut_s when cs_s = '0' and spiMemSel_s = "01" else`
405			`(others => '0');`
406			`jp2(33) <= '1' when spiCsIn_s = '0' and stalled_n_s = '1' else`
407			`miso_s when cs_s = '0' else`
408			`'Z';`
409			`mosi_s <= jp2(34);`
410			`sclk_s <= jp2(35);`
411
412			`ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00010" else`
413			`'1';`
414
415			`ioport_i : ioport`
416			`port map (`
417			`cs_n => ioPortEn_n_s,`
418			`clk => sclk_s,`
419
420			`mdbwr_n => ioWr_n_s,`
421			`mdb_i => ioDataOut_s,`
422			`mdb_o => ioDataGpio_s,`
423			`mab => ioAddr_s(2 downto 0),`
424
425			`irq => ioPortIrq_s,`
426			`irqAck => irqLineAck_s(4),`
427
428			`-- port interface`
429			`PnIN => gpio_in_s,`
430			`PnOUT => gpio_out_s,`
431			`PnOEN => gpio_dir_s,`
432
433			`rst_n => rst_n_s`
434			`);`
435
436			`ioTimerEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00011" else`
437			`'1';`
438
439			`timer_i : timer`
440			`port map (`
441			`clk => mclk_s,`
442			`-- clk => '0',`
443
444			`addr => ioAddr_s(2 downto 0),`
445
446			`writeEn_n => ioWr_n_s,`
447			`readEn_n => ioTimerEn_n_s,`
448
449			`dataOut => ioTimerDataOut_s,`
450			`dataIn => ioDataOut_s,`
451
452			`irq => timer_irq_s,`
453			`irq_ack => irqLineAck_s(3),`
454
455			`rst_n => rst_n_s`
456			`);`
457
458			`end rtl;`