Subversion Repositories tinyvliw8

--Copyright (C) 1991-2011 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Altera Program License

--Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including,

--without limitation, that your use is for the sole purpose of

--programming logic devices manufactured by Altera and sold by

--Altera or its authorized distributors.  Please refer to the

--applicable agreement for further details.

component dataMem

        PORT

        (

                address         : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                inclock         : IN STD_LOGIC  := '1';

                outclock                : IN STD_LOGIC ;

                wren            : IN STD_LOGIC ;

                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

        );

end component;