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[/] [tinyvliw8/] [trunk/] [design/] [AlteraDK1/] [instMem_inst.vhd] - Blame information for rev 2

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instMem_inst : instMem PORT MAP (
                address  => address_sig,
                data     => data_sig,
                inclock  => inclock_sig,
                outclock         => outclock_sig,
                wren     => wren_sig,
                q        => q_sig
        );

Line No.	Rev	Author	Line
1	2	steckol	`instMem_inst : instMem PORT MAP (`
2			`address => address_sig,`
3			`data => data_sig,`
4			`inclock => inclock_sig,`
5			`outclock => outclock_sig,`
6			`wren => wren_sig,`
7			`q => q_sig`
8			`);`

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[/] [tinyvliw8/] [trunk/] [design/] [AlteraDK1/] [instMem_inst.vhd] - Blame information for rev 2