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--

--      4-bit clock divider module

--

--    file:   clock_divider.vhd

--    author: Oliver Stecklina <stecklina@ihp-microelectronics.com

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

ENTITY clock_divider IS

        generic (n: integer := 2);

        PORT (

                inclk     : in  std_logic;

                outclk    : out std_logic;

                div       : in std_logic_vector((n - 1) downto 0);

                en        : IN std_logic

        );

END clock_divider;

ARCHITECTURE behav OF clock_divider IS

        signal clk_reg : std_logic_vector(((2 ** n) - 2) downto 0);

        signal clk_s   : std_logic_vector(((2 ** n) - 1) downto 0);

        signal enable_s : std_logic;

        signal outclk_s : std_logic_vector(((2 ** n) - 1) downto 0);

begin

        clk_s(0) <= inclk;

        enable_s <= en;

        gen_clk : process(enable_s, clk_s(0))

                variable cnt: unsigned (((2 ** n) - 2) downto 0);

        begin

                if (enable_s = '0') then

                        cnt := (others => '0');

                else

                        if (clk_s(0)'event and clk_s(0) = '0') then

                                cnt := cnt + 1;

                        end if;

                end if;

                clk_reg <= std_logic_vector(cnt);

        end process;

        clkSync_gen: for i in 1 to ((2 ** n) - 1) generate

        begin

                clk_sync : process(enable_s, clk_s(0))

                begin

                        if (enable_s = '0') then

                                clk_s(i) <= '0';

                        else

                                if (clk_s(0)'event and clk_s(0) = '1') then

                                        clk_s(i) <= clk_reg(i - 1);

                                end if;

                        end if;

                end process;

                outclk_s(i - 1) <= clk_s(i) when div = conv_std_logic_vector(i, n) else

                                   outclk_s(i);

        end generate;

        outclk_s((2 ** n) - 1) <= '0';

        outclk <= clk_s(0) when div = conv_std_logic_vector(0, n) else

                  outclk_s(0);

end behav;