Subversion Repositories tinyvliw8

library ieee;

use ieee.std_logic_1164.all;

library altera_mf;

use altera_mf.all;

entity gendelay is

        generic (n: integer := 1);

        port (

                a_in : in std_logic;

                a_out : out std_logic

        );

end gendelay;

architecture beh of gendelay is

--component iobuf

--      PORT

--      (

--              datain          : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

--              dataout         : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

--      );

--END component;

        component LCELL

                port (

                        a_in : in std_logic;

                        a_out : out std_logic

                );

        end component;

        signal a : std_logic_vector ((2 * n) - 1 downto 0);

   signal b : std_logic_vector ((2 * n) - 2 downto 0);

        attribute keep    : boolean;

        attribute keep of a     : signal is true;

        attribute keep of b     : signal is true;

begin

        delay_gen: for i in 1 to (2 * n) - 1 generate

                begin

                        lcell_i : LCELL

                        port map (

                                a_out => b(i - 1),

                                a_in => a(i - 1)

                        );

--                      iobuf_i : iobuf

--                      port map (

--                              datain(0) => a(i - 1),

--                              dataout(0) => b(i - 1)

--                      );

                        a(i) <= b(i - 1) after 300 ps;

                end generate;

        a(0) <= a_in after 300 ps;

        a_out <= a((2 * n) - 1);

end beh;