Subversion Repositories tinyvliw8

Library ieee;

use ieee.std_logic_1164.all;

entity latch is

    port(

        d                        :  in    std_logic;

        ena                      :  in    std_logic;

        q                        :  out   std_logic);

end latch;

architecture BEHAVIOR of latch is

signal iq : std_logic := '0';

begin

    process (d, ena)

    begin

        if (ena = '1') then

            iq <= d;

        end if;

    end process;

    q <= iq;

end BEHAVIOR;