URL https://opencores.org/ocsvn/tinyvliw8/tinyvliw8/trunk

Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [library/] [latch.vhd] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log


Library ieee;
use ieee.std_logic_1164.all;
entity latch is
    port(
        d                        :  in    std_logic;
        ena                      :  in    std_logic;
        q                        :  out   std_logic);
end latch;
architecture BEHAVIOR of latch is
signal iq : std_logic := '0';
begin
    process (d, ena)
    begin
        if (ena = '1') then
            iq <= d;
        end if;
    end process;
    q <= iq;
end BEHAVIOR;
 

Line No.	Rev	Author	Line
1	2	steckol	`Library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`entity latch is`
4			`port(`
5			`d : in std_logic;`
6			`ena : in std_logic;`
7			`q : out std_logic);`
8			`end latch;`
9			`architecture BEHAVIOR of latch is`
10			`signal iq : std_logic := '0';`
11			`begin`
12			`process (d, ena)`
13			`begin`
14			`if (ena = '1') then`
15			`iq <= d;`
16			`end if;`
17			`end process;`
18			`q <= iq;`
19			`end BEHAVIOR;`
20

Browse

Tools

Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [library/] [latch.vhd] - Blame information for rev 9