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steckol |
-----------------------------------------------------------------
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-- Project: Aeternitas
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-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com
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-- Date: 13.11.2013
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-- File: alu.vhd
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-- Design: AeternitasSWUR
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-----------------------------------------------------------------
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-- Description : Arithmetic unit of IHPvliw8 processor
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-----------------------------------------------------------------
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-- $Log$
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-----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity vliwProc_alu is
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port (
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state : in std_logic_vector(3 downto 0);
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enable_n : in std_logic;
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opcode : in std_logic_vector(2 downto 0);
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as : in std_logic_vector(1 downto 0);
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dstRegIn : in std_logic_vector(2 downto 0);
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dataIn : in std_logic_vector(7 downto 0);
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reg0 : in std_logic_vector(7 downto 0);
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reg1 : in std_logic_vector(7 downto 0);
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reg2 : in std_logic_vector(7 downto 0);
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reg3 : in std_logic_vector(7 downto 0);
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reg4 : in std_logic_vector(7 downto 0);
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reg5 : in std_logic_vector(7 downto 0);
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reg6 : in std_logic_vector(7 downto 0);
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reg7 : in std_logic_vector(7 downto 0);
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cIn : in std_logic;
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cOut : out std_logic;
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zOut : out std_logic;
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dstRegEn_n : out std_logic;
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dstRegOut : out std_logic_vector(2 downto 0);
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dataOut : out std_logic_vector(7 downto 0);
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rst_n : in std_logic
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);
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end vliwProc_alu;
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architecture behavior of vliwProc_alu is
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signal cIn_s : std_logic;
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signal as_s : std_logic_vector(1 downto 0);
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signal opcode_s : std_logic_vector(2 downto 0);
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signal dstRegIn_s : std_logic_vector(2 downto 0);
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signal cShift_s : std_logic;
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signal cAdd_s : std_logic;
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signal shift_s : std_logic;
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signal logic_s : std_logic;
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signal arith_s : std_logic;
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signal dataOut_s : std_logic_vector(7 downto 0);
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signal op0_s : std_logic_vector(7 downto 0);
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signal op1_s : std_logic_vector(7 downto 0);
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signal aluEn_s : std_logic;
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signal rst_n_s : std_logic;
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begin
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rst_n_s <= rst_n;
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enable_p : process(rst_n_s, state(2))
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begin
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if (rst_n_s = '0') then
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aluEn_s <= '0';
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else
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if (state(2)'event and state(2) = '1') then
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if (enable_n = '0') then
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aluEn_s <= '1';
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else
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aluEn_s <= '0';
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end if;
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end if;
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end if;
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end process;
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commitIn_proc : process(rst_n_s, state(2))
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variable shift_v : std_logic;
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variable logic_v : std_logic;
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variable arith_v : std_logic;
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variable op0_v : unsigned(8 downto 0);
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variable op1_v : unsigned(8 downto 0);
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begin
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if (rst_n_s = '0') then
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cIn_s <= '0';
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as_s <= (others => '0');
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opcode_s <= (others => '0');
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dstRegIn_s <= (others => '0');
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op0_v := (others => '0');
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op1_v := (others => '0');
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shift_v := '0';
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logic_v := '0';
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arith_v := '0';
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cAdd_s <= '0';
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else
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if (state(2)'event and state(2) = '1') then
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shift_v := '0';
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logic_v := '0';
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arith_v := '0';
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if (enable_n = '0') then
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cIn_s <= cIn;
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as_s <= as;
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opcode_s <= opcode;
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dstRegIn_s <= dstRegIn;
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case opcode IS
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when "010" => arith_v := '1';
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when "011" => shift_v := '1';
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when "100" => logic_v := '1';
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when "101" => logic_v := '1';
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when "110" => logic_v := '1';
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WHEN others => null;
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end case;
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if (shift_v = '1') then
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if (as(0) = '0' or as(1) = '0') then
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CASE dataIn(2 downto 0) IS
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WHEN "000" => op0_v := unsigned('0' & reg0);
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WHEN "001" => op0_v := unsigned('0' & reg1);
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WHEN "010" => op0_v := unsigned('0' & reg2);
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WHEN "011" => op0_v := unsigned('0' & reg3);
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WHEN "100" => op0_v := unsigned('0' & reg4);
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WHEN "101" => op0_v := unsigned('0' & reg5);
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WHEN "110" => op0_v := unsigned('0' & reg6);
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WHEN "111" => op0_v := unsigned('0' & reg7);
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WHEN others => null;
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END CASE;
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op1_v := unsigned('0' & dataIn);
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else -- mov Rx, #NUM
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op0_v := unsigned('0' & dataIn);
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end if;
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elsif (logic_v = '1') then
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if (as(0) = '0') then
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if (dataIn(7) = '0') then
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case dataIn(6 downto 4) is
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when "000" => op0_v := unsigned('0' & reg0);
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when "001" => op0_v := unsigned('0' & reg1);
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when "010" => op0_v := unsigned('0' & reg2);
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when "011" => op0_v := unsigned('0' & reg3);
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when "100" => op0_v := unsigned('0' & reg4);
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when "101" => op0_v := unsigned('0' & reg5);
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when "110" => op0_v := unsigned('0' & reg6);
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when "111" => op0_v := unsigned('0' & reg7);
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when others => null;
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end case;
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else
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case dataIn(6 downto 4) is
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when "000" => op0_v := unsigned(not('0' & reg0));
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when "001" => op0_v := unsigned(not('0' & reg1));
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when "010" => op0_v := unsigned(not('0' & reg2));
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when "011" => op0_v := unsigned(not('0' & reg3));
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when "100" => op0_v := unsigned(not('0' & reg4));
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when "101" => op0_v := unsigned(not('0' & reg5));
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when "110" => op0_v := unsigned(not('0' & reg6));
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when "111" => op0_v := unsigned(not('0' & reg7));
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when others => null;
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end case;
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end if;
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if (dataIn(3) = '0') then
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case dataIn(2 downto 0) is
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when "000" => op1_v := unsigned('0' & reg0);
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when "001" => op1_v := unsigned('0' & reg1);
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when "010" => op1_v := unsigned('0' & reg2);
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when "011" => op1_v := unsigned('0' & reg3);
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when "100" => op1_v := unsigned('0' & reg4);
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when "101" => op1_v := unsigned('0' & reg5);
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when "110" => op1_v := unsigned('0' & reg6);
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when "111" => op1_v := unsigned('0' & reg7);
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when others => null;
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end case;
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else
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case dataIn(2 downto 0) is
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when "000" => op1_v := unsigned(not('0' & reg0));
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when "001" => op1_v := unsigned(not('0' & reg1));
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when "010" => op1_v := unsigned(not('0' & reg2));
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when "011" => op1_v := unsigned(not('0' & reg3));
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when "100" => op1_v := unsigned(not('0' & reg4));
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when "101" => op1_v := unsigned(not('0' & reg5));
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when "110" => op1_v := unsigned(not('0' & reg6));
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when "111" => op1_v := unsigned(not('0' & reg7));
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when others => null;
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end case;
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end if;
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else
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CASE dstRegIn IS
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WHEN "000" => op0_v := unsigned('0' & reg0);
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WHEN "001" => op0_v := unsigned('0' & reg1);
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WHEN "010" => op0_v := unsigned('0' & reg2);
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WHEN "011" => op0_v := unsigned('0' & reg3);
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WHEN "100" => op0_v := unsigned('0' & reg4);
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WHEN "101" => op0_v := unsigned('0' & reg5);
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WHEN "110" => op0_v := unsigned('0' & reg6);
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WHEN "111" => op0_v := unsigned('0' & reg7);
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WHEN others => null;
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END CASE;
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op1_v := unsigned('0' & dataIn);
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end if;
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elsif (arith_v = '1') then
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if (as(0) = '0') then
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if (dataIn(7) = '0') then
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case dataIn(6 downto 4) is
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when "000" => op0_v := unsigned('0' & reg0);
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when "001" => op0_v := unsigned('0' & reg1);
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when "010" => op0_v := unsigned('0' & reg2);
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when "011" => op0_v := unsigned('0' & reg3);
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when "100" => op0_v := unsigned('0' & reg4);
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when "101" => op0_v := unsigned('0' & reg5);
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when "110" => op0_v := unsigned('0' & reg6);
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when "111" => op0_v := unsigned('0' & reg7);
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when others => null;
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end case;
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else
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case dataIn(6 downto 4) is
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when "000" => op0_v := unsigned(not('0' & reg0));
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when "001" => op0_v := unsigned(not('0' & reg1));
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when "010" => op0_v := unsigned(not('0' & reg2));
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when "011" => op0_v := unsigned(not('0' & reg3));
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when "100" => op0_v := unsigned(not('0' & reg4));
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when "101" => op0_v := unsigned(not('0' & reg5));
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when "110" => op0_v := unsigned(not('0' & reg6));
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when "111" => op0_v := unsigned(not('0' & reg7));
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when others => null;
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end case;
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op0_v := op0_v + 1;
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end if;
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if (dataIn(3) = '0') then
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case dataIn(2 downto 0) is
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when "000" => op1_v := unsigned('0' & reg0);
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when "001" => op1_v := unsigned('0' & reg1);
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when "010" => op1_v := unsigned('0' & reg2);
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when "011" => op1_v := unsigned('0' & reg3);
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when "100" => op1_v := unsigned('0' & reg4);
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when "101" => op1_v := unsigned('0' & reg5);
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when "110" => op1_v := unsigned('0' & reg6);
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when "111" => op1_v := unsigned('0' & reg7);
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when others => null;
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end case;
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else
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-- two's complement
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case dataIn(2 downto 0) is
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| 268 |
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when "000" => op1_v := unsigned(not('0' & reg0));
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| 269 |
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when "001" => op1_v := unsigned(not('0' & reg1));
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| 270 |
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when "010" => op1_v := unsigned(not('0' & reg2));
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| 271 |
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when "011" => op1_v := unsigned(not('0' & reg3));
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| 272 |
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when "100" => op1_v := unsigned(not('0' & reg4));
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| 273 |
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when "101" => op1_v := unsigned(not('0' & reg5));
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| 274 |
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when "110" => op1_v := unsigned(not('0' & reg6));
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| 275 |
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when "111" => op1_v := unsigned(not('0' & reg7));
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| 276 |
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when others => null;
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| 277 |
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end case;
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| 278 |
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| 279 |
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op1_v := op1_v + 1;
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| 280 |
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end if;
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| 281 |
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else
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| 282 |
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CASE dstRegIn IS
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| 283 |
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WHEN "000" => op0_v := unsigned('0' & reg0);
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| 284 |
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WHEN "001" => op0_v := unsigned('0' & reg1);
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| 285 |
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WHEN "010" => op0_v := unsigned('0' & reg2);
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| 286 |
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WHEN "011" => op0_v := unsigned('0' & reg3);
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| 287 |
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WHEN "100" => op0_v := unsigned('0' & reg4);
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| 288 |
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WHEN "101" => op0_v := unsigned('0' & reg5);
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| 289 |
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WHEN "110" => op0_v := unsigned('0' & reg6);
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| 290 |
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WHEN "111" => op0_v := unsigned('0' & reg7);
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| 291 |
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WHEN others => null;
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| 292 |
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END CASE;
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| 293 |
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| 294 |
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op1_v := unsigned('0' & dataIn);
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| 295 |
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end if;
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| 296 |
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| 297 |
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-- addition
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| 298 |
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op0_v := op0_v + op1_v;
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| 299 |
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| 300 |
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-- carry add
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| 301 |
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if (as(1) = '1' and cIn = '1') then
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| 302 |
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op0_v := op0_v + 1;
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| 303 |
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end if;
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| 304 |
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| 305 |
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cAdd_s <= std_logic(op0_v(8));
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end if;
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| 307 |
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end if;
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| 308 |
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end if;
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| 309 |
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end if;
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| 310 |
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| 311 |
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shift_s <= std_logic(shift_v);
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| 312 |
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logic_s <= std_logic(logic_v);
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| 313 |
|
|
arith_s <= std_logic(arith_v);
|
| 314 |
|
|
|
| 315 |
|
|
op0_s <= std_logic_vector(op0_v(7 downto 0));
|
| 316 |
|
|
op1_s <= std_logic_vector(op1_v(7 downto 0));
|
| 317 |
|
|
end process;
|
| 318 |
|
|
|
| 319 |
|
|
cShift_s <= op0_s(7) when as_s(0) = '0' and as(1) = '0' else -- shift left
|
| 320 |
|
|
op0_s(0) when as_s(0) = '0' and as(1) = '1' else -- shift right
|
| 321 |
|
|
'0';
|
| 322 |
|
|
|
| 323 |
|
|
dataOut_s <= op0_s(6 downto 0) & '0' when shift_s = '1' and as_s = "00" and op1_s(3) = '0' else
|
| 324 |
|
|
op0_s(6 downto 0) & cIn_s when shift_s = '1' and as_s = "00" and op1_s(3) = '1' else
|
| 325 |
|
|
op0_s(7) & op0_s(7 downto 1) when shift_s = '1' and as_s = "01" and op1_s(3) = '0' else
|
| 326 |
|
|
cIn_s & op0_s(7 downto 1) when shift_s = '1' and as_s = "01" and op1_s(3) = '1' else
|
| 327 |
|
|
not(op0_s) when shift_s = '1' and as_s = "10" and op1_s(3) = '1' else
|
| 328 |
|
|
op0_s when shift_s = '1' and as_s(0) = '1' else
|
| 329 |
|
|
op0_s and op1_s when logic_s = '1' and opcode_s = "100" and as_s(1) = '0' else
|
| 330 |
|
|
not(op0_s and op1_s) when logic_s = '1' and opcode_s = "100" and as_s(1) = '1' else
|
| 331 |
|
|
op0_s or op1_s when logic_s = '1' and opcode_s = "101" and as_s(1) = '0' else
|
| 332 |
|
|
not(op0_s or op1_s) when logic_s = '1' and opcode_s = "101" and as_s(1) = '1' else
|
| 333 |
|
|
op0_s xor op1_s when logic_s = '1' and opcode_s = "110" and as_s(1) = '0' else
|
| 334 |
|
|
not(op0_s xor op1_s) when logic_s = '1' and opcode_s = "110" and as_s(1) = '1' else
|
| 335 |
|
|
op0_s when arith_s = '1' else
|
| 336 |
|
|
(others => '0');
|
| 337 |
|
|
|
| 338 |
|
|
cOut <= cAdd_s when aluEn_s = '1' and arith_s = '1' else -- arithmetic operations
|
| 339 |
|
|
cShift_s when aluEn_s = '1' and shift_s = '1' and as_s(0) = '0' else -- shift
|
| 340 |
|
|
'0';
|
| 341 |
|
|
|
| 342 |
|
|
dataOut <= dataOut_s when aluEn_s = '1' else
|
| 343 |
|
|
(others => '0');
|
| 344 |
|
|
zOut <= '1' when aluEn_s = '1' and dataOut_s = "00000000" else
|
| 345 |
|
|
'0';
|
| 346 |
|
|
|
| 347 |
|
|
dstRegEn_n <= '0' when aluEn_s = '1' else
|
| 348 |
|
|
'1';
|
| 349 |
|
|
dstRegOut <= dstRegIn_s when aluEn_s = '1' else
|
| 350 |
|
|
(others => '0');
|
| 351 |
|
|
|
| 352 |
|
|
end behavior;
|
