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-------------------------------------------------------------------------------
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--
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-- Design: tinyVLIW8 soft-core processor
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-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
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-- Date: 03.02.2014
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-- File: instDecoder.vhd
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--
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-------------------------------------------------------------------------------
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--
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-- Description : This unit is the instruction set decoder of the
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-- embedded 8-bit VLIW processor.
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
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--
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-- This code is free software. It is licensed under the EUPL, Version 1.1
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-- or - as soon they will be approved by the European Commission - subsequent
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-- versions of the EUPL (the "License").
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-- You may redistribute this code and/or modify it under the terms of this
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-- License.
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-- You may not use this work except in compliance with the License.
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-- You may obtain a copy of the License at:
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--
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-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" basis,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity vliwProc_instDecoder is
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port (
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clk : in std_logic;
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instData : in std_logic_vector(31 downto 0);
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ldstOpCode : out std_logic;
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ldstAs : out std_logic_vector(1 downto 0);
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ldstDstReg : out std_logic_vector(2 downto 0);
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ldstSrc : out std_logic_vector(7 downto 0);
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ldstEn_n : out std_logic;
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aluOpCode : out std_logic_vector(2 downto 0);
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aluAs : out std_logic_vector(1 downto 0);
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aluDstReg : out std_logic_vector(2 downto 0);
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aluSrc : out std_logic_vector(7 downto 0);
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aluEn_n : out std_logic;
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jmpAs : out std_logic_vector(1 downto 0);
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jmpDstReg : out std_logic_vector(10 downto 0);
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jmpEn_n : out std_logic;
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esb : out std_logic_vector(3 downto 0);
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stalled_n : out std_logic;
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stall_n : in std_logic;
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rst_n : in std_logic
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);
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end vliwProc_instDecoder;
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architecture behavior of vliwProc_instDecoder is
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component gendelay
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generic (n: integer := 1);
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port (
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a_in : in std_logic;
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a_out : out std_logic
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);
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end component;
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signal instWord0_s : std_logic_vector(15 downto 0);
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signal instWord1_s : std_logic_vector(15 downto 0);
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signal clk_s : std_logic;
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signal esb_s : std_logic_vector(3 downto 0);
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signal untSel0_n_s : std_logic_vector(2 downto 0);
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signal untSel1_n_s : std_logic_vector(2 downto 0);
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signal stalled_n_s : std_logic;
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signal ldstEn_n_s : std_logic;
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signal aluEn_n_s : std_logic;
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signal jmpEn_n_s : std_logic;
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signal cnt_s : std_logic_vector(1 downto 0);
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begin
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clk_s <= clk;
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stalled_n <= stalled_n_s;
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-- Note! use cnt_s instead of esb to be faster than esb
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-- otherwise we get a glitch on esb(0) in case of stall
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sync_Stall: process(rst_n, cnt_s(0))
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begin
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if (rst_n = '0') then
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stalled_n_s <= '1';
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else
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if (cnt_s(0)'event and cnt_s(0) = '1') then
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stalled_n_s <= stall_n;
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end if;
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end if;
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end process;
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ldstEn_n <= ldstEn_n_s;
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jmpEn_n <= jmpEn_n_s;
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aluEn_n <= aluEn_n_s;
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genState_p : process(rst_n, clk_s)
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begin
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if (rst_n = '0') then
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cnt_s <= "01";
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else
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if (clk_s'event and clk_s = '0') then
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cnt_s(1) <= not(cnt_s(1));
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end if;
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if (clk_s'event and clk_s = '1') then
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cnt_s(0) <= not(cnt_s(0));
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end if;
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end if;
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end process;
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-- execution state bus
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esb_s <= "0001" when rst_n = '1' and cnt_s = "01" else
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"0010" when rst_n = '1' and cnt_s = "11" else
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"0100" when rst_n = '1' and cnt_s = "10" else
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"1000" when rst_n = '1' and cnt_s = "00" else
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"0000";
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esb <= esb_s when stalled_n_s = '1' else
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(others => '0');
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untSel1_n_s <= "111" when instWord0_s(15 downto 13) = instWord1_s(15 downto 13) else
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"110" when instWord1_s(15 downto 13) = "111" else
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"101" when instWord1_s(15 downto 13) = "000" or instWord1_s(15 downto 13) = "001" else
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"011";
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untSel0_n_s <= "110" when instWord0_s(15 downto 13) = "111" else
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"101" when instWord0_s(15 downto 13) = "000" or instWord0_s(15 downto 13) = "001" else
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"011";
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jmpEn_n_s <= '0' when (untSel0_n_s(0) = '0' or untSel1_n_s(0) = '0') and cnt_s(1) = '1' else
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'1';
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ldstEn_n_s <= '0' when (untSel0_n_s(1) = '0' or untSel1_n_s(1) = '0') and cnt_s(1) = '1' else
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'1';
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aluEn_n_s <= '0' when (untSel0_n_s(2) = '0' or untSel1_n_s(2) = '0') and cnt_s(1) = '1' else
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'1';
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instWord0_s <= instData(31 downto 16);
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instWord1_s <= instData(15 downto 0);
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aluOpCode <= instWord0_s(15 downto 13) when untSel0_n_s(2) = '0' else
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instWord1_s(15 downto 13) when untSel1_n_s(2) = '0' else
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(others => '0');
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aluAs <= instWord0_s(12 downto 11) when untSel0_n_s(2) = '0' else
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instWord1_s(12 downto 11) when untSel1_n_s(2) = '0' else
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(others => '0');
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aluDstReg <= instWord0_s(10 downto 8) when untSel0_n_s(2) = '0' else
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instWord1_s(10 downto 8) when untSel1_n_s(2) = '0' else
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(others => '0');
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aluSrc <= instWord0_s(7 downto 0) when untSel0_n_s(2) = '0' else
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instWord1_s(7 downto 0) when untSel1_n_s(2) = '0' else
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(others => '0');
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ldstOpCode <= instWord0_s(13) when untSel0_n_s(1) = '0' else
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instWord1_s(13) when untSel1_n_s(1) = '0' else
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'0';
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ldstAs <= instWord0_s(12 downto 11) when untSel0_n_s(1) = '0' else
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instWord1_s(12 downto 11) when untSel1_n_s(1) = '0' else
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(others => '0');
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ldstDstReg <= instWord0_s(10 downto 8) when untSel0_n_s(1) = '0' else
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instWord1_s(10 downto 8) when untSel1_n_s(1) = '0' else
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(others => '0');
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ldstSrc <= instWord0_s(7 downto 0) when untSel0_n_s(1) = '0' else
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instWord1_s(7 downto 0) when untSel1_n_s(1) = '0' else
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(others => '0');
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jmpAs <= instWord0_s(12 downto 11) when untSel0_n_s(0) = '0' else
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instWord1_s(12 downto 11) when untSel1_n_s(0) = '0' else
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(others => '0');
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jmpDstReg <= instWord0_s(10 downto 0) when untSel0_n_s(0) = '0' else
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instWord1_s(10 downto 0) when untSel1_n_s(0) = '0' else
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(others => '0');
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end behavior;
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