Subversion Repositories tinyvliw8

-----------------------------------------------------------------

-- Project: Aeternitas

-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com>

-- Date:    03.02.2014 

-- File:    instDecoder.vhd

-- Design:  AeternitasSWUR

-----------------------------------------------------------------

-- Description : This unit is the instruction set decoder of the

--               embedded 8-bit VLIW processor.

-----------------------------------------------------------------

-- $Log$

-----------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity vliwProc_instDecoder is

        port (

                clk        : in std_logic;

                instData   : in  std_logic_vector(31 downto 0);

                ldstOpCode : out std_logic;

                ldstAs     : out std_logic_vector(1 downto 0);

                ldstDstReg : out std_logic_vector(2 downto 0);

                ldstSrc    : out std_logic_vector(7 downto 0);

                ldstEn_n   : out std_logic;

                aluOpCode  : out std_logic_vector(2 downto 0);

                aluAs      : out std_logic_vector(1 downto 0);

                aluDstReg  : out std_logic_vector(2 downto 0);

                aluSrc     : out std_logic_vector(7 downto 0);

                aluEn_n    : out std_logic;

                jmpAs      : out std_logic_vector(1 downto 0);

                jmpDstReg  : out std_logic_vector(10 downto 0);

                jmpEn_n    : out std_logic;

                esb        : out std_logic_vector(3 downto 0);

                stalled_n  : out std_logic;

                stall_n    : in std_logic;

                rst_n      : in std_logic

        );

end vliwProc_instDecoder;

architecture behavior of vliwProc_instDecoder is

component gendelay

        generic (n: integer := 1);

        port (

                a_in    : in    std_logic;

                a_out   : out   std_logic

        );

end component;

        signal instWord0_s  : std_logic_vector(15 downto 0);

        signal instWord1_s  : std_logic_vector(15 downto 0);

        signal clk_s          : std_logic;

        signal esb_s           : std_logic_vector(3 downto 0);

        signal untSel0_n_s : std_logic_vector(2 downto 0);

        signal untSel1_n_s : std_logic_vector(2 downto 0);

        signal stalled_n_s : std_logic;

        signal ldstEn_n_s  : std_logic;

        signal aluEn_n_s   : std_logic;

        signal jmpEn_n_s   : std_logic;

        signal cnt_s      : std_logic_vector(1 downto 0);

begin

        clk_s     <= clk;

        stalled_n <= stalled_n_s;

        -- Note! use cnt_s instead of esb to be faster than esb

        --    otherwise we get a glitch on esb(0) in case of stall

        sync_Stall: process(rst_n, cnt_s(0))

        begin

                if (rst_n = '0') then

                        stalled_n_s <= '1';

                else

                        if (cnt_s(0)'event and cnt_s(0) = '1') then

                                stalled_n_s <= stall_n;

                        end if;

                end if;

        end process;

        ldstEn_n <= ldstEn_n_s;

        jmpEn_n <= jmpEn_n_s;

        aluEn_n <= aluEn_n_s;

        genState_p : process(rst_n, clk_s)

        begin

                if (rst_n = '0') then

                        cnt_s <= "01";

                else

                        if (clk_s'event and clk_s = '0') then

                                cnt_s(1) <= not(cnt_s(1));

                        end if;

                        if (clk_s'event and clk_s = '1') then

                                cnt_s(0) <= not(cnt_s(0));

                        end if;

                end if;

        end process;

        -- execution state bus

        esb_s <= "0001" when rst_n = '1' and cnt_s = "01" else

                 "0010" when rst_n = '1' and cnt_s = "11" else

                 "0100" when rst_n = '1' and cnt_s = "10" else

                 "1000" when rst_n = '1' and cnt_s = "00" else

                 "0000";

        esb <= esb_s when stalled_n_s = '1' else

               (others => '0');

        untSel1_n_s <= "111" when instWord0_s(15 downto 13) = instWord1_s(15 downto 13) else

                       "110" when instWord1_s(15 downto 13) = "111" else

                                   "101" when instWord1_s(15 downto 13) = "000" or instWord1_s(15 downto 13) = "001" else

                                   "011";

        untSel0_n_s <= "110" when instWord0_s(15 downto 13) = "111" else

                                   "101" when instWord0_s(15 downto 13) = "000" or instWord0_s(15 downto 13) = "001" else

                                   "011";

        jmpEn_n_s  <= '0' when (untSel0_n_s(0) = '0' or untSel1_n_s(0) = '0') and cnt_s(1) = '1' else

                      '1';

        ldstEn_n_s <= '0' when (untSel0_n_s(1) = '0' or untSel1_n_s(1) = '0') and cnt_s(1) = '1' else

                      '1';

        aluEn_n_s  <= '0' when (untSel0_n_s(2) = '0' or untSel1_n_s(2) = '0') and cnt_s(1) = '1' else

                      '1';

        instWord0_s <= instData(31 downto 16);

        instWord1_s <= instData(15 downto 0);

        aluOpCode  <= instWord0_s(15 downto 13)  when untSel0_n_s(2) = '0' else

                      instWord1_s(15 downto 13)  when untSel1_n_s(2) = '0' else

                      (others => '0');

        aluAs      <= instWord0_s(12 downto 11) when untSel0_n_s(2) = '0' else

                      instWord1_s(12 downto 11) when untSel1_n_s(2) = '0' else

                      (others => '0');

        aluDstReg  <= instWord0_s(10 downto 8)  when untSel0_n_s(2) = '0' else

                      instWord1_s(10 downto 8)  when untSel1_n_s(2) = '0' else

                      (others => '0');

        aluSrc     <= instWord0_s(7 downto 0)   when untSel0_n_s(2) = '0' else

                      instWord1_s(7 downto 0)   when untSel1_n_s(2) = '0' else

                      (others => '0');

        ldstOpCode  <= instWord0_s(13)           when untSel0_n_s(1) = '0' else

                       instWord1_s(13)           when untSel1_n_s(1) = '0' else

                       '0';

        ldstAs      <= instWord0_s(12 downto 11) when untSel0_n_s(1) = '0' else

                       instWord1_s(12 downto 11) when untSel1_n_s(1) = '0' else

                       (others => '0');

        ldstDstReg  <= instWord0_s(10 downto 8)  when untSel0_n_s(1) = '0' else

                       instWord1_s(10 downto 8)  when untSel1_n_s(1) = '0' else

                       (others => '0');

        ldstSrc     <= instWord0_s(7 downto 0)   when untSel0_n_s(1) = '0' else

                       instWord1_s(7 downto 0)   when untSel1_n_s(1) = '0' else

                       (others => '0');

        jmpAs      <= instWord0_s(12 downto 11) when untSel0_n_s(0) = '0' else

                      instWord1_s(12 downto 11) when untSel1_n_s(0) = '0' else

                      (others => '0');

        jmpDstReg  <= instWord0_s(10 downto 0)  when untSel0_n_s(0) = '0' else

                      instWord1_s(10 downto 0)  when untSel1_n_s(0) = '0' else

                      (others => '0');

end behavior;