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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [proc/] [irqCntl.vhd] - Blame information for rev 9

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1 2 steckol 
library ieee;
2 
use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
4 
 
5 
entity vliwProc_irqCntl is
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        port (
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                state      : in std_logic_vector(3 downto 0);
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                stalled_n  : in std_logic;
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                irqLineIn  : in  std_logic_vector(5 downto 0);
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                irqLineOut : out std_logic_vector(5 downto 0);
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                irqAck     : out std_logic;
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                irqAddr    : out std_logic_vector(1 downto 0);
15 9 steckol 
 
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                ioDataIn   : in std_logic_vector(7 downto 0);
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                ioDataOut  : out std_logic_vector(7 downto 0);
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                ioInEn_n   : in std_logic;
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                ioInWr_n   : in std_logic;
20 2 steckol 
 
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                enable     : in std_logic;
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                -- reset input
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                rst_n      : in std_logic
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        );
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end vliwProc_irqCntl;
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architecture behavior of vliwProc_irqCntl is
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        signal irq_s        : std_logic;
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        signal irqAck_s     : std_logic;
32 9 steckol 
        signal irqAddr_s    : std_logic_vector(1 downto 0);
33 2 steckol 
 
34 9 steckol 
        signal irqLineOut_s : std_logic_vector(3 downto 0);
35 2 steckol 
        signal irqLineIn_s  : std_logic_vector(3 downto 0);
36 9 steckol 
 
37 2 steckol 
        signal irqLine_s    : std_logic;
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        signal irqUpd_s     : std_logic;
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40 9 steckol 
        signal irqCtrl_r    : std_logic_vector(7 downto 0);
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42 2 steckol 
begin
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44 9 steckol 
        ------------------------------------------------------------------------------------------
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        --
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        --   IRQ line multiplexer
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        --
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        ------------------------------------------------------------------------------------------
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        irqLineIn_s(0) <= '1' when rst_n = '1' and ((irqCtrl_r(1 downto 0) = "01" and irqLineIn(0) = '1') or
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                                                    (irqCtrl_r(1 downto 0) = "10" and irqLineIn(2) = '1') or
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                                                                                                (irqCtrl_r(1 downto 0) = "11" and irqLineIn(5) = '1')) else
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                          '0';
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        irqLineIn_s(1) <= '1' when rst_n = '1' and ((irqCtrl_r(3 downto 2) = "01" and irqLineIn(4) = '1') or
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                                                    (irqCtrl_r(3 downto 2) = "10" and irqLineIn(0) = '1') or
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                                                                                                (irqCtrl_r(3 downto 2) = "11" and irqLineIn(3) = '1')) else
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                          '0';
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        irqLineIn_s(2) <= '1' when rst_n = '1' and ((irqCtrl_r(5 downto 4) = "01" and irqLineIn(1) = '1') or
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                                                    (irqCtrl_r(5 downto 4) = "10" and irqLineIn(4) = '1') or
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                                                                                                (irqCtrl_r(5 downto 4) = "11" and irqLineIn(5) = '1')) else
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                          '0';
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        irqLineIn_s(3) <= '1' when rst_n = '1' and ((irqCtrl_r(7 downto 6) = "01" and irqLineIn(1) = '1') or
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                                                    (irqCtrl_r(7 downto 6) = "10" and irqLineIn(2) = '1') or
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                                                                                            (irqCtrl_r(7 downto 6) = "11" and irqLineIn(3) = '1')) else
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                          '0';
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        irqLineOut(0) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
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                                  ((irqCtrl_r(1 downto 0) = "01" and irqLineOut_s(0) = '1') or
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                                   (irqCtrl_r(3 downto 2) = "10" and irqLineOut_s(1) = '1')) else
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                         '0';
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        irqLineOut(1) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
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                             ((irqCtrl_r(5 downto 4) = "01" and irqLineOut_s(2) = '1') or
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                                   (irqCtrl_r(7 downto 6) = "01" and irqLineOut_s(3) = '1')) else
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                         '0';
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        irqLineOut(2) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
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                                  ((irqCtrl_r(1 downto 0) = "10" and irqLineOut_s(0) = '1') or
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                                   (irqCtrl_r(7 downto 6) = "10" and irqLineOut_s(3) = '1')) else
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                         '0';
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        irqLineOut(3) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
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                                  ((irqCtrl_r(3 downto 2) = "11" and irqLineOut_s(1) = '1') or
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                                   (irqCtrl_r(7 downto 6) = "11" and irqLineOut_s(3) = '1')) else
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                         '0';
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        irqLineOut(4) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
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                                  ((irqCtrl_r(3 downto 2) = "01" and irqLineOut_s(1) = '1') or
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                                   (irqCtrl_r(5 downto 4) = "10" and irqLineOut_s(2) = '1')) else
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                         '0';
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        irqLineOut(5) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
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                                  ((irqCtrl_r(1 downto 0) = "11" and irqLineOut_s(0) = '1') or
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                                   (irqCtrl_r(5 downto 4) = "11" and irqLineOut_s(2) = '1')) else
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                         '0';
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92 
        ------------------------------------------------------------------------------------------
93 
        --
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        --   Control register
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        --
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        ------------------------------------------------------------------------------------------
97 
 
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        ioDataOut <= irqCtrl_r when rst_n = '1' and ioInEn_n = '0' else
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                     (others => '0');
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101 2 steckol 
        update_irqCtrlReg: process(rst_n, ioInWr_n)
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        begin
103 9 steckol 
                if (rst_n = '0') then
104 2 steckol 
                        irqCtrl_r <= (others => '0');
105 9 steckol 
                else
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                        if (ioInWr_n'event and ioInWr_n = '0') then
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                                if (ioInEn_n = '0') then
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                                        irqCtrl_r <= ioDataIn;
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                                end if;
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                        end if;
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                end if;
112 2 steckol 
        end process;
113 
 
114 9 steckol 
        ------------------------------------------------------------------------------------------
115 
        --
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        --   IRQ address generation
117 
        --
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        ------------------------------------------------------------------------------------------
119 
 
120 2 steckol 
        irqAddr <= irqAddr_s;
121 9 steckol 
 
122 2 steckol 
        irq_proc : process(rst_n, irqUpd_s)
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        begin
124 
                if (rst_n = '0') then
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                        irq_s <= '0';
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127 
                        irqAddr_s    <= (others => '0');
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                        irqLineOut_s <= (others => '0');
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                else
130 9 steckol 
                        if (irqUpd_s'event and irqUpd_s = '0') then
131 2 steckol 
                                if (irqLine_s = '1') then
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                                        irq_s <= '1';
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134 
                                        if (irqLineIn_s(3) = '1') then
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                                                irqAddr_s <= "11";
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                                                irqLineOut_s <= "1000";
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                                        elsif (irqLineIn_s(2) = '1') then
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                                                irqAddr_s <= "10";
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                                                irqLineOut_s <= "0100";
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                                        elsif (irqLineIn_s(1) = '1') then
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                                                irqAddr_s <= "01";
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                                                irqLineOut_s <= "0010";
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                                        else
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                                                irqAddr_s <= "00";
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                                                irqLineOut_s <= "0001";
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                                        end if;
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                                else
148 
                                        irq_s <= '0';
149 
                                        irqLineOut_s <= (others => '0');
150 
                                end if;
151 
                        end if;
152 
                end if;
153 
        end process;
154 
 
155 
        irqLine_s <= irqLineIn_s(0) or irqLineIn_s(1) or irqLineIn_s(2) or irqLineIn_s(3);
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157 9 steckol 
        irqUpd_s <= state(3) when enable = '1' and stalled_n = '1' else
158 
                    '0'      when enable = '1' and irqLine_s = '1' else
159 
                    '1';
160 2 steckol 
 
161 
        irqAck <= irq_s;
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163 
end behavior;

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